CN102844861B - 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 - Google Patents

对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 Download PDF

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CN102844861B
CN102844861B CN201180019483.4A CN201180019483A CN102844861B CN 102844861 B CN102844861 B CN 102844861B CN 201180019483 A CN201180019483 A CN 201180019483A CN 102844861 B CN102844861 B CN 102844861B
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substrate
nude film
vias
package substrate
expansion
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CN102844861A (zh
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玛格丽特·罗丝·西蒙斯-马修斯
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Texas Instruments Inc
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Texas Instruments Inc
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    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Abstract

一种用于组装裸片封装的方法(100)包括将位于多个第一裸片的第一侧上的触点附接(101)到位于复合载体的顶部表面上的衬底垫。所述复合载体包括包含至少一个嵌入金属层的封装衬底，所述封装衬底使其底部表面紧固到半导体晶片。所述复合载体在组装期间使所述裸片与所述封装衬底之间的热膨胀系数CTE失配的效应最小化，从而减少所述裸片的翘曲。在所述附接之后，从所述封装衬底移除(103)所述半导体晶片。将导电连接器附接(104)到所述封装衬底的所述底部表面，且锯开(105)所述封装衬底以形成多个单一化裸片封装。

Description

对用于裸片翘曲减少的组装的IC封装衬底的TCE补偿
技术领域
所揭示的实施例涉及集成电路(“IC”)封装，且更明确地说，涉及裸片组装。
背景技术
如此项技术中已知的，术语“裸片接合”或“裸片附接”描述将半导体裸片附接到封装衬底或例如用于卷带自动接合的带状载体等某种其它衬底的操作。首先从经分离的晶片或华夫式(waffle)托盘拾取裸片，将其对准到载体或衬底上的目标垫，且接着进行永久性附接，这通常通过焊料或环氧树脂接合来进行。
在IC裸片组装期间的裸片附接温度通常在至少150℃的温度下执行，且可针对共晶裸片附接在375℃或更高的温度下执行。已知由于裸片与封装衬底之间的大的热膨胀系数(“CTE”)失配所造成的裸片翘曲的缘故而使得将非常薄的裸片(小于100μm厚，例如20到80μm)组装到一些封装衬底(例如有机衬底)较为困难。举例来说，在硅裸片的情况下，裸片的CTE可为约3ppm/℃，且有机衬底的CTE可为约20ppm/℃或更高。可能随温度上升而缺少刚性的薄封装衬底(例如，约100到200μm厚)可使这个问题进一步恶化。
即使微小的裸片翘曲也可在小面积和/或密集裸片触点的情况下造成对准问题和所得的裸片附接问题。未对准的接点会减小接触面积，这会增加接点的接触电阻，且可甚至造成开路触点。举例来说，与穿衬底通孔(缩写为“TSV”且在硅衬底的情况下称为穿硅通孔)相关联的触点可在面积上非常小。类似地，如果例如柱(例如，铜柱)或栓(例如，金栓)等其它接触结构变得足够小且/或足够密集，那么翘曲可变成显著问题。当一个裸片在两侧上均具有触点(例如，包含位于裸片的一侧上的倒装芯片封装衬底连接以及位于裸片的另一侧上的小面积TSV连接)时，翘曲还对于裸片堆叠来说尤其成问题。
一种已知的用于解决上述翘曲问题的方法是使用低CTE封装衬底，其提供改进的相对于裸片的CTE匹配。举例来说，陶瓷衬底和一些专门的聚合物衬底可提供改进的与裸片的CTE匹配。然而，与常规的基于环氧玻璃树脂(例如，BT树脂)的有机衬底相比，低CTE封装衬底通常显著较昂贵。需要用于在组装期间使裸片与封装衬底之间的CTE失配的翘曲和所得效应最小化以允许使用常规聚合物衬底的新型封装方法。
发明内容
所揭示的实施例描述用于在组装期间使裸片与封装衬底之间的CTE失配的效应最小化的新型封装方法，其显著地允许使用低成本的常规聚合物衬底，同时提供减小的裸片翘曲。包含包括至少一个嵌入金属层的封装衬底(其底部表面紧固到半导体晶片)的复合载体控制裸片与衬底之间的CTE失配。本发明人已经认识到，复合载体的CTE将在很大程度上由半导体载体晶片的CTE驱动，所述半导体载体晶片的CTE经选择以匹配裸片的CTE，使得不管裸片与封装衬底之间的CTE失配，封装衬底将在组装期间对ΔCTE驱动的翘曲具有极小影响。在一个实施例中，裸片和晶片载体两者均可包含硅。
封装衬底通常为聚合物衬底，例如有机衬底。在典型实施例中，封装衬底具有与裸片的CTE相比至少相差10ppm/℃(通常较高)的TCE。
可在组装过程开始之前提供复合载体。对封装衬底执行裸片附接处理，同时半导体晶片附接到其上，所述半导体晶片充当载体晶片。可稍后在组装流程中在完成所有裸片附接之后移除半导体晶片，此时对平坦的裸片表面的需要通常不再是重要的。在移除载体晶片之后，可接着将多个导电连接器(例如，BGA)附接到封装衬底的底部表面。锯开封装衬底形成多个裸片封装。
所揭示的实施例包括组装单个裸片封装以及包括两个或两个以上堆叠裸片的堆叠裸片封装。所述裸片可包括TSV裸片。
附图说明
图1展示根据本发明的原理的用于组装裸片封装的实例方法。
图2展示用于组装堆叠裸片封装的实例方法。
图3展示用于组装包括具有穿衬底通孔(TSV)的裸片的堆叠裸片封装的实例方法。
图4A到4G为说明图3的实例方法中的步骤的横截面图。
具体实施方式
图1展示用于组装裸片封装的方法100的实例实施例。步骤101包含将位于多个第一裸片的第一侧上的触点附接到位于复合载体的顶部表面上的衬底垫。可以面向下(即，倒装芯片)或面向上(即，电路侧向上)(例如，用于稍后线接合，或使用穿衬底通孔(TSV)裸片)的方式附接第一裸片。裸片(例如，对于硅裸片为约3ppm/℃)与封装衬底之间的热膨胀系数(CTE)差值大体上为至少10ppm/℃。在典型实施例中，步骤101包含经由焊料凸块回焊、铜柱、金栓或其它合适的附接方法进行的多个单一化裸片到聚合物封装衬底的裸片附接和底部填充。代替单一化裸片形式，所述多个第一裸片可以晶片形式来提供，使得将晶片附接到封装衬底。
复合载体包含包括一个或一个以上嵌入金属层的封装衬底，其在底部表面处紧固到半导体晶片。封装衬底可为聚合物衬底，例如有机衬底。封装衬底还可为陶瓷衬底或其它衬底。封装衬底可为薄封装衬底，例如厚度小于200μm(例如约100到200μm)的有机衬底。如上文所述，复合载体的CTE将在很大程度上由半导体载体晶片的CTE驱动，所述半导体载体晶片的CTE经选择以匹配裸片的CTE。因此，尽管裸片与封装衬底之间的CTE失配，在组装期间封装衬底将对ΔCTE驱动的翘曲具有极小影响。
步骤102包含任选的包覆模制步骤，其可包含用恰当材料(例如，模制化合物、粘合剂)进行包覆模制。步骤103包含从封装衬底移除半导体载体晶片。释放方法可包括热、溶剂或激光辅助式方法。步骤104包含将多个导电连接器(例如，球栅阵列(BGA))附接到封装衬底的底部表面。步骤105包括锯开封装衬底以形成多个单一化裸片封装。
图2展示根据所揭示实施例的用于组装堆叠裸片封装的实例方法200。步骤201包含将位于多个第一裸片的第一侧上的触点附接到位于复合载体的顶部表面上的衬底垫。复合载体包含包括至少一个嵌入金属层的封装衬底，其底部表面紧固到半导体晶片。在典型实施例中，步骤201包含经由焊料凸块回焊、铜柱、金栓或其它合适附接方法进行多个单一化第一裸片到聚合物封装衬底的裸片附接和底部填充。如上文所描述，所述多个第一裸片可以晶片形式来提供，使得将晶片附接到封装衬底。
在步骤202中，将多个单一化第二裸片附接到第一裸片以在封装衬底上形成多个裸片堆叠。在典型实施例中，使用焊接或铜接合来附接单一化第二裸片，且接着对其进行底部填充。
步骤203包含任选的包覆模制步骤，其可包含用恰当材料(例如，模制化合物、粘合剂)进行包覆模制。步骤204包含从封装衬底移除半导体载体晶片。如上文所描述，释放方法可包括热、溶剂或激光辅助式方法。步骤205包含将多个导电连接器(例如，BGA)附接到封装衬底的底部表面。步骤206包含锯开封装衬底以形成多个单一化堆叠裸片封装。
图3展示根据所揭示实施例的用于组装包括TSV裸片的堆叠裸片封装的实例方法300。步骤301包含附接具有嵌入TSV的多个第一TSV裸片的顶侧，其包括耦合到位于复合载体的顶部表面上的衬底垫的顶侧垫。在典型实施例中，步骤301包含经由焊料凸块回焊、铜柱或其它合适附接方法进行单一化第一TSV裸片到聚合物封装衬底的裸片附接和底部填充。所述多个第一TSV裸片可以晶片形式来提供，本文中称为TSV晶片。
在步骤302中，对所述多个第一TSV裸片进行薄化以暴露所述TSV从而提供暴露的底侧TSV区域。用于薄化的方法可包括背部研磨、化学机械抛光(CMP)和/或化学蚀刻。可接着形成通往暴露TSV区域的底侧TSV触点。步骤303包含将多个单一化第二裸片附接到第一TSV裸片的底侧TSV触点以在封装衬底上形成多个裸片堆叠。在典型实施例中，使用焊接或铜接合来附接单一化第二裸片，且接着对其进行底部填充。
步骤304包含任选的包覆模制步骤，其可包含用恰当材料(例如，模制化合物、粘合剂)进行包覆模制。步骤305包含从封装衬底移除半导体载体晶片。如上文所描述，释放方法可包括热、溶剂或激光辅助式方法。步骤306包含将多个导电连接器(例如，BGA)附接到封装衬底的底部表面。步骤307包括锯开封装衬底以形成多个单一化堆叠裸片封装。
图4A到4G展示由相对于图3所描述的实例方法中的步骤产生的连续横截面描绘。图4A为在单一化TSV裸片(展示为TSV裸片1)到粘附到半导体晶片202(例如，硅晶片)的多层衬底201的裸片附接和底部填充之后的横截面描绘，多层衬底201和半导体晶片202一起构成复合载体205。TSV裸片1被展示为以倒装芯片形式附接。TSV裸片1的顶侧垫206被展示为耦合到位于封装衬底201上的衬底垫207。TSV裸片1大体上为至少500μm厚。
图4B为展示在通过恰当方法(例如，背部研磨、CMP和/或衬底(例如，硅)蚀刻)对TSV裸片1的底侧进行薄化以形成薄化TSV裸片410从而暴露嵌入的TSV215之后的电子组合件400的横截面描绘。薄化TSV裸片1大体上为小于150μm厚，通常为20到80μm厚。TSV接触垫211(例如，铜垫)被展示为位于TSV215的暴露部分上。TSV215的至少一部分耦合到顶侧垫206。图4C为展示在经由例如焊接或铜接合等合适方法进行单一化第二裸片(展示为裸片2)到薄化TSV裸片410的裸片附接和底部填充之后的电子组合件450的横截面描绘。图4D为在用例如模制化合物或粘合剂等恰当材料425进行包覆模制之后的横截面描绘。图4E为在从聚合物封装衬底201的底部移除半导体晶片202之后的横截面描绘。在一个实施例中，裸片2为存储器裸片，且TSV裸片1为处理器裸片。虽然未图示，但额外裸片可堆叠在裸片2上。
图4F为在将BGA封装焊料球218附接到封装衬底201之后的横截面描绘。图4G为在锯开包覆模制物425和封装衬底201以单一化所述堆叠裸片封装之后的横截面描绘。
虽然上文已经将复合载体描述为在半导体晶片上包含封装衬底，但封装衬底可全部包含半导体(例如，硅，以匹配半导体裸片)以在组装过程期间实现相同的受控翘曲。
形成于顶部半导体表面上的有源电路包含大体上包括晶体管、二极管、电容器和电阻器的电路元件，以及互连这些各种电路元件的信号线和其它电导体。
所揭示的实施例可集成到用以形成多种装置和相关产品的多种过程流程中。半导体衬底可包含位于其中的各种元件和/或位于其上的各种层。这些可包括势垒层、其它电介质层、装置结构、有源元件和无源元件，其包括源极区、漏极区、位线、基极、发射极、集电极、导电线、导电通孔等。此外，所揭示的实施例可在多种工艺中使用，包括双极、CMOS、BiCMOS和MEMS工艺。
在具有所有或仅一些所述特征或步骤的实例实施例的上下文中描述的具有所述特征或步骤中的一者或一者以上的不同组合的实施例既定由此涵盖。所属领域的技术人员将了解，许多其它实施例和变型在所主张的发明的范围内也是可能的。

Claims (12)

1.一种用于组装裸片封装的方法，其包含：
将位于多个第一裸片的第一侧上的触点附接到位于复合载体的顶部表面上的衬底垫，其中所述复合载体包含包括至少一个嵌入金属层的封装衬底，所述封装衬底的底部表面紧固到半导体晶片，所述复合载体的热膨胀系数(CTE)由所述半导体晶片的热膨胀系数驱动，且所述半导体晶片的所述热膨胀系数经选择以匹配所述多个第一裸片的热膨胀系数；
在所述附接之后，从所述封装衬底移除所述半导体晶片；
将多个导电连接器附接到所述封装衬底的所述底部表面，以及
锯开所述封装衬底以形成多个单一化裸片封装。
2.根据权利要求1所述的方法，其中所述多个第一裸片包含包括穿衬底通孔的裸片；且所述触点包括通往所述穿衬底通孔的触点。
3.根据权利要求2所述的方法，其进一步包含：
对所述多个第一裸片的第二侧进行薄化以暴露所述穿衬底通孔，从而提供暴露的穿衬底通孔区域，以及
将多个单一化第二裸片附接于耦合到所述暴露区域的穿衬底通孔触点以在所述封装衬底上形成多个裸片堆叠。
4.一种用于组装堆叠裸片封装的方法，其包含：
将位于多个第一裸片的第一侧上的触点附接到位于复合载体的顶部表面上的衬底垫，其中所述复合载体包含包括至少一个嵌入金属层的封装衬底，所述封装衬底的底部表面紧固到半导体晶片，所述复合载体的热膨胀系数(CTE)由所述半导体晶片的热膨胀系数驱动，且所述半导体晶片的所述热膨胀系数经选择以匹配所述多个第一裸片的热膨胀系数；
将多个单一化第二裸片附接到所述第一裸片以在所述封装衬底上形成多个裸片堆叠；
从所述封装衬底移除所述半导体晶片；
将多个导电连接器附接到所述封装衬底的所述底部表面，以及
锯开所述封装衬底以形成多个单一化堆叠裸片封装。
5.根据权利要求4所述的方法，其中所述多个第一裸片包含具有穿衬底通孔的裸片；且所述触点包括通往所述穿衬底通孔的触点。
6.根据权利要求5所述的方法，其进一步包含：
对具有所述穿衬底通孔的所述多个第一裸片的第二侧进行薄化以暴露所述穿衬底通孔，从而提供暴露的穿衬底通孔区域，以及
将多个单一化第二裸片附接于耦合到所述暴露区域的所述穿衬底通孔触点以在所述封装衬底上形成多个裸片堆叠。
7.一种用于组装堆叠裸片封装的方法，其包含：
将具有嵌入穿衬底通孔的多个单一化穿衬底通孔裸片的顶侧附接到位于复合载体的顶部表面上的衬底垫，所述顶侧具有包括耦合到所述穿衬底通孔的顶侧垫，所述复合载体包含包括至少一个嵌入金属层的有机衬底，所述有机衬底的底部表面紧固到硅晶片，所述复合载体的热膨胀系数(CTE)由所述硅晶片的热膨胀系数驱动，且所述硅晶片的所述热膨胀系数经选择以匹配所述多个单一化穿衬底通孔裸片的热膨胀系数；
对所述多个单一化穿衬底通孔裸片的底侧进行薄化以提供暴露的穿衬底通孔区域；
在所述暴露的穿衬底通孔区域上形成底侧穿衬底通孔触点；
将多个单一化第二裸片附接到所述底侧穿衬底通孔触点以在所述有机衬底上形成多个裸片堆叠；
从所述有机衬底移除所述硅晶片；
将多个导电连接器附接到所述有机衬底的所述底部表面，以及
锯开所述有机衬底以形成多个单一化堆叠裸片封装。
8.根据权利要求7所述的方法，其中将所述多个单一化穿衬底通孔裸片安置在穿衬底通孔晶片上。
9.一种电子组合件，其包含：
复合载体，其包含包括至少一个嵌入金属层的有机封装衬底，所述有机封装衬底的底部表面紧固到半导体晶片，以及
多个第一裸片，其具有20到100μm的厚度且使其顶侧触点附接到位于所述封装衬底的顶部表面上的顶侧衬底垫，
其中所述复合载体的热膨胀系数(CTE)由所述半导体晶片的热膨胀系数驱动，且所述半导体晶片的所述热膨胀系数经选择以匹配所述多个第一裸片的热膨胀系数。
10.根据权利要求9所述的电子组合件，其中所述多个第一裸片包含包括穿衬底通孔的裸片，所述裸片使耦合到所述穿衬底通孔的所述顶侧触点附接到所述封装衬底的顶侧衬底垫。
11.根据权利要求10所述的电子组合件，其进一步包含多个单一化第二裸片，所述第二裸片附接于耦合到所述穿衬底通孔的底侧触点。
12.根据权利要求10所述的电子组合件，其中所述多个第一裸片安置在晶片上。
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