CN1497717A - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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Publication number
CN1497717A
CN1497717A CNA031603351A CN03160335A CN1497717A CN 1497717 A CN1497717 A CN 1497717A CN A031603351 A CNA031603351 A CN A031603351A CN 03160335 A CN03160335 A CN 03160335A CN 1497717 A CN1497717 A CN 1497717A
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China
Prior art keywords
conductive pattern
circuit arrangement
insulative resin
screen
hole
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CNA031603351A
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English (en)
Inventor
中村岳史
优助
五十岚优助
明
坂本则明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Publication date
Application filed by Northeast Sanyo Semi-Conductive Co Ltd, Sanyo Electric Co Ltd filed Critical Northeast Sanyo Semi-Conductive Co Ltd
Publication of CN1497717A publication Critical patent/CN1497717A/zh
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Abstract

一种电路装置及其制造方法，在电路装置10的上面形成屏蔽层14。在露出导电图案11、覆盖电路元件12、金属细线16及导电图案11的绝缘性树脂13的上面形成由铜等金属构成的屏蔽层14。在通过去除绝缘性树脂13的一部分形成的通孔20上形成连接装置15，通过连接装置15电连接屏蔽层14和导电图案11B。由于形成通孔20的位置的导电图案11B是接地电位的导电图案，故可使屏蔽层层14为零电位。

Description

电路装置及其制造方法
技术领域
本发明涉及在树脂层上面设置由导电材料构成的屏蔽层的电路装置及其制造方法。
背景技术
现在，在电子仪器上设置的电路装置由于在手机、笔记本电脑等上采用，而要求小型化、薄型化、轻量化。例如，作为电路装置以半导体装置为例进行说明，一般的半导体装置目前有由通常的传递模密封的封装型半导体。如图15，该半导体装置安装在印刷线路板PS上(例如参照专利文献1)。
该封装型半导体装置61是由树脂层63覆盖半导体芯片62的周边，并由该树脂层63的侧部导出外部连接用引线端子64的装置。但是，该封装型半导体装置61由树脂层63向外导出引线端子64，整体尺寸大，不能满足小型化、薄型化及轻量化。由此，各公司为了实现小型化、薄型化及轻量化，竞相开发各种结构，且最近开发了称为CSP(芯片尺寸封装)的和芯片尺寸相同的晶片级CSP、或比芯片尺寸大一些尺寸的CSP。
图16是显示作为支承衬底采用玻璃环氧树脂衬底65的比芯片尺寸大一些的CSP66。在此，说明在玻璃环氧树脂衬底65上安装晶体管芯片T的装置。
在该玻璃环氧树脂衬底65的表面形成第一电极67、第二电极68及小片焊盘69，在背面形成第一背面电极70和第二背面电极71。而后，介由通孔TH电连接所述第一电极67和第一背面电极70及第二电极68和第二背面电极71。另外，在小片焊盘69上固定所述裸的晶体管芯片T，介由金属细线72连接晶体管发射极和第一电极67，介由金属细线72连接晶体管基极和第二电极68。另外，在玻璃环氧树脂衬底65上设置树脂层73，以覆盖晶体管芯片T。
所述CSP66采用玻璃环氧树脂衬底65，但和晶片级CSP不同，由芯片T至外部连接用背面电极70、71的延伸结构简单，具有可便宜制造的优点。另外，如图15，所述CSP66安装在印刷线路板PS上。在印刷线路板PS上设置构成电气电路的电极、配线，电连接并固定所述CSP66、封装型半导体装置61、片状电阻CR或片状电容器CC等。由该印刷线路板构成的电路安装在各种装置中。
专利文献1
特开2001-339151号公报(第一页、图1)
但是，在所述CSP69等半导体装置中，在装置上面不实施屏蔽。因此，在CSP69周边部安装有高速数字·高频装置时有时由这些装置产生的电磁噪音，会使在CSP69内装的晶体管芯片产生误动作。另外，在CSP69上内装的晶体管芯片T由于高频而动作时，由于CSP69产生电磁波，故其有可能对在CSP69周围安装的其他装置带来不良影响。
另外，在为了屏蔽CSP69，个别地设置进行屏蔽的机构时，会妨碍装置的小型化。
发明内容
本发明是鉴于这种问题而开发的，本发明的主要目的在于，提供施行了屏蔽的电路装置及其制造方法。
本发明的电路装置，第一，包括：导电图案，其安装有电路元件；绝缘性树脂，其覆盖所述电路元件及所述导电图案，自下面使所述导电图案的背面露出；屏蔽层，其设置在所述绝缘性树脂的上面；连接装置，其电连接所述导电图案和所述屏蔽层。
第二，在绝缘性树脂上设置通孔，以使所述导电图案的表面局部露出，在所述通孔的底面及侧面形成所述连接装置。
第三，和所述屏蔽层电连接的所述导电图案是形成接地电位的导电图案。
第四，所述屏蔽层由铜等金属形成。
第五，所述屏蔽层和所述连接层由同一材料一体地形成。
第六，所述屏蔽层和所述连接层通过镀敷膜形成。
第七，所述绝缘性树脂上面形成凹凸。
本发明第八方面提供一种电路装置的制造方法，其包括如下工序：准备导电箔；在所述导电箔上形成比其厚度浅的分离槽，形成多个导电图案；在所述导电图案上固定电路元件；由绝缘性树脂模装，覆盖所述电路元件并填充所述分离槽；在所述绝缘性树脂上形成通孔，使所述导电图案露出；在所述绝缘性树脂的表面形成屏蔽层，同时，在所述通孔的侧面及底面形成连接装置；除去所述导电箔的背面，直至所述绝缘性树脂露出；通过切割所述绝缘性树脂，分离成各电路装置。
第九，所述通孔使用激光形成。
第十，所述屏蔽层及所述连接层通过镀敷法形成。
第十一，除去所述各电路装置分界线对应的位置的所述屏蔽层。
附图说明
图1是说明本发明电路装置的剖面图(A)、平面图(B)；
图2是说明本发明电路装置的剖面图；
图3是说明本发明电路装置的制造方法的剖面图；
图4是说明本发明电路装置的制造方法的剖面图；
图5是说明本发明电路装置的制造方法的剖面图；
图6是说明本发明电路装置的制造方法的剖面图；
图7是说明本发明电路装置的制造方法的剖面图；
图8是说明本发明电路装置的制造方法的剖面图；
图9是说明本发明电路装置的制造方法的剖面图；
图10是说明本发明电路装置的制造方法的剖面图；
图11是说明本发明电路装置的制造方法的剖面图；
图12是说明本发明电路装置的制造方法的剖面图；
图13是说明本发明电路装置的制造方法的剖面图；
图14是说明本发明电路装置的制造方法的剖面图；
图15是说明现有电路装置的剖面图；
图16是说明现有电路装置的剖面图；
具体实施方式
(说明电路装置10结构的第一实施例)
参照图1说明本发明电路装置10的结构等。图1(A)是电路装置10的剖面图，图1(B)是图1(A)X-X’线的平面图。
参照图1(A)及图1(B)，电路装置10具有如下的结构。即，电路装置10包括：导电图案11，其安装有电路元件12；绝缘性树脂13，其覆盖所述电路元件12及导电图案11，自下面使导电图案11的背面露出；屏蔽层14，其设置在所述绝缘性树脂13的上面；连接装置15，其电连接导电图案11和屏蔽层14。以下说明上述各构成要素。
导电图案11由铜箔等金属构成，其被露出背面埋入绝缘性树脂13。在此，导电图案11形成导电图案11A及导电图案11B，所述导电图案11A形成安装半导体元件等电路元件12的小片焊盘，所述导电图案11B为焊盘。导电图案11A配置在中央部，在其上部介由焊剂固定电路元件12。由绝缘性树脂13露出的导电图案11A的背面由抗焊剂19保护。导电图案11B包围导电图案11A在电路装置周边部配置多个，并介由金属细线16和电路元件12的电极电连接。另外，在导电图案11B的背面形成由焊锡等焊剂构成的外部电极18。另外，在导电图案11B的表面形成露出部21，在绝缘性树脂13上形成的通孔露出导电图案11B表面的一部分。
绝缘性树脂13露出导电图案11的背面而密封整体。在此，密封半导体元件13、金属细线16及导电图案11。作为绝缘性树脂13的材料可采用通过传递模形成的热固性树脂或通过注射模形成的热塑性树脂。
电路装置12是例如半导体元件，在此，IC芯片面朝上固定在导电图案11A上。电路元件的电极和导电图案11B介由金属细线16电连接。作为半导体元件的电路元件12面朝上固定，但也可面朝下固定。另外，作为电路元件12除IC芯片等之外，也可采用晶体管芯片、二极管等有源元件或片状电阻、片状电容器等无源元件。另外，也可将这些有源元件及无源元件多个配置在导电图案11上。
通孔20通过去除绝缘性树脂13的一部分形成，底部露出导电图案11B表面的一部分即露出部21。在该通孔21侧面部及露出部21形成由金属膜构成的连接装置15，其具有将在绝缘性树脂13的表面形成的屏蔽层14和形成露出部21的导电图案11B电连接的作用。另外，通孔20的形状为，平面方向的断面形成大致圆形，绝缘性树脂13表面附近的断面比露出部21附近的断面大。
屏蔽层14由同等的金属构成，其通过电解镀敷法或无电解镀敷法等形成在绝缘性树脂13的表面。屏蔽层14具有防止外部的电磁波侵入电路装置10内部给电路元件12带来不良影响的作用，还具有防止由电路元件12产生的电磁波漏到装置外部的作用。另外，屏蔽层14的表面以保护其表面为目的形成抗蚀剂层17A。
连接装置15是在通过去除绝缘性树脂13形成的通孔20的侧面及底面上形成的金属层，其具有电连接屏蔽层14和导电图案11B的作用。和屏蔽层14电连接的导电图案11B由于是成为接地电位的导电图案，故屏蔽层14的电位可为零电位，可提高屏蔽层14的屏蔽效果。另外，参照图1(A)，也可填充通孔20形成连接装置15。
所述的屏蔽层14和连接装置15通过镀敷法形成一体。通过镀敷法可在绝缘性树脂13的表面、通孔20的侧面及导电图案11B的露出部21形成均等厚度的金属层。从而，通过和屏蔽层14一体形成的连接装置15，可靠地电连接屏蔽层14和导电图案11B。
参照图2说明其他形态的电路装置10A。同图所示的电路装置10A包括如下结构：导电图案11，其安装有电路元件12；绝缘性树脂13，其覆盖电路元件12及导电图案11，自下面使所述导电图案11的背面露出；屏蔽层14，其设置在绝缘性树脂的上面；连接装置15，其电连接导电图案11和屏蔽层14，绝缘性树脂13的上面形成凹凸。这样，电路装置10的结构和图1所示的电路装置10大致相同，但在绝缘性树脂13的上面形成凹凸。以下说明该结构。
在绝缘性树脂13的上面形成凹凸部22。凹凸部22通过在绝缘性树脂13上面以一定方向形成槽而形成。另外，也可通过在绝缘性树脂13上面格子状形成槽，来形成凹凸部22。这样，通过在绝缘性树脂13上面形成凹凸部22，可使绝缘性树脂13上面的表面积增大，故可提高该位置的散热效果。
本发明的特征在于，在绝缘性树脂13上面设置屏蔽层14，将屏蔽层14和导电图案11B电连接。具体地说，在绝缘性树脂13上面形成由金属膜构成的屏蔽层14，介由通孔20上设置的连接装置15将屏蔽层14和导电图案11B电连接。从而，通过屏蔽层14可防止由外部向电路装置10内部侵入电磁波。另外，通过电连接成为接地电位的导电图案11B和屏蔽层14，可进一步地提高屏蔽层14的屏蔽效果。
另外，本发明的特征在于，介由通过消除绝缘性树脂13的一部分设置的通孔20将屏蔽层14和导电图案11B电连接。具体地说，在通孔20的侧面及由其底面露出的露出部21上形成由金属膜构成的连接装置15。连接装置15和屏蔽层14通过镀敷法等一体地形成，故屏蔽层14和导电图案11B电连接。因此，没有必要劫用于屏蔽层14和导电图案11B电连接的其他结构要素。
另外，本发明的特征在于，构成电路装置10不需要安装衬底。具体地说，电路装置10通过密封导电图案11及电路元件12等的绝缘性树脂13支承整体，成为不需要现有例中的安装衬底的结构。另外，在绝缘性树脂13上面形成的屏蔽层14介由在绝缘性树脂13上设置的通孔20与导电图案11B电连接。因此，电路装置10有非常薄的结构。
另外，在上述说明中，导电图案11具有单层的配线结构，但导电图案也可形成多层配线结构。具体地说，形成介由绝缘层形成多层的导电图案，由连接装置电连接各层导电图案，从而可实现多层的配线结构。
(说明电路装置10的制造方法的第二实施例)
在本实施例中说明电路装置10的制造方法。在本实施例中，电路装置10由如下的工序制造。即其包括如下工序：准备导电箔30；在导电箔30上形成比其厚度浅的分离槽32，形成多个导电图案11；在导电图案上固定电路元件12；由绝缘性树脂13模装，覆盖导电元件12并填充分离槽32；在绝缘性树脂13上形成通孔20，使导电图案11露出；在绝缘性树脂13的表面形成屏蔽层14，同时，在通孔20的侧面及底面形成连接装置15；除去导电箔30的背面，直至绝缘性树脂13露出；通过切割绝缘性树脂13，分离成各电路装置。以下，参照图3～图14说明本发明的各工序。
第一工序：参照图3～图5
本工序在于，准备导电箔30，在导电箔30上形成比其厚度浅的分离槽32，形成多个导电图案11。
在本工序中，如图3，首先准备片状导电箔30。该导电箔30，考虑焊剂的黏附性、接合性、镀敷性而选择其材料，作为材料采用主材料为Cu的导电箔、主材料为Al的导电箔或主材料为Fe-Ni等合金构成的导电箔等。
导电箔的厚度考虑后面的蚀刻，最好为10um～300um左右，但即使在300um以上或10um以下基本上也可以。如下所述，只要可形成比导电箔30的厚度浅的分离槽32即可。
另外，片状导电箔30以规定的宽度例如45mm卷成卷后备用，可以将其搬运到后述的各工序中，也可准备切割成规定大小的矩形状导电箔30，将其搬运到后述的各工序中。接着形成导电图案。
首先，如图4所示，在导电箔30上形成光致抗蚀剂(耐腐蚀掩膜)31，对光致抗蚀剂PR进行制图，使除去成为导电图案11的区域的导电箔30露出。
然后，参照图5，选择地蚀刻导电箔30。在此，导电图案11构成形成小片焊盘的导电图案11A和构成焊盘的导电图案11B。
第二工序：参照图6
本工序在于，在导电图案11A上固定电路元件12，并将电路元件12和导电图案11B电连接。
参照图6，介由焊剂在导电图案11A上安装电路元件12。在此，作为焊剂使用焊锡或Ag膏等导电性膏。然后，进行电路元件12的电极和规定的导电图案11A的引线接合。具体地说，将在导电图案11A上安装的电路元件12的电极和所希望的导电图案11B，通过基于热压装的球形接合及基于超声波的楔形接合一并进行引线接合。
在此，作为电路元件12是在导电图案11A上固定一个IC芯片，但也可采用IC芯片以外的元件作为电路元件12。具体地说，作为电路元件12，除IC芯片等以外，还可采用晶体管芯片、二极管等有源元件或片状电阻、片状电容器等无源元件。另外，也可将这些有源元件及无源元件多个配置在导电图案11上。
第三工序：参照图7
本工序在于，由绝缘性树脂13模装，覆盖导电元件12并填充分离槽32。
在本工序中，如图7所示，绝缘性树脂13完全覆盖电路元件12及多个导电图案11，并在分离槽32填充绝缘性树脂13，和分离槽32嵌合后牢固结合。之后，通过绝缘性树脂13支承导电图案11。另外，本工序可通过传递模、注射膜或罐封实现。作为树脂材料，环氧树脂等热固性树脂可由传递模实现，聚酰亚胺树脂、聚亚苯基硫醚等热塑性树脂可由注射膜实现。
本工序的特征是在覆盖绝缘性树脂13之前，形成导电图案11的导电箔30成为支承衬底。目前，采用本来没有必要的支承衬底形成导电图案，但是在本发明中，形成支承衬底的导电箔30作为电极材料是必需的材料。由此，具有可极其节省构成材料而工作的优点，还可实现成本的降低。
另外，由于分离槽32比导电箔的厚度更浅地形成，故导电箔30不会作为导电图案11一个个分离。因此，其特征在于，可作为片状导电箔30整体处理，模装绝缘性树脂13时，向模型的搬运、安装作业非常容易。
第四工序，参照图8
本工序在于，在绝缘性树脂13上形成通孔20，以使导电图案11露出。
在本工序中，通过去除绝缘性树脂13的一部分形成通孔20，使导电图案11B的表面露出。具体地说，通过由激光将绝缘性树脂13的一部分去除形成通孔20，使露出部21露出。在此，激光最好为二氧化碳气激光。另外，在由激光蒸发绝缘性树脂13后，在露出部21上有残渣的情况下，由过锰酸钠或过硫酸铵等进行湿式蚀刻，去除该残渣。
通过激光形成的通孔20的平面形状形成圆形。另外，通孔20的平面断面的大小越接近通孔20的底部越小。
另外，通过使用激光在绝缘性树脂13的上面设置所希望厚度的槽，可在绝缘树脂13的上面设置凹凸部。这样通过在绝缘性树脂13的上面形成凹凸可增大绝缘性树脂13的表面积，故可提高绝缘性树脂13的上面的散热效果。
第五工序，参照图9及图10
本工序在于，在绝缘性树脂13的表面形成屏蔽层14，同时在通孔20的侧面及底面形成连接装置15。
在本工序中，通过电解镀敷法或无电解镀敷法在绝缘性树脂13的上面、通孔20的侧面部及露出部21上形成由铜等金属构成的镀敷膜，构成屏蔽层14及连接装置15。在通过电解镀敷法构成镀敷膜时，使用导电箔30的背面作为电极。在图9中，在通孔20侧面部及露出部21上也形成和屏蔽层14同等厚度的镀敷膜，也可将镀敷材料填入通孔20。在将金属填入通孔20时，使用添加了添加剂的镀敷液，这样的镀敷通常称为灌封镀敷。
其次，参照图10，按各电路装置10分离在绝缘性树脂13的上面形成的屏蔽层14。具体地说，首先，除去与各电路装置10的分界线对应的部位，由抗蚀剂35覆盖屏蔽层14。然后，通过进行蚀刻，局部除去与各电路装置10的分界线对应的位置的屏蔽层14。另外，结束蚀刻后，剥离抗蚀剂35。
第六工序，参照图11～图13
本工序在于，除去导电箔30的背面，直至绝缘性树脂13露出。另外，本工序也可和上述的第五工序同时进行。
参照图11，本工序是化学地及/或物理地除去导电箔30的背面，分离为导电图案11。该工序通过研磨、研削、蚀刻、激光金属蒸发等实施。在实验中，正面湿式蚀刻导电箔30，由分离槽32露出绝缘性树脂13。其结果形成分离为导电图案11A及导电图案11B，在绝缘性树脂13上露出导电图案11的背面的结构。即，成为在分离槽32填充的绝缘性树脂13的表面和导电图案11的表面实质上一致的结构。
然后，参照图12，在绝缘性树脂13的表面及背面形成保护层。在绝缘性树脂13的上面形成由铜等金属构成的屏蔽层14，为防止屏蔽层14的氧化等，在屏蔽层14的表面涂敷抗蚀剂层17A。另外，在绝缘性树脂13背面露出导电图案11。因此，在形成外部电极18的位置形成开口部33，绝缘性树脂13的背面涂敷抗焊剂19。该开口部33通过进行曝光及显影形成。
之后，参照图13，在由开口部33露出的导电图案11B的背面形成外部电极18。具体地说，通过网印法等在开口部33涂敷、溶解焊锡等焊剂，形成外部电极18。
第七工序，参照图14
本工序在于，通过切割绝缘性树脂13分离成各电路装置。
在本工序中，通过切割与各电路装置10的分界线对应的位置的绝缘性树脂13分离成各个个别的电路装置。切割线34对应的位置的导电箔30通过由背面蚀刻导电箔的工序除去。另外，切割线34对应的位置的屏蔽层14也通过蚀刻除去。从而，在本工序中，由于进行切割的刀片仅切除绝缘性树脂13，故可最小限度地抑制刀片的消耗。
由以上的工序制造电路装置10可得到图1或图2所示的最终形状。
本发明的特征在于，在绝缘性树脂13的上面设置的屏蔽层14与将屏蔽层14和导电图案11B电连接的连接装置15一并形成。具体地说，屏蔽层14及连接装置15是一体化的镀敷膜，其通过电解镀敷法或无电解镀敷法形成。从而，可极大地抑制由形成屏蔽层14引起的工序数的增加。
另外，本发明的特征在于，使用激光在绝缘性设置13上形成通孔。具体地说，由于通过调节激光的输出可仅除去绝缘性树脂13，故可在绝缘性树脂13和导电图案11的界面停止采用激光的去除。
另外，在上述说明中，通过使用激光形成通孔20，但也可由激光以外的方法形成通孔20。具体地说，在模装绝缘性树脂13的工序中，在与绝缘性树脂13的上面接触的模型上设置对应通孔20的形状的凸部。然后，使凸部的前端部接触导电图案的表面，同时，由绝缘性树脂13进行密封，可形成该凸部的形状对应的形状的通孔20。
在本发明中可达到如下所示的效果。
第一，由于在密封电路装置10的构成要素的绝缘性树脂13的上面设置由金属层构成的屏蔽层14，故可防止电磁波侵入装置内部。另外，可防止电路装置10内装的电路装置10产生的电磁波放射到外部。
第二，由于介由在绝缘性设置13上设置的连接装置电连接接地电位的导电图案11B和屏蔽层14，故通过屏蔽层14可提高屏蔽效果。
第三，由于屏蔽层14和连接装置15由一体的镀敷膜形成，故通过设置屏蔽层14可使工序数的增加最小。

Claims (11)

1、一种电路装置，其特征在于，包括：导电图案，其安装有电路元件；绝缘性树脂，其使所述导电图案的背面露出，覆盖所述电路元件及所述导电图案；屏蔽层，其设置在所述绝缘性树脂上；连接装置，其电连接所述导电图案和所述屏蔽层。
2、如权利要求1所述的电路装置，其特征在于，在绝缘性树脂上设置通孔，以使所述导电图案的表面局部露出，在所述通孔的底面及侧面形成所述连接装置。
3、如权利要求1所述的电路装置，其特征在于，和所述屏蔽层电连接的所述导电图案是形成接地电位的导电图案。
4、如权利要求1所述的电路装置，其特征在于，所述屏蔽层由铜等金属形成。
5、如权利要求1所述的电路装置，其特征在于，所述屏蔽层和所述连接层由同一材料一体地形成。
6、如权利要求1所述的电路装置，其特征在于，所述屏蔽层和所述连接层由镀敷膜形成。
7、如权利要求1所述的电路装置，其特征在于，所述绝缘性树脂上面形成凹凸。
8、一种电路装置的制造方法，其特征在于，包括如下工序：准备导电箔；在所述导电箔上形成比其厚度浅的分离槽，形成多个导电图案；在所述导电图案上固定电路元件；由绝缘性树脂模装，覆盖所述电路元件并填充所述分离槽；在所述绝缘性树脂上形成通孔，使所述导电图案露出；在所述绝缘性树脂的表面形成屏蔽层，同时，在所述通孔的侧面及底面形成连接装置；除去所述导电箔的背面，直至所述绝缘性树脂露出；通过切割所述绝缘性树脂，分离成各电路装置。
9、如权利要求8所述的电路装置的制造方法，其特征在于，所述通孔使用激光形成。
10、如权利要求8所述的电路装置的制造方法，其特征在于，所述屏蔽层及所述连接层通过镀敷法形成。
11、如权利要求8所述的电路装置的制造方法，其特征在于，除去所述各电路装置分界线对应的位置的所述屏蔽层。
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Families Citing this family (22)

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Publication number Priority date Publication date Assignee Title
US6930377B1 (en) * 2002-12-04 2005-08-16 National Semiconductor Corporation Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages
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JP5451957B2 (ja) * 2006-02-23 2014-03-26 パナソニック株式会社 赤外線検出器
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US8362598B2 (en) * 2009-08-26 2013-01-29 Amkor Technology Inc Semiconductor device with electromagnetic interference shielding
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US20130069529A1 (en) * 2011-09-21 2013-03-21 Dudley Allan ROBERTS Electronic device containing noise shield
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US9202742B1 (en) * 2014-01-15 2015-12-01 Stats Chippac Ltd. Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof
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US20190181095A1 (en) * 2017-12-08 2019-06-13 Unisem (M) Berhad Emi shielding for discrete integrated circuit packages
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Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150351A (ja) * 1984-08-20 1986-03-12 Oki Electric Ind Co Ltd Ｅｐｒｏｍ装置
JP3324437B2 (ja) * 1997-04-04 2002-09-17 松下電器産業株式会社 多層プリント配線板の製造方法
TW410446B (en) * 1999-01-21 2000-11-01 Siliconware Precision Industries Co Ltd BGA semiconductor package

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