CN1241259C - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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CN1241259C
CN1241259C CNB011393106A CN01139310A CN1241259C CN 1241259 C CN1241259 C CN 1241259C CN B011393106 A CNB011393106 A CN B011393106A CN 01139310 A CN01139310 A CN 01139310A CN 1241259 C CN1241259 C CN 1241259C
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manufacture method
conductive foil
conductive pattern
splitter box
circuit arrangement
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CN1377219A (zh
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坂本则明
小林义幸
阪本纯次
冈田幸夫
五十岚优助
前原荣寿
高桥幸嗣
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Sanyo Electric Co Ltd
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Abstract

现有用陶瓷基板和柔软板等作为支持基板安装电路元件的电路装置。但是这些基板的厚度有成为电路装置的小型化和薄型化障碍的问题。在导电箔60上利用分离沟61形成各组件的导电图形51后,因为利用化学研磨使分离沟61的表面粗面化,所以绝缘树脂50和导电图形51结合增强,引入每个组件的切割工序,能够实现适合节省资源和大量生产的电路装置制造方法。

Description

电路装置的制造方法
技术领域
本发明涉及电路装置的制造方法,特别涉及不要支持基板的薄型电路装置的制造方法。
背景技术
以前装配在电子仪器的电路装置,为用于便携式电话和便携式计算机等,正在谋求将其小型化、薄型化和轻量化。
例如,如果以半导体装置作为电路装置为例来叙述,作为一般的半导体装置,以前有利用常规转换模具密封的封装型半导体装置。如图11所示,该半导体装置安装在印刷电路板PS上。
还有,该封装型半导体装置,利用树脂层3覆盖半导体芯片2的周围,从树脂层3的侧面引出外部连接用的引线端子4。
然而,封装型半导体装置1,因为引线端子4从树脂层3向外引出,整体尺寸大,所以不能满足小型化、薄型化和轻量化的要求。
因此,各公司争先实现小型化、薄型化和轻量化,开发各种各样的结构,最近开发出称为CSP(芯片尺寸的封装)的和芯片尺寸相等的晶片规模的CSP,或比芯片尺寸大一些的CSP。
图12表示比芯片尺寸大一些的CSP6,其采用玻璃环氧树脂基板5作为支持基板。此处说明在玻璃环氧树脂基板5装配晶体管芯片T。
在玻璃环氧树脂基板5表面,形成第1电极7、第2电极8和管芯垫片9,在背面形成第1背面电极10和第2背面电极11。然后穿过通孔TH所述的第1电极7和第1背面电极10电连接第8电极和第2背面电极。在管芯垫片9固定所述裸露的晶体管芯片T,利用金属细线12连接晶体管发射极电极和第1电极7,利用金属细线12连接晶体管基极电极和第2电极8。并且为了覆盖晶体管芯片T,在玻璃环氧树脂基板5上设置树脂层13。
所述的CSP6,采用玻璃环氧树脂基板5,和晶片规模的CSP不同,从芯片T到外部连接用的背面电极10和11的延伸结构简单,具有廉价制造的优点。
如图11所示,所述的CSP6装配在印刷电路板PS上。在印刷电路板PS上,设置构成电路的电极和布线,电连接并固定着所述的CSP6,封装型半导体装置1,芯片电阻CR或芯片电容CC等。
而且,在印刷电路板上构成的电路安装在各种组件中。
接着参照图13和图14说明CSP的制造方法。
首先,制备作为基体材料(支持基板)的玻璃环氧树脂基板5,在它两面利用绝缘粘接剂压接Cu箔20和21(参照图13A)。
接着,在对应第1电极7,第2电极8,管芯垫片9,第1背面电极10和第2背面电极11的Cu箔20和21上涂覆耐腐蚀性抗蚀剂22,使Cu箔20和21形成图形。在表面和背面形成的图形都良好(参照图13B)。
接着,利用穿孔器在玻璃换氧树脂基板上形成通孔TH的的孔,电镀该孔,形成通孔TH。利用通孔TH电连接第1电极7和第1背面电极10,第2电极8和第2背面电极11。(参照图13)
还有,省略了图面,在成为焊接端的第1电极7和第2电极8进行镀Au同时,在成为管芯焊接端的管芯垫片9进行镀Au,对晶体管芯片T进行管芯焊接。
最后,利用金属细线12连接晶体管芯片T的发射极和第1电极,晶体管芯片T的基极和第2电极8,然后涂覆树脂层13。(以上参照图13D)
利用所述的制造方法,制成采用支持基板5的CSP型电气元件。即使采用柔软板作为支持基板5,这种制造方法也同样适用。
一方面,用图14所示的流程表示采用陶瓷基板制造方法。制备作为支持基板的陶瓷基板后,形成通孔,以后利用导电膏印刷表面和背面的电极,然后进行烧结。以后,直到前述制造方法的涂覆树脂层为止,和图13所示的制造方法相同,但是陶瓷基板非常脆,和柔软基板与玻璃环氧树脂基板不同,因为容易损坏造成缺口,所以存在不能利用金属模进行模制的问题。为此,浇注封装密封树脂,硬化后对密封树脂进行平坦的研磨,最后利用切割装置单个地进行分离。
如图12所示,晶体管芯片T,连接件7~12和树脂层13和外部的连接,在晶体管的保护方面,是必要的构成要素,但是仅仅用这样的构成要素,则难于提供小型化,薄型化和轻量化的电路元件。
还有,成为支持基板的玻璃环氧树脂基板5,如上所述,本来不需要。但是在制造方法方面,为了接合电极要采用支持基板,不能没有玻璃环氧树脂基板5。
因此,由于采用玻璃环氧树脂基板5,成本上升,并且由于玻璃环氧树脂基板5厚,则电路元件变厚,使小型化,薄型化和轻量化受到限制。
还有,对于玻璃环氧树脂基板和陶瓷基板,连接两面电极的通孔形成工序一定不能缺少,存在制造工序变长的问题。
发明内容
本发明是鉴于上述许多问题而研制的,目的是提供小型化,薄型化和轻量化的电路元件,不使成本上升,且制造工序不变长。
根据本发明,提供了一种电路装置的制造方法,其特征是具有下列工序:形成导电图形的工序,制备导电箔,在除了至少形成多个电路元件的搭载部分的导电图形区域的所述的导电箔,形成比导电箔厚度浅的分离沟;化学研磨所述的分离沟表面使其表面粗糙面化的工序;在所希望的所述导电图形的所述各搭载部分固定电路元件的工序;成批地覆盖各搭载部分的所述的电路元件,填充所述的分离沟,利用绝缘性环氧树脂共同模制的工序;除去没有设置所述分离沟厚部分的所述导电箔的工序;通过在各搭载部分作分割而将所述的绝缘性环氧树脂分离的工序。
其中,在将所述电路元件固定之后,将电连接所述的各搭载部分的电路元件电极和所希望的所述的导电图形的连接件形成的工序。
其中,所述的导电箔是由铜,铝,铁-镍中的任何一种构成。
其中,用导电膜至少部分地覆盖所述的导电箔的表面。
其中,所述的导电膜是由镍,金或镀银形成。
其中,利用化学或物理腐蚀形成在所述导电箔上选择地形成的所述的分离沟。
其中,利用以有机酸为主要成分的处理液进行所述的化学研磨。
其中,利用以硫酸和过氧化氢为主要成分的处理液进行所述的化学研磨。
其中,所述的电路元件固定着半导体裸露芯片和电路零件芯片中的任何一种或两种芯片。
其中,利用引线焊接形成所述的连接件。
其中,通过转换模制粘接所述的绝缘树脂。
其中,所述的绝缘树脂用和所述的分离沟表面结合来保持固定的效果。
其中,在所述的导电箔排列多个组件,该组件以矩阵型配置至少形成多个电路元件搭载部导电图形。
其中,利用转换模制在每个组件上粘接所述的绝缘树脂。
其中,在利用所述的绝缘树脂模制的所述的每个组件上,通过切割分离成各搭载部。
其中,辨认和所述的导电图形一起形成的重合标记、并以所述重合标记作为基准进行切割。
其中,辨认和所述的导电图形一起形成的相对重合的标记、并以所述重合标记作为基准进行分割。
本发明还提供了一种电路装置的制造方法,其特征是具有下列工序:制备在除了至少形成多个电路元件的搭载部分的导电图形区域的所述的导电箔,形成比导电箔厚度浅的分离沟,并由所述分离沟形成了导电图形的所述导电箔的工序;化学研磨所述的分离沟表面使其表面粗糙面化的工序;在所希望的所述导电图形的所述各搭载部分固定电路元件的工序;成批地覆盖各搭载部分的所述的电路元件,填充所述的分离沟,利用绝缘性环氧树脂共同模制的工序;除去没有设置所述分离沟厚部分的所述导电箔的工序;通过在各搭载部分作分割而将所述的绝缘性环氧树脂分离的工序。
本发明还提供了一种电路装置的制造方法,其特征是具有下列工序:制备在除了至少形成多个电路元件的搭载部分的导电图形区域的所述的导电箔,形成比导电箔厚度浅的分离沟并由所述分离沟形成了导电图形、并且通过化学研磨所述的分离沟表面使其表面粗糙面化的工序;在所希望的所述导电图形的所述各搭载部分固定电路元件的工序;成批地覆盖各搭载部分的所述的电路元件,填充所述的分离沟,利用绝缘性环氧树脂共同模制的工序;除去没有设置所述分离沟厚部分的所述导电箔的工序;通过在各搭载部分作分割而将所述的绝缘性环氧树脂分离的工序。
在本发明中,形成导电图形的导电箔是起始材料,到模制绝缘性树脂为止导电箔具有支持性能,模制后的绝缘树脂具有支持性能,可不要支持基板,所以能够解决以前的问题。
还有,在本发明中因为化学研磨分离沟表面使其表面粗糙化,使绝缘性树脂具有固定效果,能够处理各组件,大量生产多个电路装置,所以能够解决以前的问题,
附图说明
图1是说明本发明流程的图。
图2是说明本发明电路装置制造方法的图。
图3是说明本发明电路装置制造方法的图。
图4是说明本发明电路装置制造方法的图。
图5是说明本发明电路装置制造方法的图。
图6是说明本发明电路装置制造方法的图。
图7是说明本发明电路装置制造方法的图。
图8是说明本发明电路装置制造方法的图。
图9是说明本发明电路装置制造方法的图。
图10是说明本发明电路装置制造方法的图。
图11是说明以前电路装置封装结构的图。
图12是说明以前电路装置的图。
图13是说明以前电路装置制造方法的图。
图14是说明以前电路装置制造方法的图。
具体实施方式
首先参照图1说明本发明电路制造方法。
本发明具有下列工序:形成导电图形的工序,制备导电箔,在除了至少形成多个电路元件的搭载部分的导电图形区域的所述的导电箔,形成比导电箔厚度浅的分离沟;化学研磨所述的分离沟表面使其表面粗糙化的工序;在所希望的所述导电图形的各搭载部分固定电路元件的工序;形成连接件的工序,用来电连接所述的各搭载部分的电路元件电极和所希望的所述的导电图形;为了成批地覆盖各搭载部分的所述的电路元件和填充所述的分离沟,利用绝缘性树脂共同模制的工序;除去没有所述的分离沟厚部分的所述导电膜的工序;通过在各搭载部分割所述的绝缘性环氧树脂来分离的工序。
图1所示的流程和所述的工序不同,利用Cu箔,镀Ag和不完全腐蚀3个流程形成导电图形。在化学研磨流程,化学研磨分离沟的表面。在管芯焊接和引线焊接二个流程,向各搭载部固定电路元件,连接电路元件电极和导电图形。在转换模制流程,利用绝缘性树脂共同模制。在除去背面Cu箔的流程,腐蚀没有分离沟的厚部分的导电箔。在背面处理的流程,进行在背面露出的导电图形的电极处理。在测定流程对装入各搭载部的电路元件进行良品判别和特性等级分类。在切割管芯的流程,从绝缘树脂进行切割来分离各个电路元件。
下面参照图1~图10说明本发明的各工序。
如图2~图4所示,本发明的第1工序,制备导电箔60,至少在除了形成多个电路元件52的搭载部的导电图形51的区域的导电箔60,形成比导电箔60厚度浅的分离沟61,形成导电图形51。
如图2A所示,本工序用来制备片状导电箔60。关于导电箔60,选择它的材料要考虑焊料的粘附性、焊接性和电镀性,作为材料采用把Cu作为主要材料的导电箔,把Al作为主要材料的导电箔,或由Fe-Ni等合金构成的导电箔。
如果考虑后面腐蚀,导电箔的厚度最好选择10μm~300μm,这里采用70μm(2盎司)的铜箔。但是,即使300μm以上10μm以下,也是基本良好。如以后所述那样,最好形成村比导电箔60厚度浅的分离沟61。
准备片状的导电箔60,规定的宽度例如是45mm,卷成卷状,然后可以把它传送到后述的各工序,也可以将按照规定的尺寸切成栅状的导电箔60送到后述的各工序。
具体地说,如图2B所示,在短栅状导电箔60形成多个搭载部的组件62隔离地排成4~5个。在各组件62之间设置缝隙63,用来吸收小模制工序等热处理时产生的导电箔60的应力。还有,在导电箔60的上下端按照一定间隔设置标引孔64,用于在各工序确定导电箔的位置。
接着,形成导电图形。
首先,如图3所示,在Cu箔60上形成光致抗蚀剂(耐腐蚀)PR,使光致抗蚀剂PR形成图形,以便除了导电图形51区域以外的导电箔60露出。然后如图4A所示,利用光致抗蚀剂PR选择地腐蚀导电箔60。
通过腐蚀形成的分离沟61的深度例如是50μm,它的侧面因为变成粗面,所以提高了和绝缘树脂50的粘接性。
分离沟61的侧壁虽然用直线模式地图示,但是除去的方法不同可能有不同的结构。该除去工序能够采用湿腐蚀,干腐蚀,激光蒸发和切割方法。在湿腐蚀情况,主要采用氯化二铁或氯化二铜进行腐蚀,把所述的导电箔浸入在腐蚀液中,用该腐蚀液进行喷射。这里的腐蚀液一般进行非各向非异性的腐蚀,所以把侧面腐蚀成弯曲结构。
在干腐蚀情况,可能进行各向异性,非各向异性的腐蚀。现在据说利用反应性离子腐蚀不能除去Cu,但是用溅射能够除去Cu。还有,根据溅射的条件能够进行各向异性,非各向异性的腐蚀。
还有,用激光器直接照射激光形成分离沟61,此时所说到的那个分离沟61的侧面形成直面。
在图3也可以选择性地覆盖对腐蚀液耐腐蚀的某种导电膜(没有图示)来代替光致抗蚀剂。如果选择地覆盖电路部分,该导电膜成为腐蚀保护膜,能够不用抗蚀剂来腐蚀分离沟。考虑作为这种导电膜的材料有Ag,Ni,Au,Pt,或Pd等。而且,这些耐蚀性的导电膜的特征是,能够按照原样用作管芯焊盘和焊点。
例如,Ag膜和Au连接,也和焊料连接。因此如果在芯片背面覆盖金膜,能够照原样在电路51的Ag膜上热压芯片,就能够利用焊锡等焊料固定芯片。因为Au细线连接着Ag导电膜,所以可能用导线焊接。因此具有这样的优点,能够使这些导电膜按照原样用作管芯焊盘和焊点。
图4B表示具体的导电图形51。该图表示图2B所示的组件62中的一个被扩大了的图形。涂黑部分的一个是一个搭载部分65,构成导电图形51,一个组件62以5行10列的矩阵形状排列多个搭载部分65,在每个搭载部分65上设置同一导电图形51。各组件的周边设置成方框形状的图形66,与其离开一些并其内侧处设置切割时对照位置的标记67。框状图形66用作和模制金属膜的嵌合,在导电箔60背面腐蚀后,具有使绝缘树脂50加强的作用。
本发明的第2工序,如图5所示,化学研磨分离沟61,使其表面粗糙化。
本工序在形成分离沟61后,利用以硫酸-过氧化氢为主要成分的处理液进行处理,使分离沟61表面粗糙化。采用メツク(株)制CB-801作为处理液,在腐蚀液中浸入数分钟,在表面形成1~2μm的凹凸的活性表面。因此增加分离沟61壁面的面积。在后续的工序,能够加强和模制绝缘树脂50的结合强度,获得好的固定效果。
本发明还有这样的方法,即用有机酸系的腐蚀处理液,化学研磨粗化分离沟61的壁面。采用メツク(株)制CZ-8100作为有机酸系的腐蚀处理液,在腐蚀液中浸入数分钟,在表面形成1~2μm的凹凸表面。因此,比所述的硫酸-过氧化氢腐蚀液获得更好的固定效果。但是,必须选择不损害导电图形51表面的处理液。
还有,除了所述的方法以外,在黑化处理后也能够采用等离子体腐蚀方法。
本发明的第3工序,如图6所示,在所希望的导电图形51的各搭载部65上固定电路元件52,形成电连接各搭载部65的电路元件52的电极和所希望的导电图形51的连接构件。
作为电路元件52有晶体管,二极管、IC芯片等半导体元件,电容芯片和电阻芯片等无源元件。虽然厚度变厚但是也能够安装CSP,BGA等面朝下的半导体元件。
这里把裸露的晶体管芯片52A连接在导电图形51A上,利用热压球形焊接或超声波楔形焊接等固定用的金属细线52A连接发射极电极和导电图形51B,基极电极和导电图形51B。52B是电容芯片或无源元件,用焊锡等焊料或导电膏55固定。
本工序因为在各组件62集成多个导电图形51,所以具有极高效率地固定电路元件52和焊接引线的优点。
本发明的第4工序,如图7所示,用绝缘性树脂50,以便成批的覆盖各搭载部63的电路元件52,填充分离沟61共同模。
本工序如图7所示,绝缘树脂50完全覆盖电路元件52A,52B,和多个导电图形51A,51B,51C,在导电图形51之间的分离沟61填充绝缘树脂50,获得和导电图形51A,51B,51C侧面的粗糙面结合的坚固的固定效果。所以利用绝缘树脂50能够支持导电图形51。
本工序可通过转换模制、注入模制或浸渍实现本工序。作为树脂材料,环氧树脂等的热硬化性树脂能用转换模制实现,聚酰亚胺树脂、对聚苯硫等热可塑性树脂可用注入模实现。
还有,本工序在进行转换模制或注入模制时,如图7B所示,各组件62放入一个共用的模制用的金属模的搭载部63,利用1个绝缘树脂50在各组件进行共同的模制。因此,和以前转换模制等情况分别模制各搭载部的方法相比,大幅度地减少树脂量。
调整覆盖在导电箔60表面的绝缘树脂50厚度,以便离电路元件52的金属细线55A最顶部约100μm。如考虑强度,该厚度可能厚,也可能薄。
本工序的特征是,到覆盖绝缘树脂50为止,形成导电图形51的导电薄60变成支持基板。以前,象图13那样利用没有必要的支持基板5形成电路7~11,在本发明成为支持基板的导电薄60是作为电极材料的必要材料。为此,具有用极省构成材料进行制造的优点。也实现降低成本。
分离沟61因为形成的厚度比导电箔的厚度浅,所以作为导电图形51不各自分离导电箔60。因此,作为片导电箔60进行整体处理模制绝缘树脂50时,具有向换金属模型的搬运和安装的制作非常容易的特征。
本发明的第5工序,如图7所示,除去没有设置分离沟61厚部分的导电箔60。
本工序用化学和/或物理方法除去导电箔60的背面,分离导电图形51。利用研磨,磨削,腐蚀和激光的金属蒸发等进行该工序。
在试验中利用研磨装置或磨削装置把整个面削去30μm,从分离沟61露出绝缘树脂50。在图7中用虚线表示露出面。结果分离成大约40μm厚的导电图形51。也可以在露出绝缘树脂50之前整面地湿腐蚀导电箔60,以后,利用研磨装置或磨削装置削去整面露出绝缘树脂50。还有,也可以到点线为止整面地湿腐蚀导电箔60直到虚线的位置,使绝缘树脂50露出。
结果,变成使导电图形51背面露出绝缘树脂50的构造。也就是,填充在分离沟61的绝缘树脂50表面和导电图形51的表面,成为实质上一致的构造。因此,本发明电路装置5的特征是,因为不设置如图12所示以前电极10和12那样的段差,安装时由于焊锡等表面张力的作用能够在原来位置水平地移动自己调整。
接着,对导电图形51进行背面处理,获得如图8所示的最终构造。也就是,按照要求在露出的导电图形51上涂覆焊锡等导电材料,制成电路装置。
本发明的第6工序,如图9所示,对用绝缘树脂50成批地模制各搭载部63的电路元件52的特性进行测试。
在前述工序腐蚀导电箔60背面后,从导电箔60切离各组件62。该组件62因为用绝缘树脂50连接导电箔60的残余部,所以能够不用切断金属膜的机械地剥离导电箔60的残余部。
各组件62的背面,如图9所示,露出导电图形51的背面,各搭载部65在形成导电图形51时排列成完全相同的矩阵形状。把把组件68触及在从导电图形51的绝缘树脂50露出的背面电极56上,分别测定各搭载部65的电路元件52的特性参数,判断是否良品,如果是不良品则用磁性墨水等打上标记。
在本工序,各搭载部65的电路装置53,因为用绝缘树脂50整体地支持组件62,所以没有单个分散地分离。因此,在测试仪载置台上放置的组件62按照搭载部65的尺寸分根据箭头所指的纵方向和横方向依一定间距移动,非常快地大量测定组件62的各搭载部65的电路装置53。也就是,对于以前必须进行对电路装置表面和背面的判别,电极位置的识别等能够不再进行,则大大地缩短了测定的时间。
如图10所示,本发明的第7工序,通过在各搭载部65切割绝缘树脂50而分离。
在本工序,在切割装置的载置台上真空吸附组件62,利用切割刀片69沿各搭载部65之间的切割线70切割分离沟61的绝缘树脂50,分离成各电路装置53。
在本工序,利用切割刀片69进行深削,大致切断绝缘树脂50,从切割装置取出组件62后用滚子形成巧克力片。切割时和所述的第1工序设置的各组件周边框状导电图形66整体的相对位置对合,找到标记67并且和它对准,然后进行切割。虽然众所周知,但是切割要全部沿纵方向的切割线70切割后,再把置载台回转90度按横方向切割线70进行切割。
发明的效果
本发明具有把构成导电图形材料的导电箔本体作为支持基板的功能,直到形成分离沟或安装电路元件、覆盖绝缘树脂时由导电箔支持整体,并且分离导电箔形成各导电图形时,具有把绝缘树脂作为支持基板的功能。因此,能够在电路元件,导电箔,和绝缘树脂的必要下限进行制造。例如用以前例说明,构成原来电路装置可以不要支持基板,这样能够减低成本。并且通过不要支持基板、把导电图形埋入绝缘树脂50中、而且还可能调整绝缘树脂和导电箔的厚度,具有能形成非常薄电路装置的优点。
在本发明,分离沟即使比大约为50μm浅,通过用化学研磨使其表面粗糙化,绝缘树脂和各导电膜结合加强,虽然是非常薄的电路装置,但是用绝缘树脂的电路元件密封良好。
其次,本发明在绝缘树脂的模制工序,由于共同模制每个组件,所以大量减少树脂量。
还有,在切割工序,由于利用位置配合的标记,所以具有很快确认切割线的优点。并且切割时可以只切断绝缘树脂层而不切断导电箔,因此能够延长切割片的寿命,也不发生在需要切断导电箔的情况产生的金属毛刺。
由图13可知,因为省略了通孔形成工序、导体印刷等工序(陶瓷基板的情况),使现有的制造工序大大的缩短,具有内作全部工序的优点。还有,由于完全不要框架金属模,所以是极短交付期的制造方法。

Claims (16)

1.一种电路装置的制造方法,其特征是具有下列工序:
形成导电图形的工序,制备导电箔,在除了至少形成多个电路元件的搭载部分的导电图形区域的所述的导电箔,形成比导电箔厚度浅的分离沟;
化学研磨所述的分离沟表面使其表面粗糙面化的工序;
在所希望的所述导电图形的所述各搭载部分固定电路元件的工序;
成批地覆盖各搭载部分的所述的电路元件,填充所述的分离沟,利用绝缘性树脂共同模制的工序;
除去没有设置所述分离沟厚部分的所述导电箔的工序;
通过在各搭载部分作分割而将所述的绝缘性树脂分离的工序。
2.按照权利要求1所述的电路装置的制造方法,其特征是具有:
在将所述电路元件固定之后,将电连接所述的各搭载部分的电路元件电极和所希望的所述的导电图形的连接件形成的工序。
3.按照权利要求1或2所述的电路装置的制造方法,其特征是,
所述的导电箔是由铜,铝,铁-镍中的任何一种构成。
4.按照权利要求1或2所述的电路装置的制造方法,其特征是,
用导电膜至少部分地覆盖所述的导电箔的表面。
5.按照权利要求4所述的电路装置的制造方法,其特征是,
所述的导电膜是由镍,金或镀银形成。
6.按照权利要求1或2所述的电路装置的制造方法,其特征是,
利用化学或物理腐蚀形成在所述导电箔上选择地形成的所述的分离沟。
7.按照权利要求1或2所述的电路装置的制造方法,其特征是,
利用以有机酸为主要成分的处理液进行所述的化学研磨。
8.按照权利要求1或2所述的电路装置的制造方法,其特征是,
利用以硫酸和过氧化氢为主要成分的处理液进行所述的化学研磨。
9.按照权利要求1或2所述的电路装置的制造方法,其特征是,
所述的电路元件固定着半导体裸露芯片和电路零件芯片中的任何一种或两种芯片。
10.按照权利要求2所述的电路装置的制造方法,其特征是,
利用引线焊接形成所述的连接件。
11.按照权利要求1或2所述的电路装置的制造方法,其特征是,
通过转换模制粘接所述的绝缘树脂。
12.按照权利要求11所述的电路装置的制造方法,其特征是,
所述的绝缘树脂用和所述的分离沟表面结合来保持固定的效果。
13.按照权利要求1或2所述的电路装置的制造方法,其特征是,
在所述的导电箔排列多个组件,该组件以矩阵型配置至少形成多个电路元件搭载部导电图形。
14.按照权利要求13所述的电路装置的制造方法,其特征是,
利用转换模制在每个组件上粘接所述的绝缘树脂。
15.按照权利要求13所述的电路装置的制造方法,其特征是,
在利用所述的绝缘树脂模制的所述的每个组件上,通过切割分离成各搭载部。
16.按照权利要求15所述的电路装置的制造方法,其特征是,
辨认和所述的导电图形一起形成的位置重合标记、并以所述位置重合标记作为基准进行切割。
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Families Citing this family (23)

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Publication number Priority date Publication date Assignee Title
JP2004186460A (ja) * 2002-12-04 2004-07-02 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004207277A (ja) * 2002-12-20 2004-07-22 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP4446772B2 (ja) 2004-03-24 2010-04-07 三洋電機株式会社 回路装置およびその製造方法
JP4857594B2 (ja) * 2005-04-26 2012-01-18 大日本印刷株式会社 回路部材、及び回路部材の製造方法
TW200721216A (en) * 2005-09-22 2007-06-01 Murata Manufacturing Co Packaging method of electronic component module, method for manufacturing electronic apparatus using it, and electronic component module
JP4503039B2 (ja) 2006-04-27 2010-07-14 三洋電機株式会社 回路装置
JP5091600B2 (ja) 2006-09-29 2012-12-05 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2008187045A (ja) * 2007-01-30 2008-08-14 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームとその製造方法、半導体装置
JP5550102B2 (ja) * 2008-01-17 2014-07-16 株式会社村田製作所 電子部品
KR20100103015A (ko) * 2009-03-12 2010-09-27 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
CN102170748B (zh) * 2010-02-26 2013-03-27 佳必琪国际股份有限公司 贴合式软性电路板、其制作方法及具有该电路板的条灯
JP5678980B2 (ja) * 2013-03-18 2015-03-04 大日本印刷株式会社 回路部材の製造方法
JP6362111B2 (ja) * 2014-12-01 2018-07-25 大口マテリアル株式会社 リードフレームの製造方法
JP6537136B2 (ja) * 2015-06-16 2019-07-03 大口マテリアル株式会社 Ledパッケージ及び多列型led用リードフレーム、並びにそれらの製造方法
JP6525259B2 (ja) * 2015-06-22 2019-06-05 大口マテリアル株式会社 Ledパッケージ及び多列型led用リードフレーム、並びにそれらの製造方法
JP6191664B2 (ja) * 2015-08-21 2017-09-06 大日本印刷株式会社 半導体装置の多面付け体および半導体装置
JP6593842B2 (ja) * 2016-03-16 2019-10-23 大口マテリアル株式会社 Ledパッケージ並びに多列型led用リードフレーム及びその製造方法
JP6593841B2 (ja) * 2016-03-16 2019-10-23 大口マテリアル株式会社 Ledパッケージ並びに多列型led用リードフレーム及びその製造方法
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JP7068640B2 (ja) * 2017-08-01 2022-05-17 大日本印刷株式会社 リードフレームおよび半導体装置の製造方法
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