CN1509134A - 电路装置、电路模块及电路装置的制造方法 - Google Patents

电路装置、电路模块及电路装置的制造方法 Download PDF

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Publication number
CN1509134A
CN1509134A CNA2003101181631A CN200310118163A CN1509134A CN 1509134 A CN1509134 A CN 1509134A CN A2003101181631 A CNA2003101181631 A CN A2003101181631A CN 200310118163 A CN200310118163 A CN 200310118163A CN 1509134 A CN1509134 A CN 1509134A
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China
Prior art keywords
conductive pattern
circuit
circuit arrangement
insulative resin
circuit element
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CNA2003101181631A
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Inventor
�д��ʷ
中村岳史
五十岚优助
坂本则明
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1509134A publication Critical patent/CN1509134A/zh
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Abstract

一种电路装置、电路模块及电路装置的制造方法，在电路装置10上面设置第二导电图案14，进行三维安装。在密封内装的第一电路元件12等的绝缘性树脂13上面设置第二导电图案14，由连接装置15将第一导电图案11和第二导电图案14电连接。在第二导电图案14上安装第二电路元件22。由此，可三维安装构成电路的元件。另外，由于电路装置10不需要安装衬底，故形成薄型的电路装置。

Description

电路装置、电路模块及电路装置的制造方法
技术领域
本发明涉及利用在树脂层上面形成导电图案，三维安装第一电路元件的电路装置及其制造方法。
背景技术
近年来，电子设备上安装的电路装置由于在手机、笔记本电脑等上采用，故要求小型化、薄型化及轻量化。例如，当作为电路装置将半导体装置作为例子说明时，作为一般的半导体装置目前有采用通常的传递膜密封的封装型半导体装置。如图18，该半导体装置被安装在印刷线路板PS上(例如，参照专利文献1)。
该封装型半导体装置61由树脂层63覆盖半导体芯片62的周围，且自该树脂层63侧部导出外部连接用引线端子64。但是，该封装型半导体装置61由于引线端子64自树脂层63向外部引出，故整体尺寸大，不能满足小型化、薄型化及轻量化。因此，各公司竞相为实现小型化、薄型化及轻量化开发各种结构，最近，正在开发被称作CSP(芯片尺寸封装)的，和芯片尺寸相同的晶片级CSP或比芯片尺寸大若干尺寸的CPS。
图19是显示作为支撑衬底采用玻璃环氧树脂衬底65的比芯片尺寸稍大的CSP66。在此说明在玻璃环氧树脂衬底65上安装晶体管芯片T的CSP。
在该玻璃环氧树脂衬底65表面形成第一电极67、第二电极68及垫板69，在背面形成第一背面电极70和第二背面电极71。而后，介由通孔T电连接所述第一电极67和第一背面电极70、第二电极68和第二背面电极71。另外，在垫板69上固定所述裸的晶体管芯片T，介由金属细线72连接晶体管发射极和第一电极67，介由金属细线72连接晶体管基极和第二电极68。然后，在玻璃环氧树脂衬底65上设置树脂层73，以覆盖晶体管芯片T。
所述CSP66采用玻璃环氧树脂衬底65，但和晶片级CSP不同，自芯片T向外部连接用背面电极70、71的延伸结构简单，具有可便宜制造的优点。另外，如图18，所述CSP66被安装在印刷线路板PS上。在印刷线路板PS上设置形成电气电路的电极、配线，电连接所述CSP66、封装型半导体装置61、片状电阻CR或片状电容器CC等，并固定。由该印刷线路板构成的电路被安装在各种装置中。
专利文献：特开2001-339151号公报(第1页、图1)
发明内容
但是，所述的CSP等半导体装置，由于晶体管芯片T没有在树脂层73表面设置图案，故半导体装置的三维安装有困难。从而，为将多个半导体装置安装在印刷线路板PS上，必须平面安装半导体装置，这会引起印刷线路板PS的大型化。
本发明是鉴于这样的问题产生的，本发明的主要目的在于，提供一种电路装置、电路模块及电路装置的制造方法，通过在封装内装的第一电路元件的树脂表面设置导电图案，而具有立体的安装结构。
本发明的电路装置包括：第一导电图案，其安装有第一电路元件；绝缘性树脂，其至少覆盖所述第一电路元件及所述第一导电图案；第二导电图案，其设置在所述绝缘性树脂上面；连接装置，其电连接所述第一导电图案和所述第二导电图案，设置在通孔底面及侧面，所述通孔设置为使所述第一导电图案表面局部露出；第二电路元件，其安装在所述第二导电图案上。
这样，通过在密封第一电路元件的绝缘性树脂的上面形成第二导电图案，安装第二电路元件，可三维地进行元件的配置，因此，可提高安装密度。
另外，本发明的电路模块包括第一电路装置和第二电路装置，其中，第一电路装置包括：第一导电图案，其安装有第一电路元件；绝缘性树脂，其至少覆盖所述第一电路元件；第二导电图案，其设置在所述绝缘性树脂上面；连接装置，其电连接所述第一导电图案和所述第二导电图案；外部电极，其设置在所述第一导电图案背面，所述第二电路装置和所述第一电路装置具有相同结构，介由所述第一电路装置具有的外部电极利用迭层结构在所述第二电路装置上部固定所述第一电路装置。
如上所述，通过介由绝缘性树脂上面形成的第二导电图案，使第一电路装置和第二电路装置形成迭层结构，可三维地配置内装LSI等半导体元件的电路装置。
本发明电路装置的制造方法包括：形成第一导电图案的工序；在所述第一导电图案上固定第一电路元件的工序；由绝缘性树脂进行模装，至少覆盖所述第一电路元件的工序；在所述绝缘性树脂上形成通孔，以使所述第一导电图案露出的工序；在所述绝缘性树脂表面形成第二导电图案，并在所述通孔侧面及底面形成连接装置的工序；在所述第二导电图案上安装第二电路元件的工序；通过切割所述绝缘性树脂，分离为各电路装置的工序。
如上所述，通过使在绝缘性树脂上面形成的第二导电图案和连接装置同时形成，可尽可能减少工时，形成进行三维配置的导电图案。
附图说明
图1是说明本发明电路装置的剖面图(A)、平面图(B)、平面图(C)；
图2是说明本发明电路装置的平面图；
图3是说明本发明电路模块的剖面图；
图4是说明本发明电路装置制造方法的剖面图；
图5是说明本发明电路装置制造方法的剖面图；
图6是说明本发明电路装置制造方法的剖面图；
图7是说明本发明电路装置制造方法的剖面图；
图8是说明本发明电路装置制造方法的剖面图；
图9是说明本发明电路装置制造方法的剖面图；
图10是说明本发明电路装置制造方法的剖面图；
图11是说明本发明电路装置制造方法的剖面图；
图12是说明本发明电路装置制造方法的剖面图；
图13是说明本发明电路装置制造方法的剖面图；
图14是说明本发明电路装置制造方法的剖面图；
图15是说明本发明电路装置制造方法的剖面图；
图16是说明本发明电路装置制造方法的剖面图；
图17是说明本发明电路装置制造方法的剖面图；
图18是说明现有电路装置的剖面图；
图19是说明现有电路装置的剖面图。
具体实施方式
说明电路装置10结构的第一实施例
参照图1说明本发明电路装置10的结构等。图1(A)是电路装置10的剖面图，图1(B)是俯视图，图1(C)是在图1(A)X-X’线的平面图。
参照图1(A)～图1(C)，电路装置10具有如下结构，包括：第一导电图案11，其安装第一电路元件12；绝缘性树脂13，其至少覆盖第一电路元件12及第一导电图案；第二导电图案14，其设置在绝缘性树脂13上面；连接装置15，其电连接第一导电图案11和第二导电图案14；第二电路元件22，其安装在所述第二导电图案14上。以下说明这样的各构成要素。另外，所述的第一导电图案可形成单层或单层的配线结构，在此说明单层的配线结构。
第一导电图案11由铜箔等金属构成，使其背面露出，埋入绝缘性树脂13上。在此，第一导电图案11构成形成安装作为半导体元件等的第一电路元件12的垫板的第一导电图案11A和作为焊盘的第一导电图案11B。第一导电图案11A被配置在中央部，在其上部介由焊剂固定第一电路元件12。自绝缘性树脂13露出的第一导电图案11A的背面利用抗焊剂19保护。第一导电图案11B为多个配置在电路装置的周围，包围第一导电图案11A，介由金属细线16和第一电路元件12的电极电连接。另外，在第一导电图案11B的背面形成由焊锡等焊剂构成的外部电极18。然后，在第一导电图案11B的表面形成露出部21，在绝缘性树脂13上形成的通孔露出第一导电图案11B表面的一部分。
在此，第一导电图案的侧面被示意性地直线描绘，但实际上是弯曲地形成，在弯曲形成的第一导电图案11的侧面和绝缘性树脂13之间产生锚固效应，两者被紧固地结合。
绝缘性树脂13使第一导电图案11的背面露出而整体密封。在此，将半导体元件13、金属细线16及第一导电图案11密封，也具有支撑整体的作用。从而，本发明的电路装置不需要支撑衬底而构成。另外，作为绝缘性树脂13的材料，可采用利用传递膜形成的热硬性树脂或利用注入膜形成的热塑性树脂。
第一电路元件12例如是半导体元件，在此，IC芯片利用面朝上结合法被固定在第一导电图案11A上。第一电路元件的电极和第一导电图案11B介由金属细线16电连接。半导体元件第一电路元件12由面朝上结合法固定，但也可以由面朝下结合法固定。另外，作为第一电路元件12，除IC芯片等以外，也可以采用晶体管芯片、二极管等有源元件或片状电阻、片状电容器等无源元件。另外，也可以将多个这些有源元件及无源元件配置在第一导电图案11上。
通孔23通过钻削绝缘性树脂13的一部分形成，在底部露出作为第一导电图案11B表面一部分的露出部21。在该通孔20的侧面部分及露出部21上形成由金属模构成的连接装置15，其具有电连接绝缘性树脂13表面形成的第二导电图案14和形成露出部21的第一导电图案11B的作用。另外，通孔20的形状大致圆形地形成平面方向的剖面，并且，绝缘性树脂13表面附近的剖面比露出部21附近的剖面更大地形成。
第二导电图案14由铜等金属形成，利用电解电镀法或无电解镀敷法在绝缘性树脂13上面形成。利用连接装置15电连接第二导电图案14和第一导电图案11。另外，参照图1(B)，第二导电图案14形成安装四个第二电路元件22这样的图案。
第二电路元件22介由焊剂被固定在绝缘性树脂13表面形成的第二导电图案14上。作为第二电路元件22，可采用片状电阻或片状电容器等无源元件，另外，作为第二电路元件22也可在第二导电图案14上安装LSI芯片或晶体管等。
连接装置15是在通过钻削绝缘性树脂13形成的通孔20的侧面及底面上形成的金属层，具有电连接第一导电图案11和第二导电图案14的作用。另外，参照图1(A)，也可充填通孔20形成连接装置15。
所述的第二导电图案14和连接装置15利用电镀法作为一体形成。利用电镀法可在绝缘性树脂13的表面、通孔20的侧面及第一导电图案11B的露出部分21上形成均等厚度的金属层。从而，利用和屏蔽层14一体形成的连接装置15可靠地电连接第一导电图案11和第二导电图案14。
参照图2说明在绝缘性树脂13上面设置屏蔽层14A时的电路装置10的结构。在此，在绝缘性树脂13上面设置第二导电图案14，在其它部分的绝缘性树脂13上面设置屏蔽层14A。屏蔽层14A和第二导电图案14电分离，具有抑制电磁波自外部进入的作用。另外，屏蔽层14A介由连接装置15和第一导电图案11电连接，形成接地电位，可更加提高其屏蔽效应。
参照图3说明图1显示的电路装置被形成迭层结构的电路模块5的结构。
电路模块5具有如下结构，其包括第一电路装置10A和具有与第一电路装置相同结构的第二电路装置10B，其中，第一电路装置10A包括：第一导电图案11，其安装第一电路元件12；绝缘性树脂13，其至少覆盖第一电路元件12；第二导电图案14，其设置在绝缘性树脂13上面；连接装置15，其电连接第一导电图案11和第二导电图案14；外部电极18，其设置在第一导电图案11背面，构成介由第一电路装置10A具有的外部电极18在第二电路装置10B上部利用迭层结构固定第一电路装置10A的结构。
如上所述，在此，第一及第二电路装置10A、10B介由外部电极18利用迭层结构固定。从而，在第二电路装置10B的绝缘性树脂13上面设置的第二导电图案14与第一电路装置10A具有的外部电极18的位置相对应。
在此，是利用迭层结构固定两个电路装置10，但也可以层积更多个电路装置10，由此，可更加提高安装密度。
参照图4，说明形成多层第一导电图案11的电路装置10C的结构。在此说明的电路装置10C具有和参照图1说明的电路装置10类似的结构，第一导电图案11形成多层。
第一导电图案11介由层间绝缘膜23多层层积，上层的第一导电图案11介由金属细线16和第一电路元件12电连接，在下层第一导电图案11的所希望位置形成外部电极18。上部的第一导电图案11介由连接装置15和第二导电图案14电连接。在此，第一导电图案具有两层配线结构，但也可以形成更多层的配线结构。
本发明的特征在于，在覆盖第一电路元件12的绝缘性树脂13上面设置第二导电图案。由此，如图1所示，在第二导电图案14上固定第二电路元件22，可实现三维的安装结构。另外，如图3所示，介由第二导电图案14可以以迭层结构安装多个电路装置10。从而可提高安装密度。
另外，本发明的特征在于，介由通过钻削绝缘性树脂13的一部分设置的通孔20电连接第二导电图案14和第一导电图案11。具体地说，在自通孔20的侧面及其底面露出的露出部21上形成由金属膜构成的连接装置15。由于连接装置15和第二导电图案14利用电镀法等整体地形成，故第一导电图案11和第二导电图案14被电连接。由此，没有必要追加用于电连接两者的其它结构要素。
另外，本发明的特征在于，不需要安装衬底而构成电路装置10。具体地说，电路装置10由密封第一导电图案11及第一电路元件12等的绝缘性树脂13整体支撑，形成不需要现有例中的安装衬底的结构。从而，电路装置10可形成非常薄型的结构，抑制了装置厚度的增加，可进行三维安装。
说明电路装置10制造方法的第二实施例
在本实施例中，电路装置10由以下这样的工序制造。这些工序包括：形成第一导电图案11的工序；在第一导电图案11上固定第一电路元件12的工序；由绝缘性树脂13模制，以至少覆盖第一电路元件的工序；在绝缘性树脂13上形成通孔，以露出第一导电图案11的工序；在绝缘性树脂13表面形成第二导电图案14，且在通孔20的侧面及底面形成连接装置15的工序；在第二导电图案14上安装第二电路元件22的工序；通过切割绝缘性树脂13分离为各电路装置10的工序。以下参照图5～图17说明本发明的各工序。在此，说明第一导电图案11为单层配线结构时的电路装置的制造方法。第一导电图案11是多层的配线结构时，除形成第一导电图案11的工序以外其它工序也相同。
第一工序：参照图5～图7
本工序是形成第一导电图案11的工序。在此，说明形成具有单层配线结构的第一导电图案11的方法。具体地说，准备导电箔30，在导电箔30上形成比其厚度薄的分离槽32，形成多个第一导电图案11。
在本工序中，首先如图5，准备片状导电箔30。该导电箔30考虑焊剂的黏附性、接合性、电镀性选择其材料，材料采用以Cu作为主材料的导电箔、以Al作为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。
导电箔的厚度考虑到以后的蚀刻，最好为10um～300um左右，但在300um以上或10um以下也基本可以。如后所述，只要能形成比导电箔30的厚度浅的分离槽32即可。另外，片状导电箔30可以以规定宽度例如45mm卷成筒装备用，将其运送到后述的各工序中，也可以准备切割成规定大小的矩形导电箔30，并运送到后述的各工序中。然后形成导电箔。
首先，如图6所示，在导电箔30上形成光致抗蚀剂层(耐蚀刻掩模)31，将光致抗蚀剂层PR构图，以使除去作为第一导电图案11的区域的导电箔30露出。
而后，参照图7，选择性地蚀刻导电箔30。在此，第一导电图案11构成形成垫板的第一导电图案11A和形成焊盘的第一导电图案11B。
第二工序：参照图8
本工序在于，在第一导电图案11上固定第一电路元件12。
参照图8，介由焊剂在第一导电图案11A上安装第一电路元件12，在此，作为焊剂使用焊锡或Ag膏等导电性膏。另外，进行第一电路元件12的电极和所希望的第一导电图案11B的引线接合。具体地说，将第一导电图案11A上安装的第一电路元件12的电极和所希望的第一导电图案11B利用热压装进行的球形接合及超声波进行的楔形接合一并进行引线接合。
在此，作为第一电路元件12，一个IC芯片被固定在第一导电图案11A上，但也可以采用IC芯片以外的元件作为第一电路元件12。具体地说，作为第一电路元件12除IC芯片等以外也可采用晶体管芯片、二极管等有源元件或片状电阻、片状电容器等无源元件。另外，可将这些有源元件及无源元件多个配置在第一导电图案11上。
第三工序：参照图9
本工序在于，由绝缘性树脂13模装，以至少覆盖第一电路元件12。具体地说，由绝缘性树脂13模装，覆盖第一电路元件12，并填充分离槽32。
在如图9所示，本工序中，绝缘性树脂13完全覆盖第一电路元件12及多个第一导电图案11，绝缘性树脂13填充在分离槽32，与分离槽32嵌合并紧固结合。利用绝缘性树脂13支撑第一导电图案11。在本工序中可通过传递膜、注入膜或罐封实现。作为树脂材料，环氧树脂等热硬性树脂可通过传递膜实现，聚酰亚胺树脂、硫化聚苯等热塑性树脂可通过注入膜实现。
本工序的特征在于，在覆盖绝缘性树脂13之前，作为第一导电图案11的导电箔30构成支撑衬底。现有例中，采用本来没有必要的支撑衬底形成导电图案，在本发明中，作为支撑衬底的导电箔30是作为电极材料的必须材料。因此，具有可最大限度节省构成材料的优点，也可实现成本的降低。另外，由于分离槽32比导电箔的厚度更浅，故导电箔30作为第一导电图案11未被一个个分离。从而，片状导电箔30作为整体处理，模装绝缘性树脂13时，向模型的搬运、安装作业非常容易。
第四工序：参照图10
本工序在于，在绝缘性树脂13上形成通孔20，使第一导电图案11露出。
在本工序中，钻削绝缘性树脂13的一部分形成通孔20，从而露出第一导电图案11B的表面。具体地说，利用由激光去除绝缘性树脂13的一部分而形成通孔20，使露出部21露出。在此，作为激光最好使用二氧化碳激光。另外，利用激光使绝缘性树脂13蒸发后，当露出部21上有残渣时，利用过锰酸钠或过硫酸铵等进行湿式腐蚀，除去该残渣。
利用激光形成的通孔20的平面形状为圆形。另外，通孔20的平面剖面的大小向离通孔20底部接近而缩小。
第五工序：参照图11～图14
本工序在于，在绝缘性树脂13表面形成第二导电图案14，在通孔20的侧面及底面形成连接装置15。
参照图11，在本工序中，利用电解电镀法或无电解镀敷法在绝缘性树脂13上面、通孔20侧面部及露出部21上形成由铜等金属构成的镀膜，构成第二导电图案14及连接装置15。采用电解电镀法构成电镀膜时，将导电箔30的背面作为电极使用。图11中，在通孔20侧面部及露出部21上也形成具有和电镀膜24相同厚度的电镀膜，但也可以由电镀材料埋入通孔20。在利用金属埋入通孔20时，使用加入添加剂的镀液，这样的电镀一般被称为填充电镀。
其次，参照图12，在绝缘性树脂13上面形成的电镀膜24上部形成抗蚀剂层35，以形成要求的第二导电图案14。
参照图13，以抗蚀剂层35为掩模，选择性地蚀刻导电膜24，形成第二导电图案14，在此，与矩阵状地形成多个的各电路装置分界线对应的位置的导电膜24也被除去。另外，蚀刻结束后，抗蚀剂层35被剥离。在该工序中，也可在利用蚀刻形成导电膜24的同时形成屏蔽层。此时，在绝缘性树脂13上面，在不形成第二导电图案14的剩余部分设置屏蔽层。另外，也可以利用连接装置将屏蔽层和第一导电图案11B电连接。
通过以无掩模的方式全部除去导电箔30背面，将各第一导电图案11电分离。具体地说，将导电箔30背面化学地及/或物理地除去，分离为第一导电图案11。该工序通过研磨、研削、蚀刻、激光的金属蒸发等实施。实验中，整面湿式腐蚀导电箔30，自分离槽32露出绝缘性树脂13。其结果，形成第一导电图案11A及第一导电图案11B而被分离。形成在绝缘性树脂13上露出第一导电图案11背面的结构。
其次，参照图14，在形成外部电极18的位置形成开口部，在绝缘性树脂13的背面涂敷抗焊剂19。该开口部33通过进行曝光及显影形成。
第六工序：参照图15及图16
本工序在于，在第二导电图案14上安装第二电路元件22。参照图15，介由焊锡等焊剂在绝缘性树脂13上面形成的第二导电图案14上固定第二电路元件22。作为第二电路元件22可采用片状电阻或片状电容器等无源元件。另外，也可以采用ISI等半导体元件。
其次，参照图16，在自抗焊剂19的开口部露出的第一导电图案11B背面形成外部电极18。具体地说，利用网印等在开口部33上涂敷、熔解焊锡等焊剂，形成外部电极18。
第七工序：参照图17
本工序在于，通过切割绝缘性树脂13分离为各电路装置。
在本工序中，通过切割与各电路装置10的分界线对应的位置的绝缘性树脂13，分离为一个个的电路装置。与切割线34对应的位置的导电箔30由自背面蚀刻导电箔的工序除去。另外，与切割线34对应的位置的第二导电图案14也利用蚀刻除去。从而，在本工序中，由于进行切割的刀片仅切除绝缘性树脂13，故可将刀片的损耗控制在最小限度。
由以上工序中制造电路装置10，可得到图1或图2显示的最终形状。
本发明的特征在于，将绝缘性树脂13上面设置的第二导电图案14和连接装置15一并形成。具体地说，第二导电图案14及连接装置15是一体化的镀膜，其利用电解电镀法或无电解镀敷法形成。从而，可最大限度抑制形成屏蔽层14引起的工序数的增加。
另外，本发明的特征在于，使用激光在绝缘性树脂13上形成通孔20。具体地说，由于通过调节激光的输出，可仅除去绝缘性树脂13，故在绝缘性树脂13和导电图案11的界面停止激光进行的除去。
另外，在所述说明中，是通过使用激光形成通孔20，但也可以利用激光以外的方法形成通孔20。具体地说，在模装绝缘性树脂13的工序中，在与绝缘性树脂13上面接触的模型上设置与通孔20的形状对应的凸部。使连接凸部的前端部与导电图案表面接触，同时利用绝缘性树脂13进行密封，可形成与该凸部形状相对应的形状的通孔20。
另外，在所述说明中，连接装置15是和第二导电图案14一起利用镀敷法形成的，但是，也可以利用Ag膏等导电性膏形成连接装置14。另外，也可使连接装置15及第二导电图案14均由导电膏形成。
本发明可得到以下所示的效果。
第一，通过在密封整体的绝缘性树脂13上面设置第二导电图案14，在第二导电图案14上安装第二电路元件22，可三维安装元件。另外，电路装置10由绝缘性树脂13上面支撑整体，由于具有不需要安装衬底的结构，故形成薄型、轻量的装置。
第二，在绝缘性树脂13上面，通过在不设置第二导电图案14的位置设置屏蔽层14A，可防止噪声自外部进入装置内部。
第三，由于第二导电图案和连接装置15由一体的镀膜形成，故可将第二导电图案及连接装置一并形成，可减少工序数。

Claims (14)

1、一种电路装置，其特征在于，包括：第一导电图案，其安装有第一电路元件；绝缘性树脂，其至少覆盖所述第一电路元件及所述第一导电图案；第二导电图案，其设置在所述绝缘性树脂上面；连接装置，其电连接所述第一导电图案和所述第二导电图案，且被设置在通孔的底面及侧面，所述通孔设置为使所述第一导电图案的表面部分地露出；第二电路元件，其安装在所述第二导电图案上。
2、如权利要求1所述的电路装置，其特征在于，所述第一导电图案具有单层的配线结构，且所述第一导电图案背面自所述绝缘性树脂露出。
3、如权利要求1所述的电路装置，其特征在于，所述第一导电图案及所述第二导电图案由铜等金属形成。
4、如权利要求1所述的电路装置，其特征在于，所述第二导电图案和所述连接装置作为一体由同一材料形成。
5、如权利要求1所述的电路装置，其特征在于，所述第二导电图案和所述连接装置利用镀膜形成。
6、如权利要求1所述的电路装置，其特征在于，所述第二电路元件是片状电阻或片状电容器。
7、如权利要求1所述的电路装置，其特征在于，在未设置所述第二导电图案的区域的所述绝缘性树脂上面设置屏蔽层。
8、如权利要求7所述的电路装置，其特征在于，由所述连接装置将所述屏蔽层和所述第一导电图案电连接。
9、一种电路模块，其特征在于，其包括第一电路装置和第二电路装置，其中，所述第一电路装置包括：第一导电图案，其安装有第一电路元件；绝缘性树脂，其至少覆盖所述第一电路元件；第二导电图案，其设置在所述绝缘性树脂上面；连接装置，其电连接所述第一导电图案和所述第二导电图案；外部电极，其设置在所述第一导电图案背面，所述第二电路装置和所述第一电路装置具有相同结构，介由所述第一电路装置具有的外部电极利用迭层结构在所述第二电路装置上部固定所述第一电路装置。
10、如权利要求9所述的电路模块，其特征在于，在所述第一电路装置具有的第二导电图案上固定第二电路元件。
11、一种电路装置的制造方法，其特征在于，包括：形成第一导电图案的工序；在所述第一导电图案上固定第一电路元件的工序；由绝缘性树脂模装，以至少覆盖所述第一电路元件的工序；在所述绝缘性树脂上形成通孔，以使所述第一导电图案露出的工序；在所述绝缘性树脂表面形成第二导电图案，并在所述通孔的侧面及底面形成连接装置的工序；在所述第二导电图案上安装第二电路元件的工序；通过切割所述绝缘性树脂分离为各电路种装置的工序。
12、如权利要求11所述的电路装置的制造方法，其特征在于，所述通孔使用激光形成。
13、如权利要求11所述的电路装置的制造方法，其特征在于，所述第二导电图案及所述连接层利用电镀法形成。
14、如权利要求15所述的电路装置的制造方法，其特征在于，利用在导电箔上形成分离槽形成单层的所述第一导电图案，进行所述绝缘性树脂的填充，在所述分离槽中也进行填充，通过除去所述导电箔的背面直至露出所述绝缘性树脂，将各第一导电图案电分离。
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