CN118053873A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN118053873A
CN118053873A CN202311494339.7A CN202311494339A CN118053873A CN 118053873 A CN118053873 A CN 118053873A CN 202311494339 A CN202311494339 A CN 202311494339A CN 118053873 A CN118053873 A CN 118053873A
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diode
layer
main surface
electrode
semiconductor device
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西康一
小西和也
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Mitsubishi Electric Corp
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Abstract

得到能够在具有***栅构造的RC‑IGBT中使RRSOA提高的半导体装置。IGBT区域(3)及二极管区域(4)设置于半导体基板(1)。IGBT区域具有：多个有源沟槽(11)，它们是从第一主面(1a)将基极层(8)及发射极层(9)贯通而设置的；栅极电极(12)，其隔着栅极绝缘膜(14)而设置于有源沟槽的内部；以及埋入电极(13)，其隔着栅极绝缘膜而设置于有源沟槽的内部，配置于栅极电极的第二主面(1b)侧。二极管区域具有：第二导电型的阳极层(17)，其设置于漂移层(2)的第一主面侧；多个二极管沟槽(19)，它们从第一主面设置于阳极层；以及二极管电极(20)，其隔着二极管绝缘膜(21)而设置于二极管沟槽的内部。阳极层的深度比二极管沟槽的深度深。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
提出了具有***栅构造的RC-IGBT(例如，参照专利文献1)。
专利文献1：日本特开2017-147431号公报
在现有技术中，在二极管区域形成有载流子积蓄层，并且二极管区域的沟槽底部与漂移层接触。因此，容易在沟槽底部发生电场集中，所以存在RRSOA(Reverse RecoverySafe Operation Area)变窄，在恢复动作时容易破坏这一问题。
发明内容
本发明就是为了解决上述这样的课题而提出的，其目的在于得到能够在具有***栅构造的RC-IGBT中使RRSOA提高的半导体装置。
本发明涉及的半导体装置的特征在于，具有：半导体基板，其在彼此相对的第一主面与第二主面之间具有第一导电型的漂移层；IGBT区域及二极管区域，它们设置于所述半导体基板；以及发射极电极，其设置于所述半导体基板的所述第一主面，所述IGBT区域具有：第一导电型的载流子积蓄层，其设置于所述漂移层的第一主面侧；第二导电型的基极层，其设置于所述载流子积蓄层的第一主面侧；第一导电型的发射极层及第二导电型的接触层，它们设置于所述基极层的第一主面侧；多个有源沟槽，它们是从所述第一主面将所述基极层及所述发射极层贯通而设置的；栅极电极，其隔着栅极绝缘膜而设置于所述有源沟槽的内部；埋入电极，其隔着所述栅极绝缘膜而设置于所述有源沟槽的内部，配置于所述栅极电极的第二主面侧；以及第二导电型的集电极层，其设置于所述漂移层的第二主面侧，所述二极管区域具有：第二导电型的阳极层，其设置于所述漂移层的第一主面侧；多个二极管沟槽，它们从所述第一主面设置于所述阳极层；二极管电极，其隔着二极管绝缘膜而设置于所述二极管沟槽的内部；以及第一导电型的阴极层，其设置于所述漂移层的第二主面侧，所述阳极层的深度比所述二极管沟槽的深度深。
发明的效果
在本发明中，在二极管区域，阳极层的深度比二极管沟槽的深度深。通过阳极层将二极管沟槽的底部覆盖而进行保护，从而能够缓和二极管沟槽的底部的电场。其结果，能够在具有***栅构造的RC-IGBT中使RRSOA提高。
附图说明
图1是表示实施方式1涉及的半导体装置的剖视图。
图2是沿图1的I-II的剖视图。
图3是表示实施方式2涉及的半导体装置的剖视图。
图4是表示实施方式3涉及的半导体装置的剖视图。
图5是表示实施方式4涉及的半导体装置的剖视图。
图6是表示实施方式5涉及的半导体装置的剖视图。
图7是表示实施方式6涉及的半导体装置的剖视图。
图8是表示实施方式7涉及的半导体装置的剖视图。
图9是表示实施方式8涉及的半导体装置的俯视图。
图10是沿图9的I-II的剖视图。
图11是表示实施方式9涉及的半导体装置的剖视图。
图12是表示实施方式10涉及的半导体装置的剖视图。
图13是表示实施方式11涉及的半导体装置的剖视图。
图14是表示实施方式12涉及的半导体装置的剖视图。
图15是表示实施方式13涉及的半导体装置的剖视图。
具体实施方式
参照附图，对实施方式涉及的半导体装置进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1
图1是表示实施方式1涉及的半导体装置的剖视图。图2是沿图1的I-II的剖视图。该半导体装置是具有***栅构造的RC-IGBT。半导体基板1在彼此相对的第一主面1a与第二主面1b之间具有第一导电型的漂移层2。此外，例如第一导电型是n型，第二导电型是p型。
在半导体基板1设置有IGBT区域3、二极管区域4及埋入电极上拉区域(未图示)。发射极电极5设置于半导体基板1的第一主面1a。集电极(collector)电极(electrode)6设置于半导体基板1的第二主面1b。此外，也可以在半导体基板1与发射极电极5之间设置有阻挡金属层。也可以在发射极电极5之上通过镀敷等设置有正面金属。
在IGBT区域3，第一导电型的载流子积蓄层7设置于漂移层2的第一主面1a侧。载流子积蓄层7的杂质浓度大于漂移层2。第二导电型的基极层8设置于载流子积蓄层7的第一主面1a侧。第一导电型的发射极层9及第二导电型的接触层10设置于基极层8的第一主面1a侧。
多个有源沟槽11是从半导体基板1的第一主面1a将发射极层9、基极层8及载流子积蓄层7贯通而设置的。栅极电极12和埋入电极13隔着栅极绝缘膜14而设置于有源沟槽11的内部。栅极电极12的底部位于比基极层8更靠第二主面侧处。埋入电极13配置于栅极电极12的第二主面1b侧，通过栅极绝缘膜14与栅极电极12绝缘，与发射极电极5电连接。
第一导电型的缓冲层15设置于漂移层2的第二主面1b侧。缓冲层15的杂质浓度大于漂移层2。第二导电型的集电极层16设置于缓冲层15的第二主面1b侧。
在二极管区域4，第二导电型的阳极层17设置于漂移层2的第一主面1a侧。第二导电型的二极管接触层18设置于阳极层17的第一主面侧。二极管接触层18的杂质浓度高于阳极层17。多个二极管沟槽19从半导体基板1的第一主面1a设置于阳极层17。二极管电极20隔着二极管绝缘膜21设置于二极管沟槽19的内部，与发射极电极5电连接。
在二极管区域4，第一导电型的缓冲层15也设置于漂移层2的第二主面1b侧。第一导电型的阴极层22设置于缓冲层15的第二主面1b侧。在从半导体基板1的第一主面1a朝向基板内侧的方向的深度上，阳极层17的深度比二极管沟槽19的深度深。
多个有源沟槽11及多个二极管沟槽19在俯视观察时彼此平行地配置。发射极层9及接触层10以在俯视观察时与有源沟槽11正交的方式条带状地延伸，相互交替地配置。阳极层17及二极管接触层18以在俯视观察时与二极管沟槽19正交的方式条带状地延伸，相互交替地配置。
层间绝缘膜23设置于有源沟槽11及二极管沟槽19之上。发射极电极5穿过层间绝缘膜23的开口23a而与发射极层9及接触层10电连接，穿过层间绝缘膜23的开口23b而与阳极层17及二极管接触层18电连接。集电极电极6与集电极层16及阴极层22电连接。
RC-IGBT在恢复动作时将在二极管区域4积蓄的电子从第二主面1b侧排出、将空穴从第一主面1a侧排出而使耗尽层延伸，由此在集电极-发射极之间对电源电压进行保持，使二极管断开。此时，如果电场在沟槽底部集中，则在恢复动作时容易破坏，即RRSOA变窄。另外，如果空穴在半导体基板1的第一主面1a侧积蓄，则电场在PN结界面集中，RRSOA变窄。特别地，就具有***栅构造的RC-IGBT而言，恢复时的di/dt大，因此，上述模式下的RRSOA下降变得显著。因此，需要对沟槽底部的电场进行缓和，或提高空穴排出效率。
与此相对，在本实施方式中，在二极管区域4，使阳极层17的深度比二极管沟槽19的深度深。通过由阳极层17将二极管沟槽19的底部覆盖而进行保护，从而能够缓和二极管沟槽19的底部的电场。其结果，在具有***栅构造的RC-IGBT中能够使RRSOA提高。
实施方式2
图3是表示实施方式2涉及的半导体装置的剖视图。位于埋入电极13的侧壁或底部的栅极绝缘膜14比位于栅极电极12的侧壁的栅极绝缘膜14厚。由此，能够对有源沟槽11的底部进行保护，因此能够提高栅极可靠性。其它结构及效果与实施方式1相同。
实施方式3
图4是表示实施方式3涉及的半导体装置的剖视图。阳极层17是通过在注入了第二导电型的离子之后实施高温、长时间的退火而形成的，通过退火温度、时间对阳极层17的深度进行调整。在本实施方式中，阳极层17的深度比有源沟槽11的深度浅。由此，能够缩短阳极层17的退火时间，因此，能够降低制造成本。另外，二极管沟槽19的深度D2比有源沟槽11的深度D1浅，因此与实施方式1同样地，阳极层17的深度比二极管沟槽19的深度深。其它结构及效果与实施方式1相同。
实施方式4
图5是表示实施方式4涉及的半导体装置的剖视图。通过负载效应，从而在相同的蚀刻条件下在开口宽度窄的区域中得到的蚀刻深度浅。因此，在本实施方式中，使二极管沟槽19的宽度W2比有源沟槽11的宽度W1窄。由此，在利用负载效应通过相同的蚀刻工序形成了有源沟槽11和二极管沟槽19的情况下，能够使二极管沟槽19的深度D2比有源沟槽11的深度D1浅。因此，能够降低制造成本。其它结构及效果与实施方式3相同。
实施方式5
图6是表示实施方式5涉及的半导体装置的剖视图。有源沟槽11的间距P1是相邻的2个有源沟槽11的间隔。二极管沟槽19的间距P2是相邻的2个二极管沟槽19的间隔或相邻的有源沟槽11与二极管沟槽19的间隔。为了降低导通损耗，优选IGBT区域3的有源沟槽11的间距P1设计得窄。因此，在本实施方式中，使二极管沟槽19的间距P2比有源沟槽11的间距P1宽。由此，无需变更IGBT区域3的设计就能够增加二极管区域4中的发射极电极5与阳极层17之间的接触面积，通过提高空穴排出效率而使RRSOA提高。其它结构及效果与实施方式1相同。
实施方式6
图7是表示实施方式6涉及的半导体装置的剖视图。在二极管沟槽19的底部，阳极层17最深，阳极层17的深度比二极管沟槽19的深度深。在被二极管沟槽19彼此夹着的区域的一部分，阳极层17的深度比二极管沟槽19的深度浅。即，被二极管沟槽19彼此夹着的区域的一部分处的阳极层17的深度比前述二极管沟槽19的底部处的阳极层17的深度浅。由此，在电子电流从集电极电极6流向发射极电极5的二极管的正向动作时，能够将电子从形成得浅的阳极层17排出。因此，能够通过减少在二极管区域4积蓄的载流子而降低恢复损耗。其它结构及效果与实施方式1相同。
实施方式7
图8是表示实施方式7涉及的半导体装置的剖视图。RRSOA有时由于电流在IGBT区域3与二极管区域4的边界集中而恶化。因此，在本实施方式中，使与IGBT区域3相邻的区域中的阳极层17的深度D3比不与IGBT区域3相邻的区域中的阳极层17的深度D4深。由此，能够在IGBT区域3与二极管区域4的边界附近处使阳极层17深，使沟槽底部的电场缓和而使RRSOA提高，并且距离边界远的部分通过使阳极层17浅而降低恢复损耗。其它结构及效果与实施方式1相同。
实施方式8
图9是表示实施方式8涉及的半导体装置的俯视图。图10是沿图9的I-II的剖视图。在俯视观察时在被有源沟槽11与二极管沟槽19夹着的区域形成的二极管接触层18的面积大于在被二极管沟槽19彼此夹着的区域形成的二极管接触层18的面积。由此，能够提高IGBT区域3与二极管区域4的边界处的空穴排出效率而使RRSOA提高，并且通过在被二极管沟槽19彼此夹着的区域形成的二极管接触层的面积而对恢复损耗进行调整。其它结构及效果与实施方式1相同。
实施方式9
图11是表示实施方式9涉及的半导体装置的剖视图。二极管埋入电极24隔着二极管绝缘膜21而设置于二极管沟槽19的内部，配置于二极管电极20的第二主面侧。二极管埋入电极24通过二极管绝缘膜21与二极管电极20绝缘。能够通过二极管电极20或二极管埋入电极24的电位对输入电容Ci与反馈电容Cr的电容比Cr/Ci进行调整。例如，与二极管电极20和二极管埋入电极24这两者都呈发射极电位的情况相比，如果将二极管电极20设为发射极电位，将二极管埋入电极24设为栅极电位，则能够增加栅极-发射极间电容Cge、增加Ci，能够使Cr/Ci变小。其它结构及效果与实施方式1相同。
实施方式10
图12是表示实施方式10涉及的半导体装置的剖视图。在俯视观察时在与有源沟槽11及二极管沟槽19正交的方向上，二极管区域4中的层间绝缘膜23的开口23b的宽度大于IGBT区域3中的层间绝缘膜23的开口23a的宽度。因此，二极管沟槽19彼此之间的发射极电极5与第一主面1a之间的接触宽度W4大于有源沟槽11彼此之间的发射极电极5与第一主面1a之间的接触宽度W3。这样，通过使二极管区域4的接触宽度W4比IGBT区域3的接触宽度W3大，从而能够提高二极管区域4的空穴排出效率、使RRSOA提高，却不会增加IGBT区域3中的有源沟槽11与发射极电极5的短路故障。其它结构及效果与实施方式1相同。
实施方式11
图13是表示实施方式11涉及的半导体装置的剖视图。二极管电极20的上部位于比半导体基板1的第一主面1a更靠第二主面1b侧处。在二极管沟槽19的内部，在二极管电极20与发射极电极5之间设置有凹陷(recess)电极25。凹陷电极25与二极管电极20、发射极电极5连接。凹陷电极25的材料也可以是与发射极电极5相同的材料。凹陷电极25的侧壁与半导体基板1接触。因此，还能够从凹陷电极25的侧壁将空穴排出，所以能够提高空穴排出效率而使RRSOA提高。其它结构及效果与实施方式1相同。
实施方式12
图14是表示实施方式12涉及的半导体装置的剖视图。在二极管区域4的漂移层2的第二主面1b侧，p型的集电极层16与n型的阴极层22交替地配置。由此，能够降低来自第二主面1b侧的电子注入效率，降低恢复损耗。其它结构及效果与实施方式1相同。
实施方式13
图15是表示实施方式13涉及的半导体装置的剖视图。在IGBT区域3的漂移层2的第二主面1b侧，p型的集电极层16与n型的阴极层22交替地配置。由此，能够降低来自第二主面1b侧的空穴注入效率，降低截止损耗。其它结构及效果与实施方式1相同。
此外，半导体基板1不限于由硅形成，也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。由这样的宽带隙半导体形成的半导体芯片的耐压性及容许电流密度高，因此能够小型化。通过使用该小型化的半导体芯片，从而组装有该半导体芯片的半导体装置也能够小型化、高集成化。另外，由于半导体芯片的耐热性高，因此能够使散热器的散热鳍片小型化，能够使水冷部空冷化，因而能够使半导体装置进一步小型化。另外，由于半导体芯片的电力损耗低且高效，因此能够使半导体装置高效化。
以上，对优选的实施方式等进行了详细说明，但并非限于上述实施方式等，在不脱离权利要求书所记载的范围的情况下，能够对上述实施方式等施加各种变形及置换。本发明能够不限定于耐压等级、FZ基板、MCZ基板、外延基板等地进行应用。能够进行不同实施方式的组合，也能够在某个区域局部地应用各实施方式的结构。另外，以IGBT区域3与二极管区域4相邻的情况为例进行了说明，但也可以在IGBT区域3与二极管区域4之间配置有边界区域(在第一主面侧具有二极管构造，在第二主面侧配置有集电极层的区域)。
以下，将本发明的各方案作为附记而汇总地进行记载。
(附记1)
一种半导体装置，其特征在于，具有：
半导体基板，其在彼此相对的第一主面与第二主面之间具有第一导电型的漂移层；
IGBT区域及二极管区域，它们设置于所述半导体基板；以及
发射极电极，其设置于所述半导体基板的所述第一主面，
所述IGBT区域具有：
第一导电型的载流子积蓄层，其设置于所述漂移层的第一主面侧；
第二导电型的基极层，其设置于所述载流子积蓄层的第一主面侧；
第一导电型的发射极层及第二导电型的接触层，它们设置于所述基极层的第一主面侧；
多个有源沟槽，它们是从所述第一主面将所述基极层及所述发射极层贯通而设置的；
栅极电极，其隔着栅极绝缘膜而设置于所述有源沟槽的内部；
埋入电极，其隔着所述栅极绝缘膜而设置于所述有源沟槽的内部，配置于所述栅极电极的第二主面侧；以及
第二导电型的集电极层，其设置于所述漂移层的第二主面侧，
所述二极管区域具有：
第二导电型的阳极层，其设置于所述漂移层的第一主面侧；
多个二极管沟槽，它们从所述第一主面设置于所述阳极层；
二极管电极，其隔着二极管绝缘膜而设置于所述二极管沟槽的内部；以及
第一导电型的阴极层，其设置于所述漂移层的第二主面侧，
所述阳极层的深度比所述二极管沟槽的深度深。
(附记2)
根据附记1所记载的半导体装置，其特征在于，
所述埋入电极与所述栅极电极绝缘，所述埋入电极与所述发射极电极电连接，
所述二极管电极与所述发射极电极电连接。
(附记3)
根据附记1或2所记载的半导体装置，其特征在于，
位于所述埋入电极的侧壁或底部的栅极绝缘膜比位于所述栅极电极的侧壁的所述栅极绝缘膜厚。
(附记4)
根据附记1至3中任一项所记载的半导体装置，其特征在于，
所述阳极层的深度比所述有源沟槽的深度浅。
(附记5)
根据附记4所记载的半导体装置，其特征在于，
所述二极管沟槽的宽度小于所述有源沟槽的宽度，
所述二极管沟槽的深度比所述有源沟槽的深度浅。
(附记6)
根据附记1至5中任一项所记载的半导体装置，其特征在于，
所述多个二极管沟槽的间距大于所述多个有源沟槽的间距。
(附记7)
根据附记1至6中任一项所记载的半导体装置，其特征在于，
被所述二极管沟槽彼此夹着的区域的一部分处的所述阳极层的深度比所述二极管沟槽的底部处的所述阳极层的深度浅。
(附记8)
根据附记1至7中任一项所记载的半导体装置，其特征在于，
与所述IGBT区域相邻的区域中的所述阳极层的深度比不与所述IGBT区域相邻的区域中的所述阳极层的深度深。
(附记9)
根据附记1至8中任一项所记载的半导体装置，其特征在于，
所述二极管区域具有设置于所述阳极层的第一主面侧且与所述阳极层相比杂质浓度高的第二导电型的二极管接触层，
在俯视观察时在被所述有源沟槽与所述二极管沟槽夹着的区域形成的所述二极管接触层的面积大于在被所述二极管沟槽彼此夹着的区域形成的所述二极管接触层的面积。
(附记10)
根据附记1至9中任一项所记载的半导体装置，其特征在于，
所述二极管区域还具有二极管埋入电极，该二极管埋入电极隔着所述二极管绝缘膜而设置于所述二极管沟槽的内部，该二极管埋入电极配置于所述二极管电极的第二主面侧，与所述二极管电极绝缘。
(附记11)
根据附记1至10中任一项所记载的半导体装置，其特征在于，
所述二极管沟槽彼此之间的所述发射极电极与所述第一主面之间的接触宽度大于所述有源沟槽彼此之间的所述发射极电极与所述第一主面之间的接触宽度。
(附记12)
根据附记1至11中任一项所记载的半导体装置，其特征在于，
所述二极管区域还具有凹陷电极，该凹陷电极在所述二极管沟槽的内部设置于所述二极管电极与所述发射极电极之间，该凹陷电极的侧壁与所述半导体基板接触。
(附记13)
根据附记1至12中任一项所记载的半导体装置，其特征在于，
在所述二极管区域的所述漂移层的第二主面侧，所述集电极层与所述阴极层交替地配置。
(附记14)
根据附记1至13中任一项所记载的半导体装置，其特征在于，
在所述IGBT区域的所述漂移层的第二主面侧，所述集电极层与所述阴极层交替地配置。
(附记15)
根据附记1至14中任一项所记载的半导体装置，其特征在于，
所述半导体基板由宽带隙半导体形成。
标号的说明
1半导体基板，1a第一主面，1b第二主面，2漂移层，3IGBT区域，4二极管区域，5发射极电极，7载流子积蓄层，8基极层，9发射极层，10接触层，11有源沟槽，12栅极电极，13埋入电极，14栅极绝缘膜，16集电极层，17阳极层，18二极管接触层，19二极管沟槽，20二极管电极，21二极管绝缘膜，22阴极层，24二极管埋入电极，25凹陷电极

Claims (15)

1.一种半导体装置，其特征在于，具有：
半导体基板，其在彼此相对的第一主面与第二主面之间具有第一导电型的漂移层；
IGBT区域及二极管区域，它们设置于所述半导体基板；以及
发射极电极，其设置于所述半导体基板的所述第一主面，
所述IGBT区域具有：
第一导电型的载流子积蓄层，其设置于所述漂移层的第一主面侧；
第二导电型的基极层，其设置于所述载流子积蓄层的第一主面侧；
第一导电型的发射极层及第二导电型的接触层，它们设置于所述基极层的第一主面侧；
多个有源沟槽，它们是从所述第一主面将所述基极层及所述发射极层贯通而设置的；
栅极电极，其隔着栅极绝缘膜而设置于所述有源沟槽的内部；
埋入电极，其隔着所述栅极绝缘膜而设置于所述有源沟槽的内部，配置于所述栅极电极的第二主面侧；以及
第二导电型的集电极层，其设置于所述漂移层的第二主面侧，
所述二极管区域具有：
第二导电型的阳极层，其设置于所述漂移层的第一主面侧；
多个二极管沟槽，它们从所述第一主面设置于所述阳极层；
二极管电极，其隔着二极管绝缘膜而设置于所述二极管沟槽的内部；以及
第一导电型的阴极层，其设置于所述漂移层的第二主面侧，
所述阳极层的深度比所述二极管沟槽的深度深。
2.根据权利要求1所述的半导体装置，其特征在于，
所述埋入电极与所述栅极电极绝缘，所述埋入电极与所述发射极电极电连接，
所述二极管电极与所述发射极电极电连接。
3.根据权利要求1或2所述的半导体装置，其特征在于，
位于所述埋入电极的侧壁或底部的栅极绝缘膜比位于所述栅极电极的侧壁的所述栅极绝缘膜厚。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述阳极层的深度比所述有源沟槽的深度浅。
5.根据权利要求4所述的半导体装置，其特征在于，
所述二极管沟槽的宽度小于所述有源沟槽的宽度，
所述二极管沟槽的深度比所述有源沟槽的深度浅。
6.根据权利要求1或2所述的半导体装置，其特征在于，
所述多个二极管沟槽的间距大于所述多个有源沟槽的间距。
7.根据权利要求1或2所述的半导体装置，其特征在于，
被所述二极管沟槽彼此夹着的区域的一部分处的所述阳极层的深度比所述二极管沟槽的底部处的所述阳极层的深度浅。
8.根据权利要求1或2所述的半导体装置，其特征在于，
与所述IGBT区域相邻的区域中的所述阳极层的深度比不与所述IGBT区域相邻的区域中的所述阳极层的深度深。
9.根据权利要求1或2所述的半导体装置，其特征在于，
所述二极管区域具有设置于所述阳极层的第一主面侧且与所述阳极层相比杂质浓度高的第二导电型的二极管接触层，
在俯视观察时在被所述有源沟槽与所述二极管沟槽夹着的区域形成的所述二极管接触层的面积大于在被所述二极管沟槽彼此夹着的区域形成的所述二极管接触层的面积。
10.根据权利要求1或2所述的半导体装置，其特征在于，
所述二极管区域还具有二极管埋入电极，该二极管埋入电极隔着所述二极管绝缘膜而设置于所述二极管沟槽的内部，该二极管埋入电极配置于所述二极管电极的第二主面侧，与所述二极管电极绝缘。
11.根据权利要求1或2所述的半导体装置，其特征在于，
所述二极管沟槽彼此之间的所述发射极电极与所述第一主面之间的接触宽度大于所述有源沟槽彼此之间的所述发射极电极与所述第一主面之间的接触宽度。
12.根据权利要求1或2所述的半导体装置，其特征在于，
所述二极管区域还具有凹陷电极，该凹陷电极在所述二极管沟槽的内部设置于所述二极管电极与所述发射极电极之间，该凹陷电极的侧壁与所述半导体基板接触。
13.根据权利要求1或2所述的半导体装置，其特征在于，
在所述二极管区域的所述漂移层的第二主面侧，所述集电极层与所述阴极层交替地配置。
14.根据权利要求1或2所述的半导体装置，其特征在于，
在所述IGBT区域的所述漂移层的第二主面侧，所述集电极层与所述阴极层交替地配置。
15.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体基板由宽带隙半导体形成。
CN202311494339.7A 2022-11-15 2023-11-10 半导体装置 Pending CN118053873A (zh)

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