CN116578164B - Multichannel coherent signal generating device and multichannel coherent signal source - Google Patents

Multichannel coherent signal generating device and multichannel coherent signal source Download PDF

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CN116578164B
CN116578164B CN202310857052.XA CN202310857052A CN116578164B CN 116578164 B CN116578164 B CN 116578164B CN 202310857052 A CN202310857052 A CN 202310857052A CN 116578164 B CN116578164 B CN 116578164B
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clock
signal
signals
phase
speed
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CN116578164A (en
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何志海
杨胜领
程军强
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Zhongxing Lianhua Technology Beijing Co ltd
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Zhongxing Lianhua Technology Beijing Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The invention belongs to the technical field of coherent signal source circuits, and provides a multichannel coherent signal generating device and a multichannel coherent signal source, wherein the multichannel coherent signal generating device comprises: a clock board card; the high-speed clock buffer unit is used for buffering the high-speed clock signals provided by the clock board card into multiple paths of clock signals; the trigger signal distribution unit is used for distributing signals to the trigger signals; at least two clock distribution units for receiving the multiple trigger signals and the first clock signals and outputting multiple second clock signals; the FPGA chip is used for receiving the third clock signal and the signal control command to obtain multiple paths of data streams; and the at least two digital-analog conversion chips are used for receiving the multipath data streams, the corresponding clock signals and the alignment signals thereof and generating multichannel coherent signals. The device can independently control the phase of the phase-coherent signals of all channels, has high phase modulation precision, low phase noise and high spurious suppression, and the phase-coherent signals are not easily affected by temperature and have high stability.

Description

Multichannel coherent signal generating device and multichannel coherent signal source
Technical Field
The invention relates to the technical field of coherent signal source circuits, in particular to a multichannel coherent signal generating device and a multichannel coherent signal source.
Background
The multi-channel coherent signal is widely applied to the scenes such as testing verification of phased array radar, direction-finding positioning radar or Multiple Input Multiple Output (MIMO) communication, and the phase and the amplitude of each path of signal are strictly controlled.
In the prior art, when a multichannel coherent signal is obtained, the phase shifter is generally used for adjusting the phase of the multichannel clock signal, and the phase shifter is easy to be interfered by temperature change during calibration, so that the phase control of the clock signal is inaccurate.
Disclosure of Invention
The invention provides a multichannel coherent signal generating device and a multichannel coherent signal source, which are used for solving the defects that the result of signal coherent adjustment by using a phase shifter is inaccurate in the prior art, and the phase noise difference and the phase jitter of a coherent signal obtained by using a DDS technology are large, improving the stability of the generated coherent signal, and the multichannel coherent signal generating device has simple control, strong expandability and can realize the expansion of the number of channels through simple cascading.
The invention provides a multichannel coherent signal generating device, which comprises:
the clock board card is used for providing a plurality of high-speed clock signals and outputting a plurality of trigger signals and a plurality of first enabling signals under the condition that a synchronous instruction sent by the controller is received, and edges among the high-speed clock signals, the trigger signals and the first enabling signals are strictly aligned;
a high-speed clock buffer unit for buffering the high-speed clock signal into a plurality of paths of clock signals, wherein the edges of the plurality of paths of clock signals are aligned;
the trigger signal distribution unit is used for distributing the trigger signals, the edges of the multiple paths of trigger signals are aligned, the transmission leads of the multiple paths of trigger signals are equal in length, and each path of trigger signals are aligned with the phase of the corresponding clock signal;
the at least two clock distribution units are used for receiving the multipath trigger signals and the first clock signals and outputting multipath second clock signals, the multipath second clock signals comprise medium-speed clock signals and low-speed clock signals, the edges of the multipath second clock signals are aligned, each path of second clock signals are aligned with the phases of the first clock signals, the ratio of the frequency of the high-speed clock signals to the frequency of each path of second clock signals is an integer, the first clock signals are at least one of the multipath clock signals, and the leads of the multipath trigger signals are equal in length;
The FPGA chip is used for receiving the third clock signal sent by the clock distribution unit and a signal control command sent by the controller, obtaining a plurality of paths of data streams, and respectively and synchronously sending the plurality of paths of data streams according to the plurality of paths of first enabling signals when the plurality of multi-channel coherent signal generating devices synchronously work; the third clock signal belongs to the multipath second clock signals, the third clock signal comprises a working clock of an FPGA chip, a working clock signal of a high-speed serial interface of the FPGA chip and an alignment signal of the working clock signal of the high-speed serial interface, leads between the clock distribution unit and clock pins of the FPGA chip are equal in length, and the FPGA chip comprises one or more than one;
the digital-analog conversion chips are used for generating multichannel coherent signals according to the multipath data streams sent by the FPGA chip through the high-speed serial ports, the alignment signals of the working clocks of the digital-analog conversion chips sent by the clock distribution unit and the clock signals of the digital-analog conversion chips sent by the high-speed clock buffer unit, the lead wires between the high-speed clock buffer unit and the clock pins of the at least two digital-analog conversion chips are equal in length, and the lead wires between the clock distribution unit and the working clock alignment pins of the at least two digital-analog conversion chips are equal in length; the high-speed data transmission leads between the FPGA chip and the digital-analog conversion chip are strictly equal in length.
According to the multichannel coherent signal generating device provided by the invention, the FPGA chip is internally provided with a plurality of data sources, the FPGA controls the plurality of data sources to generate target digital signals according to the received signal control command, and under the condition that the third clock signal is received, data streams are continuously generated to obtain the multichannel data streams, and the multichannel data streams are synchronously aligned.
According to the multi-channel coherent signal generating device provided by the invention, the FPGA chip is also used for receiving the multi-channel second enabling signals sent by the controller, and synchronously sending the multi-channel data streams according to the multi-channel second enabling signals or the multi-channel first enabling signals under the condition that a plurality of channels in a single multi-channel coherent signal generating device synchronously work, and each channel of second enabling signals are strictly aligned.
According to the invention, a multichannel coherent signal generating device is provided, and the device further comprises:
each integer phase-locked loop is used for receiving one channel phase-locked signal and outputting a phase-locked loop output signal corresponding to the one channel phase-locked signal, each phase-locked loop output signal is a multi-octave signal, and the ratio between the phase of the phase-locked loop output signal and the phase of the one channel phase-locked signal is the ratio between the frequency of the phase-locked loop output signal and the frequency of the one channel phase-locked signal.
According to the invention, a multichannel coherent signal generating device is provided, and the device further comprises:
and each frequency expansion unit is used for receiving one phase-locked loop output signal and outputting a frequency expansion signal corresponding to the phase-locked loop output signal, and the ratio of the phase of the frequency expansion signal to the phase of the phase-locked loop output signal is a target frequency expansion multiple.
According to the invention, a multichannel coherent signal generating device is provided, and the device further comprises:
and at least two amplitude control units, each amplitude control unit being used for adjusting the amplitude of the frequency spread signal.
According to the multichannel coherent signal generating device provided by the invention, the controller is also used for fine adjustment of the time delay of the multipath second clock signals.
The invention also provides a multichannel coherent signal source, comprising:
the clock board card is used for providing a plurality of high-speed clock signals and outputting a plurality of trigger signals and a plurality of first enabling signals under the condition that a synchronous instruction sent by the controller is received, and edges among the high-speed clock signals, the trigger signals and the first enabling signals are strictly aligned;
a high-speed clock buffer unit, configured to buffer the high-speed clock signal into multiple paths of clock signals, where edges of the multiple paths of clock signals are aligned;
The trigger signal distribution unit is used for distributing the trigger signals, the edges of the multiple paths of trigger signals are aligned, the transmission leads of the multiple paths of trigger signals are equal in length, and each path of trigger signals are aligned with the phase of the corresponding clock signal;
the at least two clock distribution units are used for receiving the multipath trigger signals and the first clock signals and outputting multipath second clock signals, the multipath second clock signals comprise medium-speed clock signals and low-speed clock signals, the edges of the multipath second clock signals are aligned, each path of second clock signals are aligned with the phases of the first clock signals, the ratio of the frequency of the high-speed clock signals to the frequency of each path of second clock signals is an integer, the first clock signals are at least one of the multipath clock signals, and the leads of the multipath trigger signals are equal in length;
the FPGA chip is used for receiving the third clock signal sent by the clock distribution unit and a signal control command sent by the controller, obtaining a plurality of paths of data streams, and respectively and synchronously sending the plurality of paths of data streams according to the plurality of paths of first enabling signals when the plurality of multi-channel coherent signal generating devices synchronously work; the third clock signal belongs to the multipath second clock signals, the third clock signal comprises a working clock of an FPGA chip, a working clock signal of a high-speed serial interface of the FPGA chip and an alignment signal of the working clock signal of the high-speed serial interface, leads between the clock distribution unit and clock pins of the FPGA chip are equal in length, and the FPGA chip comprises one or more than one;
The digital-analog conversion chips are used for generating multichannel coherent signals according to the multipath data streams sent by the FPGA chip through the high-speed serial ports, the alignment signals of the working clocks of the digital-analog conversion chips sent by the clock distribution unit and the clock signals of the digital-analog conversion chips sent by the high-speed clock buffer unit, the lead wires between the high-speed clock buffer unit and the clock pins of the at least two digital-analog conversion chips are equal in length, and the lead wires between the clock distribution unit and the working clock alignment pins of the at least two digital-analog conversion chips are equal in length; the high-speed data transmission leads between the FPGA chip and the digital-analog conversion chip are strictly equal in length;
each integer phase-locked loop is used for receiving one channel phase-locked signal and outputting a phase-locked loop output signal corresponding to the one channel phase-locked signal, each phase-locked loop output signal is a multi-octave signal, and the ratio between the phase of the phase-locked loop output signal and the phase of the one channel phase-locked signal is the ratio between the frequency of the phase-locked loop output signal and the frequency of the one channel phase-locked signal;
Each frequency expansion unit is used for receiving one phase-locked loop output signal and outputting a frequency expansion signal corresponding to the phase-locked loop output signal, and the ratio of the phase of the frequency expansion signal to the phase of the phase-locked loop output signal is a target frequency expansion multiple;
and at least two amplitude control units, each amplitude control unit being used for adjusting the amplitude of the frequency spread signal.
The multi-channel coherent signal generating device and the multi-channel coherent signal source provided by the invention have the advantages that a clock board is arranged to provide a plurality of high-speed clock signals, a plurality of trigger signals and a plurality of first enabling signals, a high-speed clock buffer unit is arranged to output the high-speed clock signals as a plurality of clock signals, the plurality of trigger signals are sent to each clock distribution unit through the trigger signal distribution unit, the second clock signals with different frequencies are obtained through at least two clock distribution units according to the received synchronous trigger signals and the first clock signals, the edges of each second clock signal are aligned and are aligned with the phases of the first clock signals, one or more FPGA chips are arranged to generate a plurality of data streams sent through the high-speed serial ports, the clock signals of the digital-analog conversion chip and the aligned signals thereof, the phase of each channel coherent signal can be independently controlled, the phase modulation precision is high, the phase noise is low, the spurious suppression is high, the coherent signal is not easily affected by temperature, and the stability is high.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a multichannel coherent signal generating device provided by the invention;
fig. 2 is a schematic structural diagram of cascade connection of multiple multi-channel coherent signal generating devices according to the present invention;
fig. 3 is a schematic structural diagram of a multichannel coherent signal source provided by the present invention.
Reference numerals:
110: a high-speed clock buffer unit; 120: a clock distribution unit;
130: an FPGA chip; 140: a digital-to-analog conversion chip; 150: a controller;
160: a clock board card; 170: an integer phase-locked loop; 180: a frequency expansion unit;
190: an amplitude control unit; 200: and a trigger signal distribution unit.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The multi-channel coherent signal generating apparatus and the multi-channel coherent signal source of the present invention are described below with reference to fig. 1 to 3.
Fig. 1 is a schematic structural diagram of a multi-channel coherent signal generating apparatus according to the present invention, as shown in fig. 1, the multi-channel coherent signal generating apparatus includes: the clock circuit board 160, the high-speed clock buffer unit 110, at least two clock distribution units 120, the FPGA chip 130, at least two digital-to-analog conversion chips 140, and the trigger signal distribution unit 200.
The high-speed clock buffer unit 110 is configured to output the input high-speed clock signal as multiple clock signals, and edges of each clock signal are aligned.
The clock board 160 is configured to provide a high-speed clock signal, and output a plurality of trigger signals and a plurality of first enable signals when receiving a synchronization command sent by the controller.
In this embodiment, the clock board 160 is capable of automatically generating a plurality of high-speed clock signals in a case of normal operation, and generating a plurality of trigger signals and a plurality of first enable signals in a case of receiving a synchronization instruction transmitted from the controller 150, wherein the high-speed clock signals, the trigger signals and the first enable signals are strictly aligned.
In the embodiment shown in fig. 1, after receiving the synchronization instruction, the clock board 160 sends a high-speed clock signal to the clock buffer circuit (corresponding to the high-speed clock buffer unit 110), and after receiving the synchronization instruction, sends a trigger signal SYNC to the trigger signal distribution unit 200, and sends N paths of first enable signals to the N FPGA chips 130, respectively. In this embodiment, the high-speed clock buffer unit 110 may be a demultiplexer, a clock buffer chip, or other electronic devices for implementing power distribution.
In this embodiment, one high-speed clock signal input from the outside is buffered into multiple high-speed clock signals by the high-speed clock buffer unit 110, and each output high-speed clock signal is edge-aligned.
The trigger signal distribution unit 200 is configured to perform signal distribution on the trigger signals sent by the clock board 160, and align edges of the trigger signals sent to each clock distribution unit 120, where leads of multiple trigger signals are equal in length, and each trigger signal is aligned with a phase of a corresponding clock signal.
The at least two clock distribution units 120 are configured to receive multiple trigger signals and first clock signals and output multiple second clock signals, where the multiple second clock signals include a medium-speed clock signal and a low-speed clock signal, edges of the multiple second clock signals are aligned, each of the multiple second clock signals is phase aligned with the first clock signal, a ratio of a frequency of the high-speed clock signal to a frequency of each of the multiple second clock signals is an integer, and the first clock signal is at least one of the multiple clock signals.
In this embodiment, the first clock signal is a buffered high-speed clock signal, and the first signal is input to the multiple clock distribution units 120 to generate second clock signals with different frequencies, for example, an alignment signal dac_sysref of the digital-to-analog conversion chip 140, a clock signal fpga_clk of the FPGA chip 130, a clock signal gtx_ref of the high-speed serial interface, and an alignment signal gtx_sysref of the high-speed serial interface.
In this embodiment, each output second clock signal and each high-speed clock signal are in an integer multiple relationship, that is, the ratio of the frequency of the high-speed clock signal to the frequency of each second clock signal is an integer, and the circuit layout of each clock distribution unit 120 is strictly consistent with the lead of the output clock signal, the edges of each second clock signal are strictly aligned, and each second signal is aligned with the phase of the high-speed clock signal.
In this embodiment, the clock distribution unit 120 also needs to align the output various second clock signals by synchronizing the trigger signals.
The FPGA chip 130 is configured to receive the second clock signal sent by the clock distribution unit 120 and the signal control command sent by the controller 150, obtain multiple data streams, and when the multiple-channel coherent signal generating devices operate synchronously, respectively perform synchronous transmission on the multiple data streams according to multiple first enable signals, where the third clock signal is at least one of the multiple second clock signals, the third clock signal includes an operating clock of the FPGA chip 130, an operating clock signal of a high-speed serial interface of the FPGA chip 130, and an alignment signal of an operating clock signal of the high-speed serial interface, and leads between the clock distribution unit 120 and clock pins of the FPGA chip 130 are equal in length, and the FPGA chip 130 includes one or more of the following.
In this embodiment, when multiple signal devices are required to operate synchronously, the clock board 160 is required to provide multiple first enable signals to the FPGA chip 130 to ensure synchronous transmission of multiple data streams.
In addition, in some embodiments, when multiple channels within a single signal device operate synchronously, either multiple first enable signals provided by the Zhong Banka and multiple second enable signals provided by the controller 150 may be used.
In the embodiment shown in fig. 1, FPGAs 1_clk and FPGAs 2_clk belong to working clock signals of FPGAs, N clock distribution units 120 are respectively connected to clock pins of N FPGAs through leads, and the leads from the clock distribution units 120 to the clock pins of each path of FPGA chip 130 are strictly equal in length; the gtx1_ref and the gtx2_ref are working clocks of the high-speed serial interface of the FPGA1, and need to be connected to a GTX reference clock input pin of the FPGA chip 130, and lead wires reaching the GTX reference clock pins corresponding to each path of FPGA from the clock distribution unit 120 are strictly equal in length; the gtx1_sysref and the gtx2_sysref are alignment signals of working clocks of the high-speed serial interface of the FPGA1, and need to be connected to the corresponding gtx_sysref pin of the FPGA chip 130, and the leads from the clock distribution unit 120 to the gtx_sysref pin of each path of FPGA chip 130 are strictly equal in length.
In this embodiment, the FPGA operating clock is produced by clock distribution unit 120 and each path of signal transmission leads are strictly equal in length; and the FPGA executes a corresponding algorithm according to the received command and the working clock to generate a corresponding data stream, so that synchronous alignment of the data streams generated by the multiple FPGA is ensured.
The at least two digital-to-analog conversion chips 140, the digital-to-analog conversion chips 140 are configured to generate a multi-channel coherent signal according to a multi-channel data stream sent by the FPGA chip 130 through the high-speed serial port, an alignment signal of an operation clock of the digital-to-analog conversion chips 140 sent by the clock distribution unit 120, and a clock signal of the digital-to-analog conversion chips 140 sent by the high-speed clock buffer unit 110, wherein a lead between the high-speed clock buffer unit 110 and clock pins of the at least two digital-to-analog conversion chips 140 is equal in length, and a lead between the clock distribution unit 120 and the operation clock alignment pins of the at least two digital-to-analog conversion chips 140 is equal in length; the high-speed data transmission leads between the FPGA chip 130 and the digital-to-analog conversion chip are strictly equal in length.
In this embodiment, due to the high data stream rate and large bandwidth of the synchronization, the data transmission needs to be synchronized by adopting a high-speed serial port to send to the high-speed digital-analog conversion chip 140 (Digital to Analog Converter, DAC); the working clock gtx_ref and the alignment signal gtx_sysref of the high-speed serial port are generated by the clock distribution unit 120, and each path of wires are strictly equal in length, so that the synchronization of the multi-path data transmission is ensured.
In the embodiment shown in fig. 1, the high-speed DAC receives the data stream, generating corresponding analog signals (coherent signal 1,., coherent signal N-1, and coherent signal N); the multi-path DAC adopts the high-speed clock signal DAC_CLK buffered by the same clock, and the clock leads from the high-speed clock buffer unit 110 to each path DAC are strictly equal in length; meanwhile, the DAC_SYSREF signals are adopted by the multipath DAC to perform signal alignment, leads of each path of DAC_SYSEREF signals are strictly equal in length, and finally generated signal phases are guaranteed to be strictly aligned.
Fig. 2 is a schematic structural diagram of a cascade connection of a plurality of multi-channel coherent signal generating devices according to the present invention, in the embodiment shown in fig. 2, when n multi-channel coherent signal generating devices are cascaded, a clock board 160 may respectively provide a path of high-speed clock signals (corresponding to high-speed clock signals 1-n) to a high-speed clock buffer unit 110 in the n multi-channel coherent signal generating devices; after the clock board 160 receives the control instruction sent by the controller, one path of trigger signal SYNC (corresponding to SYNC 1-N) is provided to each trigger signal distribution unit 200 in synchronization, and one path of first enable signal (corresponding to first enable signal 1-N) is provided to each FPGA chip 130, where each path of first enable signal may include N enable signals, and the value of N is the same as the number of coherent signal channels of the single multi-channel coherent signal generating device.
According to the multi-channel coherent signal generating device provided by the invention, a multi-channel clock board is arranged to provide a high-speed clock signal, a multi-channel trigger signal and a multi-channel first enable signal, a high-speed clock buffer unit 110 is arranged to output the input high-speed clock signal as the multi-channel clock signal, the multi-channel trigger signal is sent to each clock distribution unit 120 through a trigger signal distribution unit 200, and at least two clock distribution units 120 obtain second clock signals with different frequencies according to the received synchronous trigger signal and the first clock signal, each channel of second clock signal is aligned with the edge of the first clock signal and is aligned with the phase of the first clock signal, one or more FPGA chips 130 are arranged to send multi-channel data streams through a high-speed serial port, the clock signals of a digital-analog conversion chip 140 and aligned signals thereof, so that the phase of each channel coherent signal can be independently controlled, the phase modulation accuracy is high, the phase noise is low, the spurious suppression is high, the coherent signal is not easily affected by temperature, and the stability is high.
In some embodiments, a plurality of data sources are disposed in the FPGA chip 130, and the FPGA controls the plurality of data sources to generate the target digital signal according to the received signal control command, and continuously generates the data stream under the condition that the third clock signal is received, so as to obtain multiple data streams, where the multiple data streams are aligned synchronously.
In this embodiment, the target digital signal is a digital signal required by the user, and the phase and frequency of the target digital signal may be set according to the user's needs.
In this embodiment, the data source may be a DDS signal generator, and one DDS signal generator executes a corresponding data stream generating algorithm according to the fpga_clk signal, the gtx_ref signal, and the gtx_sysref signal received by the FPGA chip 130, so as to obtain multiple synchronous aligned data streams.
In this embodiment, since the synchronous data stream has high data stream rate and large bandwidth, the data stream can be sent to the DAC by using a high-speed serial port, the working clock gtx_ref and the alignment signal gtx_sysref of the high-speed serial port are generated by the clock distribution unit 120, and each path of wires are strictly equal in length, so as to ensure that the multi-path data transmission remains synchronous.
It should be noted that, the number of data sources that can be supported in the FPGA is limited by the number of high-speed serial ports and the scale of hardware resources contained in the FPGA, and a single FPGA chip with high specification can support at least two paths of data sources and provide data streams for at least two DACs; the maximum number of channels supported by a single signal device (multi-channel coherent signal generating device) is limited by the number of FPGAs.
In the embodiment shown in fig. 3, the FPGA1 chip includes a data source 1 and a data source 2, the data source 1 outputs a high-speed data stream (DAC 1 JESD) to be transmitted to the DAC1, and the DAC1 performs digital-to-analog conversion on the input DAC1 JESD signal according to the received DAC1 sytref signal and DAC1 CLK signal, and outputs a corresponding analog signal.
According to the multichannel coherent signal generating device provided by the invention, the plurality of data sources are arranged in the FPGA chip 130 to obtain the target digital signal, so that independent control of signal phases is realized, and synchronous high-speed data streams are continuously generated under the condition of receiving the third clock signal, and the data streams output by the FPGA chip 130 are ensured to maintain a coherent relationship.
In some embodiments, the FPGA chip 130 is further configured to receive multiple second enable signals sent by the controller, and in a case where multiple channels in the single multi-channel coherent signal generating apparatus operate synchronously, send multiple data streams synchronously according to the multiple second enable signals or the multiple first enable signals, where each of the multiple second enable signals is strictly aligned.
In this embodiment, when multiple channels in a single signal device operate synchronously, multiple first enable signals may be provided to the FPGA chip 130 by the clock board 160, or multiple second enable signals may be provided to the FPGA chip 130 by the controller 150, so as to ensure that multiple data streams start to be sent synchronously; in this way, the source of the enable signal required by FPGA chip 130 may be flexibly selected by the user.
According to the multichannel coherent signal generating device provided by the invention, the controller 150 is used for sending the second enabling signal to the FPGA chip 130 to trigger the synchronous sending function of the multipath data streams, so that convenience is provided for the phase alignment of the subsequent control signals.
In some embodiments, the apparatus further comprises: at least two integer phase-locked loops 170, each integer phase-locked loop 170 is configured to receive a channel-coherent signal and output a phase-locked loop output signal corresponding to the channel-coherent signal, the phase-locked loop output signal is a multi-octave signal, and a ratio between a phase of the phase-locked loop output signal and a phase of the channel-coherent signal is a ratio between a frequency of the phase-locked loop output signal and a frequency of the channel-coherent signal.
In this embodiment, the output signal of the DAC may be used as a reference signal of the integer phase-locked loop 170, and the signals output by the integer phase-locked loops 170 respectively keep the signal phase-correlation relationship, so that the phases of the output signals are aligned.
In the embodiment shown in fig. 3, N coherent signals are respectively input to the corresponding integer pll 170, and the controller 150 controls the integer pll 170 to output a multi-octave pll output signal through an input instruction.
According to the multichannel coherent signal generating device provided by the invention, the output signals of the DACs are processed by arranging at least two integer phase-locked loops 170, so that phase noise and spurious emissions at the far end of the output signals of the phase-locked loops can be reduced.
In some embodiments, the apparatus further comprises: and at least two frequency expansion units 180, where each frequency expansion unit 180 is configured to receive a phase-locked loop output signal and output a frequency expansion signal corresponding to the phase-locked loop output signal, and a ratio of a phase of the frequency expansion signal to a phase of the phase-locked loop output signal is a target frequency expansion multiple.
In this embodiment, the frequency expansion unit 180 maintains a strict proportional relationship with the phase of the phase-locked loop output signal of the integer phase-locked loop 170, and thus the expanded frequency signal continues to maintain the phase-dependence.
In this embodiment, the target frequency expansion multiple may be any integer.
In the embodiment shown in fig. 3, the output signal of the integer pll 170 is transmitted to the frequency expansion unit 180, and in the case that the frequency expansion unit 180 receives the control command sent by the controller 150, the frequency of the output signal of the pll is multiplied to obtain the required signal frequency, and the frequency is aligned with the signals output by the other split frequency expansion units 180 to maintain the signal correlation relationship.
According to the multichannel coherent signal generating device provided by the invention, the frequency of the phase-locked loop output signal is independently controlled by setting at least two frequency expansion units 180, so that the multi-octave signal is expanded to a higher octave, and the coverage range of the signal frequency is expanded.
In some embodiments, the apparatus further comprises: at least two amplitude control units 190, each amplitude control unit 190 for adjusting the amplitude of the frequency spread signal.
In this embodiment, after the signal passes through the frequency expansion unit, a filtering unit may be further configured to filter harmonic and subharmonic spurious in the output signal of the frequency expansion unit. In the embodiment shown in fig. 3, the signal output by the frequency expansion unit 180 is sent to the amplitude control unit 190, and when receiving the control instruction sent by the controller 150, the amplitude control unit 190 adjusts the signal amplitude of the frequency expansion signal, and the adjusted signal is aligned with the signals output by the other split amplitude control units 190, so as to maintain the signal-coherent relationship.
The multichannel coherent signal generating device provided by the invention realizes independent and high-precision control of the amplitude of the frequency expansion signal by arranging at least two amplitude control units 190.
In some embodiments, the controller 150 is further configured to fine tune the delays of the multiple second clock signals.
In this embodiment, the controller 150 may also perform fine delay adjustment on each output signal of the clock distribution unit 120, so as to ensure that strict setup time requirements between each clock are satisfied, and no random process is generated.
According to the multichannel coherent signal generating device provided by the invention, the time delay of the multipath second clock signals is finely adjusted through the controller 150, so that the alignment of each clock is ensured to be met, and the generation of a randomness process is reduced.
In some embodiments, the present invention also provides a multi-channel coherent signal source comprising: the clock board 160 is configured to provide multiple high-speed clock signals, and output multiple trigger signals and multiple first enable signals when receiving a synchronization instruction sent by the controller, where edges among the high-speed clock signals, the trigger signals and the first enable signals are strictly aligned; a high-speed clock buffer unit 110 for buffering the high-speed clock signal into a plurality of clock signals, the edges of the plurality of clock signals being aligned; the trigger signal distribution unit 200 is configured to perform signal distribution on the trigger signals, align edges of multiple trigger signals, make transmission leads of the multiple trigger signals equal in length, and align phases of each trigger signal and a corresponding clock signal; the at least two clock distribution units 120, the at least two clock distribution units 120 are configured to receive multiple paths of trigger signals and first clock signals, and output multiple paths of second clock signals, where the multiple paths of second clock signals include a medium speed clock signal and a low speed clock signal, edges of the multiple paths of second clock signals are aligned, each path of second clock signal is aligned with a phase of the first clock signal, a ratio of a frequency of the high speed clock signal to a frequency of each path of second clock signal is an integer, the first clock signal is at least one of the multiple paths of clock signals, and leads of the multiple paths of trigger signals are equal in length; the FPGA chip 130, the FPGA chip 130 is configured to receive the third clock signal sent by the clock distribution unit 120 and the signal control command sent by the controller 150, obtain multiple paths of data streams, and when the multiple-channel coherent signal generating devices operate synchronously, respectively send the multiple paths of data streams synchronously according to multiple paths of first enable signals, where the FPGA chip includes one or more than one of the multiple paths of data streams; the third clock signal belongs to multiple paths of second clock signals, and comprises an operating clock of the FPGA chip 130, an operating clock signal of a high-speed serial interface of the FPGA chip 130 and an alignment signal of the operating clock signal of the high-speed serial interface, and leads between the clock distribution unit 120 and clock pins of the FPGA chip 130 are equal in length; the at least two digital-to-analog conversion chips 140, the digital-to-analog conversion chips 140 are configured to generate multi-channel phase reference signals according to the multi-channel data stream sent by the FPGA chip 130 through the high-speed serial port, the alignment signal of the working clock of the digital-to-analog conversion chips sent by the clock distribution unit 120, and the clock signal of the digital-to-analog conversion chips sent by the high-speed clock buffer unit 110, and the leads between the high-speed clock buffer unit 100 and the clock pins of the at least two digital-to-analog conversion chips 140 are equal in length, and the leads between the clock distribution unit 120 and the working clock alignment pins of the at least two digital-to-analog conversion chips 140 are equal in length; the high-speed data transmission leads between the FPGA chip 130 and the digital-analog conversion chip are strictly equal in length; at least two integer phase-locked loops 170, each integer phase-locked loop 170 is configured to receive a channel-coherent signal and output a phase-locked loop output signal corresponding to the channel-coherent signal, each phase-locked loop output signal is a multi-octave signal, and a ratio between a phase of the phase-locked loop output signal and a phase of the channel-coherent signal is a ratio between a frequency of the phase-locked loop output signal and a frequency of the channel-coherent signal; at least two frequency expansion units 180, each frequency expansion unit 180 is configured to receive a phase-locked loop output signal and output a frequency expansion signal corresponding to the phase-locked loop output signal, where a ratio of a phase of the frequency expansion signal to a phase of the phase-locked loop output signal is a target frequency expansion multiple; at least two amplitude control units 190, each amplitude control unit 190 for adjusting the amplitude of the frequency spread signal.
The clock board 160 can automatically generate a plurality of high-speed clock signals under the normal operation condition, and generate a plurality of trigger signals and a plurality of first enable signals under the condition of receiving the synchronization command transmitted from the controller 150. The trigger signal distribution unit 200 is configured to perform signal distribution on the trigger signals, and the edges of the multiple trigger signals are aligned, the leads of the multiple trigger signals are equal in length, and each trigger signal is aligned with the phase of the corresponding clock signal.
In this embodiment, the high-speed clock buffer unit 110 may be a demultiplexer, a clock buffer chip, or other electronic devices for implementing power distribution.
In this embodiment, the first clock signal is a buffered high-speed clock signal, and the first signal is input to the multiple clock distribution units 120 to generate second clock signals with different frequencies, for example, an alignment signal dac_sysref of the digital-to-analog conversion chip 140, a clock signal fpga_clk of the FPGA chip 130, a clock signal gtx_ref of the high-speed serial interface, and an alignment signal gtx_sysref of the high-speed serial interface.
In this embodiment, the clock distribution unit 120 also needs to align the output various second clock signals by synchronizing the trigger signals.
In the embodiment shown in fig. 1, FPGAs 1_clk and FPGAs 2_clk belong to working clock signals of FPGA1, N clock distribution units 120 are respectively connected to clock pins of N FPGAs through leads, and leads from the clock distribution units 120 to the clock pins of each path of FPGA chip 130 are strictly equal in length; the gtx1_ref and the gtx2_ref are working clocks of the high-speed serial interfaces of the FPGAs, and are required to be connected to a GTX reference clock input pin of the FPGAs, and leads reaching the GTX reference clock pin of each path of FPGA chip 130 from the clock distribution unit 120 are strictly equal in length; the gtx1_sysref and the gtx2_sysref are alignment signals of working clocks of the high-speed serial interface of the FPGA, and need to be connected to the corresponding gtx_sysref pin of the FPGA, and the leads from the clock distribution unit 120 to the gtx_sysref pin of each path of FPGA chip 130 are strictly equal in length.
In this embodiment, the high speed DAC receives the data stream, generating a corresponding analog signal; the multi-path DAC adopts the high-speed clock signal DAC_CLK buffered by the same clock, and the clock leads from the high-speed clock buffer unit 110 to each path DAC are strictly equal in length; meanwhile, the DAC_SYSREF signals are adopted by the multipath DAC to perform signal alignment, leads of each path of DAC_SYSEREF signals are strictly equal in length, and finally generated signal phases are guaranteed to be strictly aligned.
In this embodiment, the frequency expansion unit 180 maintains a strict proportional relationship with the phase of the output signal of the integer phase locked loop 170, and the expanded frequency signal continues to maintain the phase correlation.
In this embodiment, the amplitude control unit 190 adjusts the signal amplitude of the frequency spread signal, and the adjusted signal is aligned with the signals output by the other split amplitude control units 190 to maintain the signal-coherent relationship.
In the embodiment shown in fig. 3, N coherent signals output by the multi-channel coherent signal generating device are respectively input to a corresponding integer phase-locked loop 170, and the controller 150 controls the integer phase-locked loop 170 to output a multi-octave phase-locked loop output signal through an input instruction; the pll output signal outputted from the integer pll 170 is transmitted to the frequency expansion unit 180, and in the case that the frequency expansion unit 180 receives the control command sent by the controller 150, the frequency of the pll output signal is multiplied to obtain a required signal frequency, and the frequency is aligned with the signals outputted from the other split frequency expansion units 180 to maintain the signal phase relationship; the signal output by the frequency expansion unit 180 is sent to the amplitude control unit 190, and when a control instruction sent by the controller 150 is received, the amplitude control unit 190 adjusts the signal amplitude of the frequency expansion signal to obtain an amplitude control signal, and the amplitude control signal is aligned with the signals output by other shunt amplitude control units 190 so as to maintain the signal phase-coherent relationship.
In addition, the circuits or units in the embodiments shown in fig. 2 and 3 may be split, cascaded or combined arbitrarily to meet different requirements of signal phase control, frequency control and amplitude control.
The multichannel coherent signal source provided by the invention can ensure that the phases of a high-speed clock and a trigger signal are strictly aligned by arranging the clock board card to provide a multichannel high-speed clock signal, a multichannel trigger signal and a multichannel first enabling signal, arranging the high-speed clock buffer unit to output the input high-speed clock signal into a multichannel clock signal, transmitting the multichannel trigger signal to each clock distribution unit through the trigger signal distribution unit, obtaining second clock signals with different frequencies through at least two clock distribution units according to the received synchronous trigger signal and the first clock signal, aligning the edges of each second clock signal with the phases of the first clock signal, arranging one or more FPGA chips to generate multichannel coherent signals through multichannel data streams transmitted by the high-speed serial ports, clock signals of the digital-analog conversion chip and aligned signals thereof, processing output signals of a plurality of DACs through arranging at least two integer phase-locked loops, independently controlling the frequencies of the output signals of the phase-locked loops through arranging at least two frequency expansion units, expanding the signals of the frequency ranges to higher octaves, and realizing the high-precision control of the frequency expansion signals through arranging at least two frequency expansion units.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (8)

1. A multi-channel coherent signal generating apparatus, comprising:
the clock board card is used for providing a plurality of high-speed clock signals and outputting a plurality of trigger signals and a plurality of first enabling signals under the condition that a synchronous instruction sent by the controller is received, and edges among the high-speed clock signals, the trigger signals and the first enabling signals are strictly aligned;
a high-speed clock buffer unit for buffering the high-speed clock signal into a plurality of paths of clock signals, wherein the edges of the plurality of paths of clock signals are aligned;
the trigger signal distribution unit is used for distributing the trigger signals, the edges of the multiple paths of trigger signals are aligned, the transmission leads of the multiple paths of trigger signals are equal in length, and each path of trigger signals are aligned with the phase of the corresponding clock signal;
The at least two clock distribution units are used for receiving the multipath trigger signals and the first clock signals and outputting multipath second clock signals, the multipath second clock signals comprise medium-speed clock signals and low-speed clock signals, the edges of the multipath second clock signals are aligned, each path of second clock signals are aligned with the phases of the first clock signals, the ratio of the frequency of the high-speed clock signals to the frequency of each path of second clock signals is an integer, the first clock signals are at least one of the multipath clock signals, and the leads of the multipath trigger signals are equal in length;
the FPGA chip is used for receiving the third clock signal sent by the clock distribution unit and a signal control command sent by the controller, obtaining a plurality of paths of data streams, and respectively and synchronously sending the plurality of paths of data streams according to the plurality of paths of first enabling signals when the plurality of multi-channel coherent signal generating devices synchronously work; the third clock signal belongs to the multipath second clock signals, the third clock signal comprises an operating clock of an FPGA chip, an operating clock signal of a high-speed serial interface of the FPGA chip and an alignment signal of the operating clock signal of the high-speed serial interface, leads between the clock distribution unit and clock pins of the FPGA chip are equal in length, and the FPGA chip comprises one or more than one;
The digital-analog conversion chips are used for generating multichannel coherent signals according to the multipath data streams sent by the FPGA chip through the high-speed serial ports, the alignment signals of the working clocks of the digital-analog conversion chips sent by the clock distribution unit and the clock signals of the digital-analog conversion chips sent by the high-speed clock buffer unit, the lead wires between the high-speed clock buffer unit and the clock pins of the at least two digital-analog conversion chips are equal in length, and the lead wires between the clock distribution unit and the working clock alignment pins of the at least two digital-analog conversion chips are equal in length; the high-speed data transmission leads between the FPGA chip and the digital-analog conversion chip are strictly equal in length.
2. The multi-channel coherent signal generating apparatus according to claim 1, wherein a plurality of data sources are provided in the FPGA chip, the FPGA controls the plurality of data sources to generate a target digital signal according to a received signal control command, and continuously generates a data stream under the condition that the third clock signal is received, so as to obtain the multi-channel data stream, and the multi-channel data stream is synchronously aligned.
3. The multi-channel coherent signal generating apparatus according to claim 2, wherein the FPGA chip is further configured to receive multiple second enable signals sent by the controller, and in case that multiple channels in a single multi-channel coherent signal generating apparatus operate synchronously, send multiple data streams synchronously according to the multiple second enable signals or multiple first enable signals, where each second enable signal is strictly aligned.
4. The multi-channel coherent signal generating apparatus according to claim 1, characterized in that said apparatus further comprises:
each integer phase-locked loop is used for receiving one channel phase-locked signal and outputting a phase-locked loop output signal corresponding to the one channel phase-locked signal, each phase-locked loop output signal is a multi-octave signal, and the ratio between the phase of the phase-locked loop output signal and the phase of the one channel phase-locked signal is the ratio between the frequency of the phase-locked loop output signal and the frequency of the one channel phase-locked signal.
5. The multi-channel coherent signal generating apparatus according to claim 4, further comprising:
And each frequency expansion unit is used for receiving one phase-locked loop output signal and outputting a frequency expansion signal corresponding to the phase-locked loop output signal, and the ratio of the phase of the frequency expansion signal to the phase of the phase-locked loop output signal is a target frequency expansion multiple.
6. The multi-channel coherent signal generating apparatus according to claim 5, further comprising:
and at least two amplitude control units, each amplitude control unit being used for adjusting the amplitude of the frequency spread signal.
7. The multi-channel coherent signal generating apparatus according to claim 1, wherein said controller is further configured to fine tune a delay of said plurality of second clock signals.
8. A multi-channel coherent signal source comprising:
the clock board card is used for providing a plurality of high-speed clock signals and outputting a plurality of trigger signals and a plurality of first enabling signals under the condition that a synchronous instruction sent by the controller is received, and edges among the high-speed clock signals, the trigger signals and the first enabling signals are strictly aligned;
a high-speed clock buffer unit for buffering the high-speed clock signal into a plurality of paths of clock signals, wherein the edges of the plurality of paths of clock signals are aligned;
The trigger signal distribution unit is used for distributing the trigger signals, the edges of the multiple paths of trigger signals are aligned, the transmission leads of the multiple paths of trigger signals are equal in length, and each path of trigger signals are aligned with the phase of the corresponding clock signal;
the at least two clock distribution units are used for receiving the multipath trigger signals and the first clock signals and outputting multipath second clock signals, the multipath second clock signals comprise medium-speed clock signals and low-speed clock signals, the edges of the multipath second clock signals are aligned, each path of second clock signals are aligned with the phases of the first clock signals, the ratio of the frequency of the high-speed clock signals to the frequency of each path of second clock signals is an integer, the first clock signals are at least one of the multipath clock signals, and the leads of the multipath trigger signals are equal in length;
the FPGA chip is used for receiving the third clock signal sent by the clock distribution unit and a signal control command sent by the controller, obtaining a plurality of paths of data streams, and respectively and synchronously sending the plurality of paths of data streams according to the plurality of paths of first enabling signals when the plurality of multi-channel coherent signal generating devices synchronously work; the third clock signal belongs to the multipath second clock signals, the third clock signal comprises an operating clock of an FPGA chip, an operating clock signal of a high-speed serial interface of the FPGA chip and an alignment signal of the operating clock signal of the high-speed serial interface, leads between the clock distribution unit and clock pins of the FPGA chip are equal in length, and the FPGA chip comprises one or more than one;
The digital-analog conversion chips are used for generating multichannel coherent signals according to the multipath data streams sent by the FPGA chip through the high-speed serial ports, the alignment signals of the working clocks of the digital-analog conversion chips sent by the clock distribution unit and the clock signals of the digital-analog conversion chips sent by the high-speed clock buffer unit, the lead wires between the high-speed clock buffer unit and the clock pins of the at least two digital-analog conversion chips are equal in length, and the lead wires between the clock distribution unit and the working clock alignment pins of the at least two digital-analog conversion chips are equal in length; the high-speed data transmission leads between the FPGA chip and the digital-analog conversion chip are strictly equal in length;
each integer phase-locked loop is used for receiving one channel phase-locked signal and outputting a phase-locked loop output signal corresponding to the one channel phase-locked signal, each phase-locked loop output signal is a multi-octave signal, and the ratio between the phase of the phase-locked loop output signal and the phase of the one channel phase-locked signal is the ratio between the frequency of the phase-locked loop output signal and the frequency of the one channel phase-locked signal;
Each frequency expansion unit is used for receiving one phase-locked loop output signal and outputting a frequency expansion signal corresponding to the phase-locked loop output signal, and the ratio of the phase of the frequency expansion signal to the phase of the phase-locked loop output signal is a target frequency expansion multiple;
and at least two amplitude control units, each amplitude control unit being used for adjusting the amplitude of the frequency spread signal.
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