CN117420880A - Multi-chip system and clock synchronization method thereof - Google Patents

Abstract

The invention discloses a multi-chip system and a clock synchronization method thereof. The clock synchronization method of the multi-chip system comprises the following steps: the control chip generates the same PLL clock and reset signals with the same quantity according to the quantity of the verification chips, and transmits the same PLL clock and reset signals to the verification chips through the PCB wiring; the control chip controls each verification chip to generate UCLK based on the PLL clock; the control chip dynamically adjusts the output phase of each PLL clock according to the offset time, the filtering time, the PCB delay, the port delay and the path delay of each verification chip, and realizes UCLK cophase; after UCLK of all verification chips is finished in phase, the control chip controls each verification chip to generate a user clock. The invention does not need to consider the equal-length design of the PCB wiring, can realize dynamic frequency modulation and phase modulation, and has stronger flexibility.

Description

Multi-chip system and clock synchronization method thereof

Technical Field

The present invention relates to the technical field of multi-chip systems, and in particular, to a multi-chip system and a clock synchronization method thereof.

Background

In chip design, as the chip integration level is higher and higher, the logic scale of chip verification for verification is larger and larger, and a single chip cannot meet the verification requirement, so that the chip verification is realized by using a system built by a plurality of chips, and a plurality of FPGA systems are used more. Any two devices must not be identical, the performance parameters of the two devices themselves have a certain difference, the difference can have a certain influence on the stability of the system, the two devices do not have obvious differences when the number of main chips is small, and the instability of the system is particularly prominent along with the increase of the number.

In general-purpose systems, clock synchronization for multi-core systems basically requires absolute physical equal length to ensure synchronization of system clocks. The circuit board Layout (PCB Layout) of all the main chip clocks in the system requires equal length wires, and the clock input of the main chip requires the use of the same Pin Pin to reduce the error of each main chip clock parameter so as to ensure the stability of the system. However, the maximum output of the clock Buffer (CLK Buffer) is only 16, and in a system with several tens of hundreds of chips, at least a plurality of clock buffers (CLK buffers) are needed, but differences between devices, differences between PCB traces between different devices, and differences in clock paths (CLK Route) caused by logic differences in chips can all cause the problem of inconsistent clock phases of each main chip, thereby affecting the stability of the system, and only continuously reducing the system frequency to keep the clock phase difference of each main chip within a clock period with a lower frequency so as to ensure the stability of data sampled at upper and lower edges.

The long wires of the circuit board Layout (PCB Layout) can lead the wires which can be connected originally with thousands of mils to be specially wound to tens of thousands of mils in order to meet the requirement of equal-length precision, and the longer the wires are, the larger the attenuation is, the more easily the crosstalk is affected, so that the problems of clock burrs, jitter and the like are caused.

Therefore, a new clock synchronization method is needed to solve the problem of clock non-synchronization caused by various devices, wires and logic differences of a multi-chip system with a large number.

Disclosure of Invention

In order to solve the technical problem that a multi-chip system with a large number in the prior art lacks a better clock synchronization scheme, the invention provides a multi-chip system and a clock synchronization method thereof.

The clock synchronization method of the multi-chip system provided by the invention comprises the following steps:

the control chip generates the same PLL clock and reset signals with the same quantity according to the quantity of verification chips locked by a user, and transmits the same PLL clock and reset signals to the verification chips through the PCB wiring;

the control chip controls the clock generation module of each verification chip to generate UCLK based on the PLL clock;

the control chip dynamically adjusts the output phase of each PLL clock according to the offset time, the PCB delay, the port delay and the path delay of each verification chip so as to enable the corresponding UCLK to be in phase;

after UCLK of all verification chips is completed in phase, the control chip controls each verification chip to generate a user clock.

Further, the offset time and the filter time of each verification chip are generated by each verification chip comparing the difference of its corresponding PLL clock and its generated UCLK.

Further, the offset time and the filtering time of each verification chip are generated by the following steps:

after the layout and wiring are completed between the verification chips based on the segmented netlist designs, traversing each segmented netlist design, and determining the maximum value of data path delay under UCLK clock domains, the maximum value of all gate clock offsets and the delay value of an interconnection module between the verification chips in all designs;

based on inequality Skew time not less than Max (Td) +s and Filter time not less than Max (Tc) +s, obtaining the maximum value of Skew time of each verification chip as offset time of each verification chip, and the maximum value of Filter time of each verification chip as filtering time of each verification chip.

Further, the PCB trace for transmitting the PLL clock to each verification chip employs a shortest path for the trace.

Further, after UCLK realizes in-phase, the verification chip outputs UCLK_Ready high level signal, and after the UCLK_Ready signal of the verification chip is in-phase, the verification chip outputs high level Ready signal to inform the control chip that in-phase is completed.

The multi-chip system provided by the invention comprises a control chip and a plurality of verification chips, wherein the control chip and the verification chips carry out clock synchronization by adopting the clock synchronization method of the multi-chip system.

Further, the control chip includes:

the clock control module is used for managing the clock generation module and the control interface;

the clock generation module generates a PLL clock, and comprises a frequency division circuit and a register controlled by the frequency division circuit, and the enabling of the output corresponding to the register is realized by configuring the register;

the control interface is connected with the control interface of each verification chip and is used for transmitting control signals and feedback data between the control chip and the verification chip.

Further, the verification chip includes:

a verification circuit corresponding to the segmented netlist design distributed on the verification chip;

at least one interconnection module for connecting with a corresponding one of the other verification chips according to the layout wiring between the verification chips;

a clock generation module that generates UCLK based on the PLL clock;

and the control interface is connected with the control interface of the control chip.

Further, the multi-chip system is a multi-FPGA system, the control chip is a CTRL FPGA, and the verification chip is a DUT FPGA.

Compared with the prior art, the invention has the following advantages:

the simplicity is strong, and the whole system can realize the clock coordination of a single board or even a plurality of boards of multi-FPGA systems only by one path of global clock;

the universality is strong, the internal clock is configurable, and the method can be used for any system with multiple FPGAs;

the flexibility is strong, and the FPGA locking and the resource allocation can be performed according to the actually required logic resources. The normal use of other FPGAs in the single board is not affected, and even the clock frequency of DUTs in any FPGA in the single board can be inconsistent;

the stability is high, and the frequency of the system operation can be higher than that of other existing methods.

Drawings

The invention is described in detail below with reference to examples and figures, wherein:

FIG. 1 is a flow chart of an embodiment of the present invention.

FIG. 2 is a system diagram of an embodiment of the present invention.

Fig. 3 is a detailed flow chart of an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.

As shown in fig. 1, the clock synchronization method of the multi-chip system of the present invention includes the following steps.

Step 1, after the verification design is divided based on the effective utilization rate of the verification chips, the number of the verification chips to be used is determined. The control chip directly locks the verification chips required by engineering, generates the same number of PLL clocks and reset signals based on the number of locked verification chips, and transmits the same number of PLL clocks and reset signals to the verification chips through the PCB wiring.

For generating the same number of PLL clocks, the frequency division circuit is designed through the FPGA; for generating an equal number of reset signals, this is achieved by designing the counter. The generation of both signals controls the number of actual outputs by configuring registers. For example: 4 FPGAs are used in the verification system, and 4 paths of clocks and resets are required to be output. The write address of the design clock output control register is: 0x10,0x30,0x50,0x70 …, the write address of the reset output register is: 0x20,0x40,0x60,0x80 …. The control chip writes 1 (high level) at the corresponding address (0 x10-0x 80), drives 4-way clock and resets output.

The reset signal of this step is used to enable the clock generation module of the verification chip.

And 2, the control chip controls the clock generation module of each verification chip to generate UCLK based on the PLL clock. For UCLK generation, a counting mode is adopted, and when the time corresponding to the count number of the PLL clock reaches 1/2UCLK clock period, the UCLK clock signal outputs a high level; when the time corresponding to the count number of the PLLs reaches the complete UCLK clock period, the UCLK clock signal outputs a low level, and the UCLK clock signal is repeatedly cycled and output continuously.

For example, the control chip pulls the reset signal high, enabling the clock generation module of the verification chip, so that the clock generation module of the verification chip generates UCLK.

And 3, the control chip dynamically adjusts the output phase of each PLL clock according to the offset time, the filtering time, the PCB delay, the port delay and the path delay of each verification chip, so that the corresponding UCLK is in phase. Based on the above values (delay at offset, port delay and path delay of the chip), the control chip calculates the delay difference, and controls the register of each clock output to realize the enabling of the clock generation module, thus realizing dynamic adjustment.

And step 4, after UCLK of all verification chips is finished in phase, the control chip controls each verification chip to generate a user clock.

In a preferred embodiment, the present invention uses shortest paths for the PCB routing for transmitting PLL clocks to the verification chips, i.e., the present invention does not require that the verification chips use a PCB routing design of full equal length, and each verification chip can select a shortest path for the PCB routing according to the PCB layout.

In one embodiment, the verification chip outputs a high level signal of UCLK_Ready after its UCLK has achieved the same phase, which indicates that its clock has achieved the same phase, and then outputs a high level Ready signal after performing the phase with the Ready signal of the verification chip, which informs the control chip that the same phase is completed. When the chip Ready signal of the verification chip is high, the verification chip is Ready, so that if the Ready signal is high, the verification chip is Ready and the clock is Ready, and chip verification can be started. If the phase and the subsequent Ready signal are low, one of the two signals is not Ready, and the chip verification chip cannot perform chip verification.

In a specific embodiment, in the step 3, the offset time and the filtering time of each verification chip may be generated by comparing the differences between the PLL clock corresponding to each verification chip and the UCLK generated by each verification chip.

In a specific embodiment, in the step 3, the offset time and the filtering time of each verification chip may also be generated by the following steps.

After the layout and wiring are completed between verification chips based on the segmented netlist designs, traversing each segmented netlist design, and determining the maximum value of data path delay under UCLK clock domains, the maximum value of all gate clock offsets and the delay value of the interconnection module between verification chips in all designs.

And then, based on the inequality Skew time not less than Max (Td) +s and the inequality Skew time not less than Max (Tc) +s, obtaining the maximum value of Skew time of each verification chip as offset time of each verification chip, and the maximum value of the Filter time of each verification chip as filtering time of each verification chip.

As shown in fig. 2, the present invention further protects a multi-chip system, where the multi-chip system includes a control chip and a plurality of verification chips, and the control chip and the plurality of verification chips perform clock synchronization by using the clock synchronization method of the multi-chip system according to the above technical solution.

In one embodiment, the control chip includes at least: the device comprises a clock control module, a clock generation module and a control interface.

And the clock control module is used for managing the clock generation module and the control interface.

And the clock generation module generates a PLL clock, comprises a frequency division circuit and a register controlled by the frequency division circuit, and realizes the enabling of the output corresponding to the register by configuring the register.

The control interface is connected with the control interface of each verification chip and is used for transmitting control signals and feedback data between the control chip and the verification chip.

In one embodiment, the verification chip includes at least: the device comprises a verification circuit, at least one interconnection module, a clock generation module and a control interface.

And the verification circuit corresponds to the segmented netlist design distributed on the verification chip.

At least one interconnection module for connecting with a corresponding one of the other verification chips according to the layout wiring between the verification chips. Taking FPGA as an example, for example, there is interconnection of split signals between FPGA1 and FGPA2, and the FPGA1 and the FPGA2 have corresponding interconnection modules respectively. The split signals are interconnected between the FPGA1 and the FPGA3, and the FPGA1 and the FPGA3 are respectively provided with corresponding interconnection modules, namely more than one interconnection module on the FPGA 1.

A clock generation module that generates UCLK based on the PLL clock;

and the control interface is connected with the control interface of the control chip.

In one embodiment, the multi-chip system is a multi-FPGA system, the control chip is a CTRL FPGA, and the verification chip is a DUT FPGA.

The clock synchronization of the present invention will be described in detail below with reference to a multi-FPGA system, as shown in fig. 3.

The CTRL FPGA of the multi-FPGA system is mainly used for generating and controlling clocks, and a clock generating module and a clock control module are internally designed for producing PLL clocks (namely PLL_CLK).

The DUT FPGA of the multi-FPGA system comprises a DUT for user verification and a user clock generation module.

The clock generation module in the CTRL FPGA is designed for a multi-output logic matrix, a frequency division circuit is designed in the CTRL FPGA, a PLL clock is generated to generate multiple paths of clock outputs, and each path of clock output can be enabled through a configuration register.

For example: 4 FPGAs are used in the verification system, and 4 paths of clocks and resets are required to be output. The write address of the design clock output control register is: 0x10,0x30,0x50,0x70 …, the write address of the reset output register is: 0x20,0x40,0x60,0x80 …. The control chip writes 1 (high level) at the corresponding address (0 x10-0x 80), drives 4-way clock and resets output.

Each clock output interface has an enable signal, a Skew ff (clock offset signal) and a Filter ff (Filter signal) for implementing Delay (Delay) and phase offset of clock output, and for filtering clock glitches to improve clock signal quality.

The CTRL FPGA generates the same number of PLL clocks and reset signals according to the number of the DUT FPGAs locked by the user, and the PLL clocks and the reset signals are transmitted to the DUT FPGAs through the PCB wiring. As described above, the PCB trace of the PLL clock (pll_clk) does not need to be designed in equal length, and the shortest path is taken as much as possible to ensure signal quality.

The CTRL FPGA controls a clock generation module inside each DUT FPGA to generate UCLK based on the PLL clock (pll_clk), which is a homologous clock, and thus, UCLK generated inside each DUT FPGA is a homologous clock.

The trace length of the PLL clock (pll_clk) on the PCB board can obtain its delay parameter, PCB delay, through the following calculation formula.

Microstrip line calculation formula:

the stripline calculation formula:

the Delay of each Pin of the FPGA is provided by a chip design manufacturer, namely the FPGA_Pin_delay (port Delay of the chip) which comprises a CTRL FPGA and a DUT FPGA.

At PR (Place and Route), the resources used within each DUT FPGA must be different, as will the path Delay of the global clock within (route_delay). After PR is completed, performing time sequence analysis on each divided design to obtain each design route_delay.

After PR (Place and Route) is completed, each netlist of the segmented design is traversed, the maximum data path delay under UCLK clock domains in all designs is determined, the maximum offset value (skew value) of all gating clocks is determined, and the self-module delays. Here, max (Td) represents the data path delay value under the maximum UCLK clock domain, and Max (Tc) represents the skew value of the maximum gate clock; s denotes the delay of the interconnect module.

By:

Filter time≥Max(Tc)+s；

Skew time≥Max(Td)+s；

thus, the maximum value of the filter time and the skew time of each verification chip is calculated as the filtering time and the offset time of each verification chip.

When the verification chip has a plurality of interconnection modules, a person skilled in the art can select a maximum delay value from the plurality of delay values according to the needs of an actual scene, and substitute the maximum delay value into the inequality, or calculate one or more final values of s by adopting the plurality of delay values based on balance considered in each aspect, and take the values into the inequality.

The CTRL FPGA calculates the Skew time, the Filter time, the PCB_delay, the FPGA_Pin_delay and the route_delay of each DUT FPGA, dynamically adjusts the output phase of each clock of the Ctrl FPGA clock generation module and the output of the DUT FPGA clock generation module, and realizes UCLK homology and same direction.

After UCLK realizes the same direction, a UCLK_Ready high signal is output. Which, in conjunction with the dut_ready signal (chip Read signal) of the DUT, outputs a Ready signal. The clock control module of the CTRL FPGA detects that the Ready signal phase of all DUT FPGAs is SYS_Ready, and when SYS_Ready is high, the system is Ready, and the operation can be started.

After the CTRL FPGA is ready, a Start signal is sent to all FPGAs at the same time, a clock generation module in the DUT FPGA is controlled to produce CCLK (user clock) based on UCLK frequency division, and the CCLK generated based on UCLK frequency division is in phase because UCLK is in the same phase, and the DUT is started. When the CCLK is paused, operation of the DUT can also be stopped simultaneously.

In general, for each verification chip, the default pll_clk, UCLK is one way, and CCLK may be designed according to the number actually required by the user.

The clock synchronization method of the invention can be applied to not only a single board, but also a plurality of boards, wherein the single board refers to the control chip and the verification chip which are designed on the same PCB, and the plurality of boards refer to the control chip and the verification chip which are designed on different PCBs.

The invention does not need to limit the difference of devices, the difference of PCB wiring and the difference of logic Route in the chip, can lead each chip to be designed according to the optimal design, and greatly improves the operation frequency of the system. The invention can dynamically modulate frequency and phase according to the scale of the verification system, and has stronger flexibility. The method can be applied to the scenes using the FPGA, such as an FPGA Prototype verification system (Prototype), an FPGA-based hardware simulation accelerator system (simulator) and the like.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (9)

1. A method for clock synchronization in a multichip system, comprising:

the control chip generates the same PLL clock and reset signals with the same quantity according to the quantity of verification chips locked by a user, and transmits the same PLL clock and reset signals to the verification chips through the PCB wiring;

the control chip controls each verification chip to generate UCLK based on the PLL clock;

the control chip dynamically adjusts the output phase of each PLL clock according to the offset time, the filtering time, the PCB delay, the port delay and the path delay of each verification chip so as to enable UCLK to be in phase;

after UCLK of all verification chips is completed in phase, the control chip controls each verification chip to generate a user clock.

2. The method of clock synchronization of a multichip system of claim 1, wherein the offset time and the filter time of each verification chip are generated by each verification chip comparing a difference between its corresponding PLL clock and its generated UCLK.

3. The method of clock synchronization of a multichip system of claim 1, wherein the offset time and the filter time for each verification chip are generated by:

after the layout and wiring are completed between the verification chips based on the segmented netlist designs, traversing each segmented netlist design, and determining the maximum value of data path delay under UCLK clock domains, the maximum value of all gate clock offsets and the delay value of an interconnection module between the verification chips in all designs;

based on inequality Skew time not less than Max (Td) +s and Filter time not less than Max (Tc) +s, obtaining the maximum value of Skew time of each verification chip as offset time of each verification chip, and the Filter of each verification chip

the maximum value of the time is taken as the filtering time of each verification chip.

4. A clock synchronization method for a multichip system as claimed in claim 2 or 3, wherein the PCB trace for transmitting the PLL clock to each verification chip is routed using a shortest path.

5. The method for clock synchronization of a multichip system according to claim 2 or 3, wherein the verification chip outputs a high level signal of uclk_ready after UCLK is in phase, outputs a high level Ready signal after chip Ready signal phase of the verification chip, and notifies the control chip that the in phase is completed.

6. A multichip system comprising a control chip and a plurality of verification chips, wherein the control chip and the plurality of verification chips are clock synchronized using the clock synchronization method of the multichip system of any one of claims 1 to 3.

7. The multi-chip system of claim 6, wherein the control chip comprises:

the clock control module is used for managing the clock generation module and the control interface;

the clock generation module generates a PLL clock, and comprises a frequency division circuit and a register controlled by the frequency division circuit, and the enabling of the output corresponding to the register is realized by configuring the register;

the control interface is connected with the control interface of each verification chip and is used for transmitting control signals and feedback data between the control chip and the verification chip.

8. The multi-chip system of claim 6, wherein the verification chip comprises:

a verification circuit corresponding to the segmented netlist design distributed on the verification chip;

at least one interconnection module for connecting with a corresponding one of the other verification chips according to the layout wiring between the verification chips;

a clock generation module that generates UCLK based on the PLL clock;

and the control interface is connected with the control interface of the control chip.

9. The multi-chip system of any of claims 6 to 8, wherein the multi-chip system is a multi-FPGA system, the control chip is a CTRL FPGA, and the verification chip is a DUT FPGA.