CN115933808A - Multichannel DDS signal source - Google Patents
Multichannel DDS signal source Download PDFInfo
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- CN115933808A CN115933808A CN202211703881.4A CN202211703881A CN115933808A CN 115933808 A CN115933808 A CN 115933808A CN 202211703881 A CN202211703881 A CN 202211703881A CN 115933808 A CN115933808 A CN 115933808A
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Abstract
The invention discloses a multichannel DDS signal source, which comprises: the system comprises an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels; wherein, the DDS signal channel includes: the DDS chip, the balun, the low-pass filter, the variable attenuator, the fixed attenuator, the amplifier and the analog switch are connected in sequence; the clock chip provides a sampling clock for each DDS chip and a reference clock for the FPGA; the clock fan-out chip provides SYNC _ IN signals for each DDS chip respectively; the FPGA is used for monitoring a SYNC _ SMP _ ERR signal of each DDS chip, and dynamically adjusting a delay value of each DDS chip for receiving the SYNC _ IN signal if the SYNC _ SMP _ ERR signal is monitored to be a high level; respectively controlling the attenuation value of each variable attenuator according to the amplitude curve in the preset pass band; therefore, the invention can not only improve the synchronization precision of the signal channel, but also realize the stepping attenuation function of the amplitude under the condition of ensuring the output flatness.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a multichannel DDS signal source.
Background
The Direct Digital Synthesizer (DDS) has the advantages of digitally controllable and adjustable frequency, phase and amplitude of output signal, high resolution of output frequency, and fast frequency change, and can be widely applied to the fields of communication, radar, ultrasonic wave, etc. With the requirement that the bandwidth of the intermediate frequency signal output by the DDS is higher and higher, a great challenge is brought to the control design of the synchronization precision and the flatness in the passband of the DDS.
Disclosure of Invention
The embodiment of the invention provides a multichannel DDS signal source, which not only can improve the synchronization precision of signal channels, but also can realize the stepping attenuation function of amplitude under the condition of ensuring the output flatness.
In order to achieve the purpose, the invention provides the following technical scheme:
a multichannel DDS signal source, comprising: the system comprises an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels; wherein the content of the first and second substances,
the DDS signal channels include: the DDS chip, the balun, the low-pass filter, the variable attenuator, the fixed attenuator, the amplifier and the analog switch are connected in sequence;
the clock chip is used for respectively providing a sampling clock for the DDS chip of each DDS signal channel and providing a reference clock for the FPGA;
the clock fan-out chip is used for respectively providing SYNC _ IN signals for the DDS chips of each DDS signal channel;
the FPGA is respectively connected with the DDS chips of each DDS signal channel, the controllable attenuator and the analog switch, and is used for monitoring SYNC _ SMP _ ERR signals of each DDS chip, and dynamically adjusting the delay value of each DDS chip for receiving SYNC _ IN signals if the SYNC _ SMP _ ERR signals are monitored to be high level; respectively controlling the attenuation value of each variable attenuator according to an amplitude curve in a preset pass band; and controlling a corresponding number of analog switches to respectively conduct the corresponding DDS signal channels according to the set number of channels.
In a specific embodiment, the clock chips respectively have the same routing length to the sampling clock input pin of the DDS chip of each DDS signal channel; and the routing lengths from the clock fan-out chip to the SYNC _ IN signal input pins of the DDS chips of each DDS signal channel are equal.
In a specific embodiment, the FPGA is respectively connected to the I/O _ RESET pins of the DDS chips of each DDS signal channel and has the same trace length, the FPGA is respectively connected to the SYNC _ CLK pins of the DDS chips of each DDS signal channel and has the same trace length, the FPGA is respectively connected to the I/O _ UPDATE pins of the DDS chips of each DDS signal channel and has the same trace length, and the FPGA is respectively connected to the PROFILE pins of the DDS chips of each DDS signal channel and has the same trace length.
In a specific embodiment, the FPGA is configured to: outputting an I/O _ RESET signal, an I/O _ UPDATE signal and a PROFILE signal through a programmable input and output unit; and, at the falling edge of the SYNC _ CLK signal, the I/O _ UPDATE signal is output to the I/O _ UPDATE pin of the DDS chip, and/or the PROFILE signal is output to the PROFILE pin of the DDS chip.
In a specific embodiment, the signal input of the clock fan-OUT chip is provided by a signal output from a SYNC _ OUT pin of the DDS chip.
In one specific embodiment, the variable attenuator provides an attenuation step-adjustable of 0.5 dB.
In a specific embodiment, the FPGA is configured to control the operation of the clock chip and each DDS chip according to a program loaded thereon.
In a specific embodiment, the FPGA is connected to a FLASH module and a DDR3 module; the FLASH module is used for storing a program of the FPGA; and the DDR3 module is used for caching the operation data of the FPGA.
In a specific embodiment, the multichannel DDS signal source of the invention further includes: the power supply comprises a digital power supply module and an analog power supply module; the digital power supply module is used for providing power for the FPGA, the FLASH module and the DDR3 module; the analog power supply module is used for providing power for the clock chip, the DDS chip in each DDS signal channel, the variable attenuator, the amplifier and the analog switch.
In a specific embodiment, the FPGA is configured with a network interface or a serial interface for interacting with an upper computer.
Therefore, the multichannel DDS signal source provided by the embodiment of the invention can improve the synchronization precision of the signal channel and realize the amplitude stepping attenuation function under the condition of ensuring the output flatness.
Description of the drawings:
fig. 1 is a schematic diagram of an architecture of a multi-channel DDS signal source according to an embodiment of the invention;
fig. 2 is a schematic diagram of connections among an FPGA, a clock chip, a clock fan-out chip, and a plurality of DDS chips according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
As shown in fig. 1 and 2, the present invention provides a multichannel DDS signal source including: the system comprises an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels; wherein the content of the first and second substances,
the DDS signal channels include: the DDS chip, the balun, the low-pass filter, the variable attenuator, the fixed attenuator, the amplifier and the analog switch are connected in sequence;
the clock chip is used for respectively providing a sampling clock for the DDS chip of each DDS signal channel and providing a reference clock for the FPGA;
the clock fan-out chip is used for respectively providing SYNC _ IN signals for the DDS chips of each DDS signal channel;
the FPGA is respectively connected with the DDS chips of each DDS signal channel, the controllable attenuator and the analog switch, and is used for monitoring SYNC _ SMP _ ERR signals of each DDS chip, and dynamically adjusting the delay value of each DDS chip for receiving SYNC _ IN signals if the SYNC _ SMP _ ERR signals are monitored to be high level; respectively controlling the attenuation value of each variable attenuator according to an amplitude curve in a preset pass band; and controlling a corresponding number of analog switches to respectively conduct the corresponding DDS signal channels according to the set number of channels.
In the invention, the DDS chip adopts AD9910, the AD9910 is a direct digital frequency synthesizer (DDS) with a built-in 14bit DAC, the sampling rate of 1GSPS is supported, and the tuning resolution is-0.23 Hz at the sampling rate of 1 GSPS; meanwhile, a user can program an internal control register of the AD9910 through the serial I/O port to realize the control of the AD9910, the AD9910 integrates a static RAM and can support various combinations of frequency, phase and/or amplitude modulation, and a high-speed parallel data input port built in the AD9910 can realize the direct modulation of frequency, phase, amplitude or pole to support higher-level modulation functions.
IN the invention, whether the DDS chip normally receives the SYNC _ IN signal is judged by monitoring the synchronous SYNC _ SMP _ ERR signal; if the SYNC _ SMP _ ERR signal is at a high level or unstable, the SYNC reception delay value of the slave chip needs to be dynamically adjusted to ensure that the input meets the setup hold time.
The synchronization between the DDS signal channels is ensured from the hardware level, and the routing lengths from the clock chips to the sampling clock input pins of the DDS chips of each DDS signal channel are required to be equal on the hardware; the clock fan-out chip has the same routing length from the clock fan-out chip to the SYNC _ IN signal input pin of the DDS chip of each DDS signal channel; the FPGA is respectively connected to the I/O _ RESET pins of the DDS chips of each DDS signal channel, and the routing lengths of the I/O _ RESET pins are equal; the FPGA is respectively connected to the SYNC _ CLK pin of the DDS chip of each DDS signal channel, the FPGA is respectively connected to the I/O _ UPDATE pin of the DDS chip of each DDS signal channel, the FPGA is respectively connected to the PROFILE pin of the DDS chip of each DDS signal channel, and the FPGA is respectively connected to the PROFILE pin of the DDS chip of each DDS signal channel.
The method has the advantages that the synchronism among DDS signal channels is guaranteed on the software level, and the situation that the maintenance time cannot be established can exist even after the corresponding state is changed by sending a PROFILE signal and an I/O _ UPDATE signal by the FPGA when the DDS signal source works, so that the synchronism among the DDS signal channels is influenced; thus, the FPGA is configured to: outputting an I/O _ RESET signal, an I/O _ UPDATE signal and a PROFILE signal through a programmable input output unit; thus, the FPGA can step the signal to 78ps fine adjustment through a programmable input output unit (IOB) in the FPGA; meanwhile, in order to ensure the synchronization stability, the impedance matching from the FPGA to the AD9910 is required to be good, and the overshoot and undershoot do not exceed the TTL misjudgment level.
Further, when the SYNC _ CLK signal falls, the I/O _ UPDATE signal is output to the I/O _ UPDATE pin of the DDS chip, and/or the PROFILE signal is output to the PROFILE pin of the DDS chip, so that the setup holding time is completely met when the FPGA outputs all the PROFILE signals and the I/O _ UPDATE signals and the SYNC clock signal rising edge of each DDS chip.
Regarding the flatness of DDS signals generated by a DDS signal channel, an amplitude curve in the whole passband is planned in advance through early-stage testing, and the output flatness is ensured by controlling the attenuation parameters of the variable attenuator at different frequency points through an algorithm in the later stage, so that the amplitude stepping attenuation function is realized under the condition of ensuring the output flatness. Further, the variable attenuator provides attenuation step adjustment of 0.5dB, and the maximum attenuation of-30 dB can be realized by combining with the fixed attenuator.
Specifically, the clock chip adopts the HMC7044, an external reference clock or an on-board temperature compensation crystal oscillator can be used as a reference clock and input to the clock chip HMC7044 to be used as a reference clock of the PLL, and the clock chip HMC7044 generates a 1GHz clock to the AD9910 to be used as a sampling clock and generates a clock to the FPGA to be used as a reference clock. The clock fan-OUT chip can be connected with an external SYNC input or SYNC _ OUT of one DDS chip, and the SYNC _ OUT of one DDS chip is connected with the clock fan-OUT chip, so that one DDS chip is used as a master chip, and the other DDS chips are used as slave chips, therefore, the complexity of synchronous control can be reduced, and the system design can be simplified.
Through the technical means, the multichannel DDS signal source can control the DDS chip and the clock chip through the FPGA to realize the generation of multichannel 0-400MHz intermediate frequency signals, has the functions of independently controlling and programming each channel to independently perform amplitude attenuation control, phase control, frequency control and step control, and realizes multichannel phase synchronization through logic control. Taking the DDS chip AD9910 and the clock chip HMC7044 as examples, the synchronization precision between channels can be improved to be within 50 ps.
Specifically, the FPGA is configured to control the operations of the clock chip and each DDS chip according to a loaded program. Moreover, the FPGA is connected with a FLASH module and a DDR3 module; the FLASH module is used for storing a program of the FPGA; and the DDR3 module is used for caching the operation data of the FPGA.
After the system is powered on, the FPGA starts to load programs from the FLASH module; after the program is started, the interior of the FPGA starts to automatically configure a clock chip according to an internal clock mode set in the program, after the clock is locked, the electrification and initialization of each DDS signal channel are started to be controlled, and after the initialization of the DDS chip is successful, the whole initialization of the system is finished. The user can control the upper computer to interact with the FPGA through a serial port or a network port, and further has the functions of reading and writing through a DDS chip of the FPGA control system, configuring the number of analog front ends, PROFILE _ PIN selection, DDR3 data reading and writing, clock mode switching, channel switching and the like; the upper computer can be connected with a serial port of the FPGA through a USB-to-serial port chip CP 2103.
Specifically, the multichannel DDS signal source of the invention further includes: the power supply comprises a digital power supply module and an analog power supply module; the digital power supply module is used for providing power for the FPGA, the FLASH module and the DDR3 module; the analog power supply module is used for providing power for the clock chip, the DDS chip in each DDS signal channel, the variable attenuator, the amplifier and the analog switch.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A multi-channel DDS signal source comprising: the system comprises an FPGA, a clock chip, a clock fan-out chip and a plurality of DDS signal channels; wherein the content of the first and second substances,
the DDS signal channels include: the DDS chip, the balun, the low-pass filter, the variable attenuator, the fixed attenuator, the amplifier and the analog switch are connected in sequence;
the clock chip is used for respectively providing a sampling clock for the DDS chip of each DDS signal channel and providing a reference clock for the FPGA;
the clock fan-out chip is used for respectively providing SYNC _ IN signals for the DDS chips of each DDS signal channel;
the FPGA is respectively connected with the DDS chips of each DDS signal channel, the controllable attenuator and the analog switch, and is used for monitoring SYNC _ SMP _ ERR signals of each DDS chip, and dynamically adjusting the delay value of each DDS chip for receiving SYNC _ IN signals if the SYNC _ SMP _ ERR signals are monitored to be high level; respectively controlling the attenuation value of each variable attenuator according to an amplitude curve in a preset pass band; and controlling a corresponding number of analog switches to respectively conduct the corresponding DDS signal channels according to the set number of channels.
2. The multi-channel DDS signal source of claim 1, wherein the clock chips have equal trace lengths to the sampling clock input pins of the DDS chips of each DDS signal channel; and the routing lengths from the clock fan-out chips to the SYNC _ IN signal input pins of the DDS chips of each DDS signal channel are equal.
3. The multi-channel DDS signal source of claim 2, wherein the I/O _ RESET pins of the DDS chips respectively connected to each of said DDS signal channels of said FPGA have the same trace length, the SYNC _ CLK pins of the DDS chips respectively connected to each of said DDS signal channels of said FPGA have the same trace length, the I/O _ UPDATE pins of the DDS chips respectively connected to each of said DDS signal channels of said FPGA have the same trace length, and the PROFILE pins of the DDS chips respectively connected to each of said DDS signal channels of said FPGA have the same trace length.
4. The multi-channel DDS signal source of claim 1, wherein said FPGA is configured to: outputting an I/O _ RESET signal, an I/O _ UPDATE signal and a PROFILE signal through a programmable input output unit; also, upon a falling edge of the SYNC _ CLK signal, an I/O _ UPDATE signal is output to an I/O _ UPDATE pin of the DDS chip and/or a PROFILE signal is output to a PROFILE pin of the DDS chip.
5. The multi-channel DDS signal source of claim 1, wherein the signal input of said clock fan-OUT die is provided by a signal output from a SYNC _ OUT pin of said DDS die.
6. A multi-channel DDS signal source as claimed in claim 1 wherein the variable attenuator provides an attenuation step adjustable of 0.5 dB.
7. A multichannel DDS signal source as claimed in any of claims 1 to 6, wherein said FPGA is configured to control the operation of said clock chips and each DDS chip in accordance with a program loaded thereon.
8. The multi-channel DDS signal source of claim 7 wherein said FPGA is connected to a FLASH module and a DDR3 module; wherein, the first and the second end of the pipe are connected with each other,
the FLASH module is used for storing the program of the FPGA;
and the DDR3 module is used for caching the operation data of the FPGA.
9. A multi-channel DDS signal source as claimed in claim 8 further including: the power supply comprises a digital power supply module and an analog power supply module; wherein, the first and the second end of the pipe are connected with each other,
the digital power supply module is used for providing power for the FPGA, the FLASH module and the DDR3 module;
the analog power supply module is used for providing power for the clock chip, the DDS chip in each DDS signal channel, the variable attenuator, the amplifier and the analog switch.
10. The multi-channel DDS signal source of claim 1 wherein said FPGA is configured with a network interface or a serial interface for interfacing with an upper computer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211703881.4A CN115933808A (en) | 2022-12-29 | 2022-12-29 | Multichannel DDS signal source |
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| CN202211703881.4A CN115933808A (en) | 2022-12-29 | 2022-12-29 | Multichannel DDS signal source |
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