CN209842446U - Digital frequency synthesis chip full-coherent signal source circuit - Google Patents
Digital frequency synthesis chip full-coherent signal source circuit Download PDFInfo
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- CN209842446U CN209842446U CN201920930869.4U CN201920930869U CN209842446U CN 209842446 U CN209842446 U CN 209842446U CN 201920930869 U CN201920930869 U CN 201920930869U CN 209842446 U CN209842446 U CN 209842446U
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- 230000001427 coherent effect Effects 0.000 claims abstract description 25
- 230000001360 synchronised effect Effects 0.000 claims abstract description 10
- 238000001514 detection method Methods 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 4
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Abstract
The utility model belongs to the technical field of coherent signal source circuit, concretely relates to digital frequency synthesis chip is coherent signal source circuit entirely. The full-coherent signal source power circuit comprises a control circuit, wherein the control circuit controls a DDS chip through a control signal, the DDS chip generates an analog signal to be output, the input end of the DDS chip is connected with a reference clock, the DDS circuit generates an internal clock signal based on the reference clock, the internal clock signal is fed back to the control circuit, and the control circuit outputs a synchronous pulse signal. The control signals include timing control and register configuration. The control circuit core is a singlechip, a CPLD, an FPGA or a DSP and is used for generating a control signal according to a control instruction. The utility model discloses an above-mentioned technical scheme realizes the requirement of complex system to the signal degree of accuracy, realizes the signal source with the synchronous looks coherence of entire system, and this circuit has multiple extension mode, and a letter both is applicable to the looks coherence signal source circuit all the way, is applicable to multichannel looks coherence signal source again.
Description
Technical Field
The utility model belongs to the technical field of coherent signal source circuit, concretely relates to digital frequency synthesis chip is coherent signal source circuit entirely.
Background
Coherent means that the initial phase between the pulses is deterministic, the initial phase of the first pulse may be random, but the phase between the subsequent pulse and the first pulse is deterministic, which is the basis for extracting the doppler information. The randomness of the initial phase of the first pulse does not affect the subsequent detection of the signal because the detection is preceded by the modulus. Non-coherent means that the initial phases between pulses are all random and uncorrelated with each other.
Current electronic systems, such as coherent accumulation radar systems, doppler radar systems, phase modulation communication systems, etc., require a signal source that is synchronized with the entire system to perform their complex functions. A simple and reliable design scheme for coherent signal sources is a problem that needs to be solved in the electronic system.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a digital frequency synthesis chip full-phase coherent signal source circuit to the requirement of the current complex system of adaptation to the signal degree of accuracy.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a digital frequency synthesis chip full-coherent signal source circuit comprises a control circuit, wherein the control circuit controls a DDS chip through a control signal, the DDS chip generates an analog signal output, the input end of the DDS chip is connected with a reference clock, the DDS circuit generates an internal clock signal based on the reference clock, the internal clock signal is fed back to the control circuit, and the control circuit outputs a synchronous pulse signal.
Preferably, the control signal includes a timing control and a register configuration.
Preferably, the control circuit is designed with a core of a single chip microcomputer, a CPLD, an FPGA or a DSP, and is configured to receive a control instruction and generate a control signal according to the control instruction.
Preferably, the core of the DDS chip is AD9954, AD9910, or AD9914, and is configured to receive a control signal of the control circuit, and output a desired analog signal according to the control signal.
Preferably, the internal clock is coherent with the reference clock, and the internal clock frequency is one half to thirty-half of the reference clock frequency.
Preferably, the DDS chip generates the analog signal through a filter module, and the filter module is configured to suppress harmonics of the output analog signal.
Preferably, the filter module is an LC band-pass filter with a passband of 150-250 MHz.
Preferably, the analog signal output by the filter module is detected by generating an analog signal through a self-checking module, and the self-checking module mainly functions to monitor the analog signal in real time.
Preferably, the self-checking module comprises a sampling circuit, a detection circuit and a comparison circuit.
Preferably, the DDS chips are multiple, the control circuit controls the DDS chips through multiple control signals, the DDS chips generate corresponding analog signals to be output, the clock distribution chip outputs multiple reference clocks to generate internal clocks of the DDS chips, one internal clock of the DDS chip is fed back to the control circuit, and the control circuit outputs a synchronization pulse signal.
The utility model discloses a digital frequency synthesis chip is coherent signal source circuit entirely, compare produced beneficial effect with prior art and be:
the signal source of the invention mainly comprises a control circuit and a DDS circuit,
the control circuit can be generally designed by taking a singlechip, a CPLD, an FPGA, a DSP and the like as cores, and has the main functions of configuring a DDS circuit register and controlling the DDS working time sequence after the circuit is electrified.
The DDS circuit is a frequency synthesis circuit with a digital frequency synthesis chip as a core, such as AD9954, AD9910, AD9914, and so on. Its main function is to receive the register control word and control signal of the control circuit, and to output the required analog signal according to the register setting and time sequence control of the control circuit.
The reference clock signal is used as a DAC clock of the DDS circuit and is input through a reference clock pin of the digital frequency synthesis chip, and the reference clock signal is a reference of all coherent signals of the signal source.
The SYNC _ CLK signal is an internal working clock of the digital frequency synthesis chip, is coherent with a reference clock signal, has a frequency which is a fraction of the reference clock signal, and has different frequency division ratios of various types of digital frequency synthesis chips. The SYNC _ CLK signal is input via the control circuit I/O port as a clock for the control circuit to generate the control signal and the synchronization pulse signal.
The utility model discloses an above-mentioned technical scheme realizes the requirement of complex system to the signal accuracy, and this circuit has multiple extension mode, both has been applicable to coherent signal source circuit all the way, is applicable to multichannel coherent signal source again.
Drawings
Fig. 1 is a schematic diagram of a circuit of a coherent signal source of a single-channel output digital frequency synthesis chip according to the present invention;
fig. 2 is a schematic diagram of a circuit of a coherent signal source of a multiple output digital frequency synthesis chip according to the present invention;
fig. 3 is a schematic diagram of an application example of the 2-way output full-coherent signal source circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail with reference to the accompanying drawings 1-3 and specific examples.
EXAMPLE one (Single output)
With reference to fig. 1, a digital frequency synthesis chip full-coherent signal source circuit includes a control circuit, the control circuit controls a DDS chip through a control signal, the DDS chip generates an analog signal output, an input end of the DDS chip is connected to a reference clock, the DDS circuit generates an internal clock signal based on the reference clock, the internal clock signal is fed back to the control circuit, and the control circuit outputs a synchronization pulse signal.
Wherein the control signal includes timing control and register configuration.
The control circuit is designed to be a single chip microcomputer, a CPLD, an FPGA or a DSP, and is used for receiving a control instruction and generating a control signal according to the control instruction.
The core of the DDS chip is AD9954, AD9910 or AD9914, and is used for receiving a control signal of the control circuit and outputting a required analog signal according to the control signal.
The SYNC _ CLK signal is an internal clock of the digital frequency synthesis chip, and is coherent with the reference clock, the SYNC _ CLK signal internal clock is input through an I/O port of the control circuit and is used as a clock for the control circuit to generate a control signal and a synchronous pulse signal, and the internal clock frequency is one half to thirty-half of the reference clock frequency.
EXAMPLE two (Multiplexed output)
With reference to fig. 2, the circuit for the digital frequency synthesis chip full-coherent signal source comprises a control circuit, wherein the control circuit controls a plurality of DDS chips through a control signal, the plurality of DDS chips are controlled by the control circuit through a plurality of control signals, the plurality of DDS chips generate corresponding analog signal output, a plurality of reference clocks are output through a clock distribution chip to generate internal clocks of the plurality of DDS chips, the internal clocks of the 1 st DDS chip are fed back to the control circuit, and the control circuit outputs a synchronous pulse signal.
Wherein the control signal includes timing control and register configuration.
The control circuit is designed to be a single chip microcomputer, a CPLD, an FPGA or a DSP, and is used for receiving a control instruction and generating a control signal according to the control instruction.
The core of the DDS chip is AD9954, AD9910 or AD9914, and is used for receiving a control signal of the control circuit and outputting a required analog signal according to the control signal.
The SYNC _ CLK signal is an internal clock of the digital frequency synthesis chip, and is coherent with the reference clock, the SYNC _ CLK signal internal clock is input through an I/O port of the control circuit and is used as a clock for the control circuit to generate a control signal and a synchronous pulse signal, and the internal clock frequency is one half to thirty-half of the reference clock frequency.
EXAMPLE three (2 way output)
With reference to fig. 3, a digital frequency synthesis chip full-coherent signal source circuit comprises a control circuit, wherein the control circuit controls 2 DDS chips through a control signal, the control circuit controls 2 DDS chips through 2 control signals, the 2 DDS chips generate corresponding analog signal output, 2 reference clocks are output through a clock distribution chip to generate internal clocks of the 2 DDS chips, the internal clocks of the 1 st DDS chip are fed back to the control circuit, and the control circuit outputs a synchronous pulse signal.
The control circuit design core is FPGA. The UART serial interface is mainly adopted to receive a control instruction, and register configuration is carried out on 2 DDS chips through an SPI serial peripheral interface bus mode according to the received control instruction, so that frequency, amplitude and phase control of signals generated by the 2 DDS chips are completed.
The core of the DDS chip is two AD9910 chips, the AD9910 chip is a digital frequency synthesis chip with a built-in 14-bit digital-analog converter, the sampling rate of the DDS chip is up to 1GSPS, 32-bit frequency control words are supported, and the phase noise is offset by less than or equal to-125 dBc/Hz @1 KHz. The two AD9910 chips are controlled by the register configuration and the time sequence of the FPGA module to generate corresponding analog signals with controlled frequency, amplitude and phase.
The internal clock is coherent with the reference clock, the reference clock is 1GHz, the internal clock is 250MHz, and the frequency of the internal clock is one fourth of the frequency of the reference clock. The core of the clock distribution chip circuit is AD9514, the AD9514 chip is a multi-output clock distribution chip, the clock distribution chip has low jitter and low phase noise characteristics, 2 independent clock outputs can be provided, and the working frequency can reach 1.6 GHz.
And a filter module is arranged between the DDS chip and the analog signal. The filter module is an LC band-pass filter with a pass band of 150-250 MHz, and mainly functions to suppress harmonic waves of analog signals output by the digital frequency synthesis chip.
The analog signal output by the filter module is generated into an analog signal through the self-checking module for detection, the self-checking module comprises a sampling circuit, a detection circuit and a comparison circuit, and the main function of the self-checking module is to monitor the analog signal in real time.
Wherein the control signal includes timing control and register configuration.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical substance of the present invention still belong to the protection scope of the technical solution of the present invention.
Claims (10)
1. A digital frequency synthesis chip full-coherent signal source circuit is characterized in that: the DDS control circuit controls a DDS chip through a control signal, the DDS chip generates an analog signal to be output, the input end of the DDS chip is connected with a reference clock, the DDS circuit generates an internal clock signal based on the reference clock, the internal clock signal is fed back to the control circuit, and the control circuit outputs a synchronous pulse signal.
2. The digital frequency synthesis chip fully coherent signal source circuit according to claim 1, wherein: the control signals include timing control and register configuration.
3. The digital frequency synthesis chip full-coherent signal source circuit according to claim 1 or 2, characterized in that: the control circuit is designed to be a single chip microcomputer, a CPLD, an FPGA or a DSP, and is used for receiving a control instruction and generating a control signal according to the control instruction.
4. The digital frequency synthesis chip full-coherent signal source circuit according to claim 1 or 2, characterized in that: the core of the DDS chip is AD9954, AD9910 or AD9914, and is used for receiving the control signal of the control circuit and outputting the required analog signal according to the control signal.
5. The digital frequency synthesis chip full-coherent signal source circuit according to claim 1 or 2, characterized in that: the internal clock is coherent with the reference clock, the internal clock frequency being one-half to thirty-half of the reference clock frequency.
6. The digital frequency synthesis chip full-coherent signal source circuit according to claim 1 or 2, characterized in that: the DDS chip generates the analog signal through a filter module, and the filter module is used for suppressing harmonic waves of the output analog signal.
7. The digital frequency synthesis chip fully coherent signal source circuit of claim 6, wherein: the filter module is an LC band-pass filter with a pass band of 150-250 MHz.
8. The digital frequency synthesis chip fully coherent signal source circuit of claim 6, wherein: the analog signal output by the filter module generates an analog signal through the self-checking module to detect, and the self-checking module is used for monitoring the analog signal in real time.
9. The digital frequency synthesis chip fully coherent signal source circuit of claim 8, wherein: the self-checking module comprises a sampling circuit, a detection circuit and a comparison circuit.
10. The digital frequency synthesis chip fully coherent signal source circuit of claim 6, wherein: the DDS chip is provided with a plurality of DDS chips, the control circuit controls the plurality of DDS chips through a plurality of control signals, the plurality of DDS chips generate corresponding analog signal output, a plurality of reference clocks are output through the clock distribution chip to generate internal clocks of the plurality of DDS chips, one internal clock of the DDS chip is fed back to the control circuit, and the control circuit outputs a synchronous pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201920930869.4U CN209842446U (en) | 2019-06-20 | 2019-06-20 | Digital frequency synthesis chip full-coherent signal source circuit |
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| CN201920930869.4U CN209842446U (en) | 2019-06-20 | 2019-06-20 | Digital frequency synthesis chip full-coherent signal source circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114594825A (en) * | 2022-03-28 | 2022-06-07 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
| CN116578164A (en) * | 2023-07-13 | 2023-08-11 | 中星联华科技（北京）有限公司 | Multichannel coherent signal generating device and multichannel coherent signal source |
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2019
- 2019-06-20 CN CN201920930869.4U patent/CN209842446U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114594825A (en) * | 2022-03-28 | 2022-06-07 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
| CN114594825B (en) * | 2022-03-28 | 2024-04-12 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
| CN116578164A (en) * | 2023-07-13 | 2023-08-11 | 中星联华科技（北京）有限公司 | Multichannel coherent signal generating device and multichannel coherent signal source |
| CN116578164B (en) * | 2023-07-13 | 2023-09-29 | 中星联华科技（北京）有限公司 | Multichannel coherent signal generating device and multichannel coherent signal source |
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Granted publication date: 20191224 |