CN116449170A - Testing device and testing method for testing two-pin device and three-pin device - Google Patents

Testing device and testing method for testing two-pin device and three-pin device Download PDF

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Publication number
CN116449170A
CN116449170A CN202310698564.6A CN202310698564A CN116449170A CN 116449170 A CN116449170 A CN 116449170A CN 202310698564 A CN202310698564 A CN 202310698564A CN 116449170 A CN116449170 A CN 116449170A
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relay
testing
pin
circuit
test
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CN202310698564.6A
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CN116449170B (en
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何嘉辉
陈希辰
钟有权
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Foshan Linkage Technology Co ltd
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Foshan Linkage Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2632—Circuits therefor for testing diodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The invention provides a testing device and a testing method for testing a two-pin device and a three-pin device, wherein the testing device comprises a grid driving circuit, a voltage providing circuit, a testing circuit, a device to be tested and a first switching device, the testing circuit is provided with a first connecting endpoint to a third connecting endpoint, and the device to be tested is the two-pin or three-pin device and is connected to the testing circuit through the connection; the grid driving circuit is connected with the grid of the first switching device, the positive electrode end of the voltage supply circuit is connected with the drain electrode of the first switching device, the source electrode of the first switching device is connected with the first connecting end point, the negative electrode of the voltage supply circuit and the second connecting end point are both connected with the first node, the testing circuit collects voltages between all ports of the device to be tested from the first connecting end point to the third connecting end point, and collects currents flowing through the device to be tested from the second connecting end point so as to be compatible with measuring of the two-leg device and the three-leg device, a testing device does not need to be replaced when the device type is replaced, the number of the testing device is reduced, and the relevant investment of the device is reduced.

Description

Testing device and testing method for testing two-pin device and three-pin device
Technical Field
The invention relates to the field of test circuits, in particular to a test device and a test method for testing two-pin devices and three-pin devices.
Background
Currently, when a two-pin device and a three-pin device are required to be measured in an application environment, the two-pin device is a diode, the three-pin device is a triode such as a MOSFET (or an IGBT), and currently two devices and two sets of measurement loops are generally required to be used for measurement respectively, that is, the two-pin device and the three-pin device are not universal, so that when the two-pin device is measured or the three-pin device is measured, the test device needs to be replaced, thus increasing the cost investment of the device, increasing the time cost of the replacement device, increasing the maintenance cost and increasing the measurement cost, and finally leading to the unit price of the device. In addition, the two sets of testing devices occupy more environmental resources, and when a user needs to test various devices (such as two-pin devices and three-pin devices), more frequent application environments appear, which causes great inconvenience.
Disclosure of Invention
The invention aims to provide a testing device and a testing method for testing two-pin devices and three-pin devices, which can be used for compatibly measuring the two-pin devices and the three-pin devices without replacing the testing device when the types of the devices are replaced, thereby reducing the number of the testing devices and reducing the related investment of the devices.
The invention provides a testing device for testing a two-pin device and a three-pin device, which comprises a grid driving circuit, a voltage providing circuit, a testing circuit, a device to be tested and a first switching device, wherein the testing circuit is provided with a first connecting endpoint, a second connecting endpoint and a third connecting endpoint;
the grid driving circuit is connected with the grid of the first switching device, the positive electrode end of the voltage supply circuit is connected with the drain electrode of the first switching device, the source electrode of the first switching device is connected with the first connecting end point, the negative electrode of the voltage supply circuit and the second connecting end point are connected with the first node, the testing circuit collects voltages among all ports of the device to be tested from the first connecting end point, the second connecting end point and the third connecting end point, and collects current flowing through the device to be tested from the second connecting end point.
Optionally, when the device to be tested is a triode, the first connection endpoint is connected with a drain electrode of the triode, the second connection endpoint is connected with a gate electrode of the triode, and the third connection endpoint is connected with a source electrode of the triode;
when the device to be tested is a diode, the first connection terminal is connected with the cathode of the diode, and the second connection terminal is connected with the anode of the diode.
Optionally, the test circuit comprises a constant current source circuit, a first current sensor, a second current sensor, a third current sensor, a power inductor, an acquisition unit, a first relay to a fifth relay, wherein the first relay, the third relay, the fourth relay and the fifth relay are single-knife single-placed relays, the second relay is a double-knife double-placed relay, so that the second relay comprises a first knife, a second knife and four ports,
the first knife is connected with the constant current source circuit and the acquisition unit, the second knife is grounded, the first port and the fourth port are both connected with one end of the third relay and one end of the fourth relay at the same time, the second port and the third port are both connected with the second connection endpoint, the other end of the third relay is connected with the third connection endpoint, the other end of the fourth relay and one end of the fifth relay are both connected with the first connection endpoint, the first connection endpoint is also connected with the acquisition unit and the source electrode of the first switching device, the other end of the fifth relay is connected with one end of the power inductor, the second connection endpoint is connected with the input end of the third current sensor through a first wire, the first wire is arranged in the first current sensor in a penetrating mode, the other end of the power inductor is connected with the first node through a second wire, the second wire is arranged in the second current sensor in a penetrating mode, the first output end of the third current sensor is connected with the first output end of the third current sensor, and the second output end of the third current sensor is connected with the first output unit.
Further, the constant current source circuit comprises a constant current source, a high voltage diode and a first power supply, the test circuit further comprises an operational amplifier circuit, the operational amplifier circuit comprises two input ends and an output end,
the output end of the operational amplifier circuit is simultaneously connected with the acquisition unit and the second input end of the operational amplifier circuit, the first input end of the operational amplifier circuit is simultaneously connected with the output end of the constant current source and the positive electrode of the high voltage diode, the input end of the constant current source is connected with the positive electrode of the first power supply, the negative electrode of the first power supply is grounded, and the negative electrode of the high voltage diode is connected with the first knife.
Further, the gate driving circuit comprises an operational amplifier, a first diode, a second diode, a first resistor, a second resistor, a driving signal source, a second power supply and a third power supply, the operational amplifier comprises an input end, an output end, a positive power supply end and a negative power supply end,
the input end of the operational amplifier is connected with the driving signal source, the positive power end of the operational amplifier is connected with the positive electrode of the second power supply, the negative power end of the operational amplifier is connected with the negative electrode of the third power supply, the negative electrode of the second power supply and the positive electrode of the third power supply are simultaneously grounded, the output end of the operational amplifier is simultaneously connected with the positive electrode of the first diode and the negative electrode of the second diode, the negative electrode of the first diode is connected with one end of the first resistor, the positive electrode of the second diode is connected with one end of the second resistor, and the other end of the first resistor and the other end of the resistor are simultaneously connected with the grid electrode of the first switching device.
Further, the voltage supply circuit comprises a high-power programmable power supply, a first capacitor, a second capacitor and a second switching device,
the drain electrode of the first switching device is simultaneously connected with one end of the capacitor and the source electrode of the second switching device, the grid electrode of the second switching device inputs a driving signal, the drain electrode of the second switching device is simultaneously connected with one end of the capacitor and one end of the first relay, the other end of the relay is connected with the positive electrode of the high-power programmable power supply, and the negative electrode of the high-power programmable power supply, the other end of the capacitor and the other end of the capacitor are all connected with a first node.
In another aspect, the present invention also provides a test method for testing a two-pin device and a three-pin device, comprising the steps of:
step S1: providing the testing device and the device to be tested for testing the two-pin device and the three-pin device, and mounting the device to be tested on the testing device through a connecting end point of the testing device;
step S2: the states of the first relay to the fifth relay are adjusted for the first time, the voltage between all connecting endpoints of the device to be tested is measured, whether the device to be tested is a three-pin device is judged according to the measurement result, if yes, the step S3 is executed, and if not, the step S4 is executed;
Step S3: the states of the first relay to the fifth relay are adjusted for the second time, and reverse recovery time parameter test is conducted;
step S4: thirdly, adjusting the states of the first relay to the fifth relay, measuring the voltage between each connecting endpoint of the device to be tested, judging whether the device to be tested is a two-pin device according to the measurement result, if so, executing the step S5, and if not, ending the test;
step S5: and fourthly, adjusting the states of the first relay to the fifth relay, performing reverse recovery time parameter test, and ending the test.
Optionally, when the device to be tested is a triode, the first connection endpoint is connected with a drain electrode of the triode, the second connection endpoint is connected with a gate electrode of the triode, and the third connection endpoint is connected with a source electrode of the triode;
when the device to be tested is a diode, the first connection terminal is connected with the cathode of the diode, and the second connection terminal is connected with the anode of the diode.
Optionally, step 2 includes:
releasing the first relay, the second relay and the fifth relay, closing the third relay and the fourth relay, and simultaneously releasing the second switching device;
Setting the output current of the constant current source for the first time, sampling the actually measured threshold voltage of the device to be tested through the operational amplifier circuit and the acquisition unit, judging whether the threshold voltage is in a set range, judging whether the device to be tested is a three-leg device which is correctly installed and is not damaged, if so, executing the step S3, and if not, executing the step S4.
Optionally, step 3 includes:
closing the first relay, the second relay, the third relay and the fifth relay, and releasing the fourth relay;
and performing reverse recovery time parameter test, sampling and outputting a test result of the switching time parameter and the threshold voltage of the three-pin device.
Optionally, step 4 includes:
releasing the first relay, the third relay and the fifth relay, simultaneously releasing the second switching device, and closing the second relay and the fourth relay;
setting the output current of the constant current source for the second time, sampling the forward voltage drop of the actually measured diode of the device to be tested through the operational amplifier circuit and the acquisition unit, and judging whether the forward voltage drop of the diode is in a set range, thereby judging whether the device to be tested is a two-pin device which is correctly installed and has no damage;
If yes, executing step S5;
if not, ending the test, releasing the second switching device, the first relay and the fifth relay, and setting the first power supply, the second power supply and the third power supply to 0V.
Optionally, step S5 includes:
closing the first relay, the second relay and the fifth relay, and releasing the third relay and the fourth relay;
and performing reverse recovery time parameter test, sampling and outputting a test result of the switch time parameter and forward conduction voltage drop of the two-pin device.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a testing device and a testing method for testing a two-pin device and a three-pin device, wherein the testing device comprises a grid driving circuit, a voltage providing circuit, a testing circuit, a device to be tested and a first switching device, wherein the testing circuit is provided with a first connecting endpoint, a second connecting endpoint and a third connecting endpoint; the grid driving circuit is connected with the grid of the first switching device, the positive electrode end of the voltage supply circuit is connected with the drain electrode of the first switching device, the source electrode of the first switching device is connected with the first connecting end point, the negative electrode of the voltage supply circuit and the second connecting end point are connected with the first node, the testing circuit collects voltages among all ports of the device to be tested from the first connecting end point, the second connecting end point and the third connecting end point, and collects current flowing through the device to be tested from the second connecting end point. The testing device can be used for compatibly measuring the two-pin device and the three-pin device without replacing the testing device when the device is replaced, so that the number of the testing devices is reduced, and the relevant investment of the devices is reduced.
Drawings
FIG. 1 is a circuit diagram of a testing apparatus for testing two-pin and three-pin devices according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of a test apparatus for mounting a three-pin device and determining whether the DUT is a three-pin device according to an embodiment of the present invention;
FIG. 3 is a timing chart corresponding to FIG. 2 according to an embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of a test apparatus according to an embodiment of the present invention when the device under test is a three-pin device and is measured;
FIG. 5 is a timing chart corresponding to FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a circuit equivalent diagram of a three-pin device according to an embodiment of the present invention when damaged and measured;
FIG. 7 is an equivalent circuit diagram of a test apparatus for mounting a two-pin device and determining whether the device under test is a three-pin device and measuring in accordance with an embodiment of the present invention;
FIG. 8 is a timing chart corresponding to FIG. 7 according to an embodiment of the present invention;
FIG. 9 is an equivalent circuit diagram of a test apparatus for mounting a two-pin device and determining whether the device under test is a two-pin device and measuring the same according to an embodiment of the present invention;
FIG. 10 is a timing chart corresponding to FIG. 9 according to an embodiment of the present invention;
FIG. 11 is an equivalent circuit diagram of a testing apparatus according to an embodiment of the present invention when the device under test is a two-pin device and is measured;
FIG. 12 is a timing chart corresponding to FIG. 11 according to an embodiment of the present invention;
FIG. 13 is an equivalent circuit diagram of a test apparatus for determining that a device under test is a three-pin device when the device under test is not a two-pin device or a three-pin device according to an embodiment of the present invention;
FIG. 14 is a timing diagram corresponding to FIG. 13 according to an embodiment of the present invention;
FIG. 15 is an equivalent circuit diagram of a test apparatus for determining that a device under test is a two-pin device when the device under test is not a two-pin device or a three-pin device according to an embodiment of the present invention;
FIG. 16 is a timing diagram corresponding to FIG. 15 according to an embodiment of the present invention;
fig. 17 is a flowchart of a testing method for testing two-pin and three-pin devices according to an embodiment of the present invention.
Detailed Description
A test apparatus and a test method for testing a two-pin device and a three-pin device according to the present invention will be described in further detail. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
Fig. 1 is a circuit diagram of a test apparatus for testing a two-pin device and a three-pin device according to the present embodiment. As shown in fig. 1, the test apparatus for testing two-pin devices and three-pin devices provided in this embodiment relates to the field of third-generation semiconductor material device test apparatuses, and meets JEDEC standards. Wherein the three-pin device can be an IGBT or a MOSFET, and the three-pin device is a device comprising a body diode.
The test apparatus comprises a gate drive circuit, a voltage supply circuit, a test circuit, a device under test DUT and a first switching device HDUT, the test circuit having three connection terminals 1, 2, 3 for connecting the device under test DUT. The first switching device HDUT and the second switching device S1 are IGBT devices, and the first switching device HDUT is a device without a body diode (such as IXGK75N250 device manufactured by IXYS corporation).
The grid driving circuit is connected with the grid of the first switching device HDUT, the positive electrode end of the voltage providing circuit is connected with the drain electrode of the first switching device HDUT, the source electrode of the first switching device HDUT is connected with the connecting terminal 1 of the DUT, the negative electrode of the voltage providing circuit and the connecting terminal 2 of the DUT are both connected with the node P, the testing circuit collects voltages among all ports of the DUT from the connecting terminals 1, 2 and 3, and the current flowing through the DUT from the connecting terminal 2.
When the DUT is a three-pin device, such as a triode, the connection terminal 1 is connected to the drain of the triode, the connection terminal 2 is connected to the gate of the triode, and the connection terminal 3 is connected to the source of the triode; when the DUT is a two-pin device, such as a diode, the connection terminal 1 is connected to the cathode of the diode, and the connection terminal 2 is connected to the anode of the diode.
The test circuit comprises a constant current source circuit, a first current sensor I_Sens1, a second current sensor I_Sens2, a third current sensor IDS, a power inductor L, a collecting unit 10, a first relay K1 and a fifth relay K5. The first relay K1, the third relay K3, the fourth relay K4 and the fifth relay K5 are single-knife single-set relays, and the second relay K2 is a double-knife double-set relay, so that the second relay K2 comprises a first knife 1, a second knife 2 and four ports A, B, C, D. The sampling unit 10 may be a high-speed high-precision voltage sampling measurement ADC or an oscilloscope measurement port OSC, and the sampling unit 10 is configured to collect current and voltage between connection terminals of the DUT.
The first knife 1 is connected with the constant current source circuit and the collecting unit 10, the second knife 2 is grounded to VCC_GND, the port A and the port D are both connected with one end of the third relay K3 and one end of the fourth relay K4 at the same time, the port B and the port C are connected with the connecting terminal 2 at the same time, the other end of the third relay K3 is connected with the connecting terminal 3, the other end of the fourth relay K4 and one end of the fifth relay K5 are both connected with the connecting terminal 1, the connecting terminal 1 is also connected with the collecting unit 10 and a source electrode of the first switching device HDUT so as to collect the voltage of the device DUT to be tested at the connecting terminal 1, the other end of the fifth relay K5 is connected with one end of the power inductor L, the other end of the power inductor L is connected with a node P through a second lead, the second lead is arranged in the second current sensor I_Sense2 in a penetrating manner, the connecting terminal 2 is connected with the third current sensor through a first lead, the connecting terminal 2 is connected with the first lead wire, and the first current sensor I is connected with the first current sensor output end of the first IDS 2.
The constant current source circuit comprises a constant current source IM, a high-voltage diode D1 and a first power supply VCC, the test circuit further comprises an operational amplifier circuit AMP, the operational amplifier circuit AMP comprises two input ends 1 and 2 and an output end 3, the first power supply VCC is used for providing a voltage value VCC, and the output current value of the constant current source IM is 0.1 mA-100 mA.
The output end 3 of the operational amplifier circuit AMP is simultaneously connected with the collecting unit 10 and the input end 2 of the operational amplifier circuit AMP, the input end 1 of the operational amplifier circuit AMP is simultaneously connected with the output end of the constant current source IM and the positive electrode of the high voltage diode D1, the input end of the constant current source IM is connected with the positive electrode of the first power supply VCC, the negative electrode of the first power supply VCC is grounded to vcc_gnd, and the negative electrode of the high voltage diode D1 is connected with the first knife 1.
The gate driving circuit comprises an operational amplifier 20, a first diode D2, a second diode D3, a first resistor r_p, a second resistor r_n, a driving signal source HVG, a second power source hvg+ and a third power source HVG-, wherein the operational amplifier 20 comprises an input end IN, an output end OUT, a positive power source end v+ and a negative power source end V-, the first resistor r_p and the second resistor r_n are adjustable gate driving resistor arrays, and the second power source hvg+ and the third power source HVG are adjustable low-voltage isolation driving power sources.
The input terminal IN of the operational amplifier 20 is connected with the driving signal source HVG, the positive power terminal V+ of the operational amplifier 20 is connected with the positive electrode of the second power source HVG+, the negative power terminal V-of the operational amplifier 20 is connected with the negative electrode of the third power source HVG-, the negative electrode of the second power source HVG+ and the positive electrode of the third power source HVG-are simultaneously grounded to HVG_GND, so that the second power source HVG+ provides a positive voltage VHVG+, the third power source HVG provides a negative voltage VHVG-, the output terminal OUT of the operational amplifier 20 is simultaneously connected with the positive electrode of the first diode D2 and the negative electrode of the second diode D3, the negative electrode of the first diode D2 is connected with one end of the first resistor R_P, the positive electrode of the second diode D3 is connected with one end of the second resistor R_N, and the other end of the first resistor R_N is simultaneously connected with the first switch device of the first gate.
The voltage supply circuit comprises a high-POWER programmable POWER supply HV_POWER, a first capacitor C1, a second capacitor C2 and a second switching device S1, wherein the drain electrode of the first switching device HDUT is simultaneously connected with one end of the capacitor C1 and the source electrode of the second switching device S1, the grid electrode of the second switching device S1 inputs a driving signal, the drain electrode of the second switching device S1 is simultaneously connected with one end of the capacitor C2 and one end of a first relay K1, the other end of the relay K1 is connected with the positive electrode of the high-POWER programmable POWER supply HV_POWER, and the negative electrode of the high-POWER programmable POWER supply HV_POWER, the other end of the capacitor C1 and the other end of the capacitor C2 are all connected with a node P.
As shown in fig. 17, the present embodiment further provides a testing method for testing a two-pin device and a three-pin device, including the steps of:
step S1: providing a testing device and a device under test DUT for testing two-pin devices and three-pin devices, and mounting the device under test DUT on the testing device through a connecting end point of the testing device;
step S2: the states of the first relay K1 to the fifth relay K5 are adjusted for the first time, the voltage between all connecting terminals of the DUT is measured, whether the DUT is a three-pin device is judged according to the measurement result, if yes, the step S3 is executed, and if not, the step S4 is executed;
step S3: adjusting the states of the first to fifth relays K1 to K5 for the second time, performing a TRR (reverse recovery time) parameter test, and ending the test;
step S4: thirdly, adjusting the states of the first relay K1 to the fifth relay K5, measuring the voltage between each connecting endpoint of the DUT, judging whether the DUT is a two-pin device according to the measurement result, if so, executing the step S5, otherwise, ending the test;
step S5: the states of the first to fifth relays K1 to K5 are adjusted a fourth time, and a TRR (reverse recovery time) parameter test is performed, followed by ending the test.
A test method for testing diodes and transistors according to this embodiment is described in detail below with reference to fig. 2-16.
Referring to fig. 1, step S1 is first performed, and a testing apparatus and DUT for testing two-pin devices and three-pin devices are provided, where the DUT is mounted on the testing apparatus through a connection terminal of the testing apparatus.
In detail, when the DUT is a three-pin device, such as a triode, the connection terminal 1 is connected to the drain of the triode, the connection terminal 2 is connected to the gate of the triode, and the connection terminal 3 is connected to the source of the triode; when the DUT is a two-pin device, such as a diode, the connection terminal 1 is connected to the cathode of the diode, and the connection terminal 2 is connected to the anode of the diode.
As shown in fig. 2-3, step S2 is performed, the states of the first to fifth relays K1 to K5 are adjusted for the first time, the voltages between the connection terminals of the DUT are measured, and whether the DUT is a tripod device is determined according to the measurement result, if yes, step S3 is performed, and if not, step S4 is performed.
The method specifically comprises the following steps:
firstly, the first relay K1, the second relay K2 and the fifth relay K5 are released, the third relay K3 and the fourth relay K4 are closed, meanwhile, the second switching device S1 is released, an equivalent circuit of the testing device is shown in fig. 2, and at this time, in a frame M1 of fig. 2, the first power source VCC, the constant current source IM, the high voltage diode D1, the operational amplifier circuit AMP and the device under test DUT form a threshold voltage Vth testing circuit. Since the first switching device HDUT is a device without a body diode (such as IXGK75N250 device manufactured by IXYS corporation), the constant current source IM cannot flow through the first switching device HDUT, and the first capacitor C1 and the second capacitor C2 have no influence on the measurement of the threshold voltage Vth.
Next, the user may set the output current of the constant current source IM, for example, 1mA, for the first time through the host computer, and sample the actually measured threshold voltage Vth (i.e., forward voltage VF) of the DUT through the op-AMP and the collection unit 10, and determine whether the threshold voltage Vth is within the set range. For example, when the DUT is a three-pin device and is short-circuited, the threshold voltage value is smaller than 0.5V, and when the DUT is open-circuited, the threshold voltage value is close to the power voltage value VCC of the constant current source IM; when the DUT is a two-pin device, the forward voltage VF samples a measured value close to the voltage VCC because the diode is in a reverse off state and the constant current source IM does not form a path. If the set voltage VCC is 15V and the set range of the threshold voltage Vth is 0.5V-10V, judging that the DUT is a three-pin device, and judging that the DUT is correctly installed and is not damaged; if yes, executing step S3, and if not, executing step S4.
As shown in fig. 4 to 6, step S3 is then performed to adjust the states of the first to fifth relays K1 to K5 for the second time, and a TRR (reverse recovery time) parameter test is performed, followed by ending the test.
The method specifically comprises the following steps:
firstly, the first relay K1, the second relay K2, the third relay K3 and the fifth relay K5 are closed, the fourth relay K4 is released, and at this time, an equivalent circuit of the testing device is shown in fig. 4, and because the output current of the constant current source IM cannot pass through the source and the gate of the device under test DUT and flow back to the ground vcc_gnd, a path cannot be formed, at this time, the source voltage of the device under test DUT is VCC, then the gate voltage of the device under test DUT takes a value of-VCC, and at the same time, the constant current source IM provides negative pressure to the device under test DUT, so as to avoid the floating gate of the device under test DUT and ensure that the device under test DUT is maintained in an off state. In this step, the user can set the voltage VCC through the upper computer according to the characteristics of the three-pin device.
Next, a TRR (reverse recovery time) parameter test is performed. In the test, the driving signal source HVG controls the first switching device HDUT to be turned on, the current is shown as II in fig. 4, the time sequence is shown as state II in fig. 5, and when the second current sensor i_sense_2 detects that the current of the third current sensor IDS reaches the set value Iset through the detection loop of the later stage, the driving signal source HVG controls the first switching device HDUT to be turned off and reach the state III, at this time, the current loop is shown as III in fig. 4, the time sequence is shown as state III in fig. 5, and at this time, the body diode of the device under test functions as a freewheeling diode of the DUT serving as a power inductor. In the state IV, the driving signal source HVG controls the first switching device HDUT to be turned on again, and the current loop at this time is referred to II of fig. 4.
Waveforms of the source-drain voltage VDS and the source-drain current IDS of the DUT to be tested are sampled by the sampling unit, and then processed by the upper computer to output test results of the switching time parameters, such as TDON, TR, TDOFF, TF, EON, EOFF, etc., which are not described herein. And the threshold voltage Vth of the three-pin device can be measured simultaneously.
In step S3, since the first current sensor i_sense_1 is connected in series with the source of the DUT, the purpose is to detect the current on the DUT in real time through a control loop.
During testing, the DUT is shorted out, at which time current flows in the direction as in fig. 6. At this time, the current does not pass through the power inductor L to limit the rising rate, the instantaneous short-circuit current overshoots are very large, the damage to the first switching device HDUT is easy to be caused, the short-circuit current cannot be detected by the second current sensor i_sensor_2, the current on the DUT is detected in real time through the first current sensor i_sensor_1, if abnormal, the first switching device HDUT and the second switching device S1 are rapidly turned off, and the relay K1 is released, so that the fault is avoided. At this time, the high voltage diode D1 can ensure the direction of the constant current source current and prevent the high voltage from entering and damaging the subsequent circuit.
Then, the test is ended.
And then executing step S4, regulating the states of the first relay K1 to the fifth relay K5 for the third time, measuring the voltage between each connecting end point of the DUT, judging whether the DUT is a two-pin device according to the measurement result, executing step S5 if yes, and ending the test if no.
The method specifically comprises the following steps:
through step 2, since it is determined that the DUT is not a three-pin device, and meanwhile, since the diode is in the reverse cut-off state and the constant current source IM does not form a channel, the measured value of the forward voltage VF approaches to the voltage VCC, so that the threshold voltage Vth does not satisfy the preset range, and therefore, the measurement is not performed according to the state configuration of the three-pin device, where the circuit is as shown in fig. 7, the timing sequence is as shown in fig. 8, and the forward voltage VF takes the value of VCC.
Therefore, first, the first, third and fifth relays K1, K3 and K5 are released, the second switching device S1 is released, the second and fourth relays K2 and K4 are closed, and an equivalent circuit of the test apparatus is shown in fig. 9. Since the cathode of the high voltage diode D1 is connected to the anode of the DUT, the cathode of the DUT is grounded vcc_gnd, and at this time, the circuit formed by the first power source VCC, the constant current source IM, the high voltage diode D1, the operational amplifier circuit AMP and the DUT is a measuring loop of the diode forward voltage drop VFSD, as shown in block M2 in fig. 9.
Then, the user can set the output current of the constant current source IM, for example, 1mA, for the second time through the upper computer, and sample the measured VFSD of the DUT through the op-AMP and the acquisition unit 10, and determine whether the VFSD is within the set range. For example, when the DUT is short-circuited, for example, when the DUT is a two-pin device, and the VFSD value is generally smaller than 0.5V, when the DUT is open, the VFSD value approaches to the power voltage value VCC of the constant current source IM, if the set voltage VCC is 15V, it can be determined that the sampled VF value is set in the range of 0.5V to 10V, and the DUT is a two-pin device, and at the same time, the DUT is correctly installed for the DUT without damage.
Then, when it is determined that the DUT is not a two-pin device, the circuit is shown in fig. 13 and 15, the timing chart corresponding to fig. 13 is shown in fig. 14, the timing chart corresponding to fig. 15 is shown in fig. 16, and when the measured values of the forward voltage VF are all out of the preset range, the test is ended, and the second switch device S1, the first relay K1 to the fifth relay K5 are all released, and the control circuit sets the first power VCC, the second power hvg+ and the third power HVG to 0V to avoid abnormal conditions.
Next, step S5 is performed, the states of the first to fifth relays K1 to K5 are adjusted for the fourth time, and a TRR (reverse recovery time) parameter test is performed, followed by ending the test.
The method specifically comprises the following steps:
first, the first, second and fifth relays K1, K2 and K5 are closed, and the third and fourth relays K3 and K4 are released, and at this time, the equivalent circuit of the testing device is shown in fig. 11.
Next, a TRR (reverse recovery time) parameter test is performed. In the test, the driving signal source HVG controls the first switching device HDUT to be turned on, the current is shown as II in fig. 11, the time sequence is shown as state II in fig. 12, and when the second current sensor i_sense_2 detects that the current of the third current sensor IDS reaches the set value Iset through the detection loop of the later stage, the driving signal source HVG controls the first switching device HDUT to be turned off to reach the state III, and at this time, the current loop is shown as III in fig. 11, the time sequence is shown as state III in fig. 12, and at this time, the body diode of the DUT to be tested functions as a freewheeling diode of the power inductor. In the state IV, the driving signal source HVG controls the first switching device HDUT to be turned on again, and the current loop at this time is referred to II of fig. 11.
Waveforms of the source-drain voltage VDS and the source-drain current IDS of the DUT to be tested are sampled by the sampling unit 10, and then processed by an upper computer to output test results of the switching time parameters, such as TDON, TR, TDOFF, TF, EON, EOFF, etc., which are not described herein. And the forward conduction voltage drop VFSD of the two-pin device can be measured simultaneously.
In the test process of step S5, since the first current sensor i_sense_1 detects the current on the DUT in real time through the control loop, if the current is abnormal, the first switching device HDUT and the second switching device S1 are turned off rapidly, and the relay K1 is released, so that the occurrence of a fault is avoided.
In summary, the present invention provides a testing apparatus and a testing method for testing a two-pin device and a three-pin device, wherein the testing apparatus includes a gate driving circuit, a voltage providing circuit, a testing circuit, a device under test and a first switching device, the testing circuit has a first connection terminal, a second connection terminal and a third connection terminal, the device under test is a two-pin device or a three-pin device, and the device under test is connected to the testing circuit through the first connection terminal, the second connection terminal and the third connection terminal; the grid driving circuit is connected with the grid of the first switching device, the positive electrode end of the voltage supply circuit is connected with the drain electrode of the first switching device, the source electrode of the first switching device is connected with the first connecting end point, the negative electrode of the voltage supply circuit and the second connecting end point are connected with the first node, the testing circuit collects voltages among all ports of the device to be tested from the first connecting end point, the second connecting end point and the third connecting end point, and collects current flowing through the device to be tested from the second connecting end point. The testing device can be used for compatibly measuring the two-pin device and the three-pin device without replacing the testing device when the device is replaced, so that the number of the testing devices is reduced, and the relevant investment of the devices is reduced.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (12)

1. The testing device for testing the two-pin device and the three-pin device is characterized by comprising a grid driving circuit, a voltage supply circuit, a testing circuit, a device to be tested and a first switching device, wherein the testing circuit is provided with a first connecting endpoint, a second connecting endpoint and a third connecting endpoint, the device to be tested is the two-pin device or the three-pin device, and the device to be tested is connected to the testing circuit through the first connecting endpoint, the second connecting endpoint and the third connecting endpoint;
The grid driving circuit is connected with the grid of the first switching device, the positive electrode end of the voltage supply circuit is connected with the drain electrode of the first switching device, the source electrode of the first switching device is connected with the first connecting end point, the negative electrode of the voltage supply circuit and the second connecting end point are connected with the first node, the testing circuit collects voltages among all ports of the device to be tested from the first connecting end point, the second connecting end point and the third connecting end point, and collects current flowing through the device to be tested from the second connecting end point.
2. The test apparatus for testing two-pin and three-pin devices according to claim 1, wherein,
when the device to be tested is a triode, the first connecting end point is connected with the drain electrode of the triode, the second connecting end point is connected with the grid electrode of the triode, and the third connecting end point is connected with the source electrode of the triode;
when the device to be tested is a diode, the first connection terminal is connected with the cathode of the diode, and the second connection terminal is connected with the anode of the diode.
3. The test apparatus for testing a two-pin device and a three-pin device according to claim 1, wherein the test circuit includes a constant current source circuit, a first current sensor, a second current sensor, a third current sensor, a power inductor, a collecting unit, a first relay to a fifth relay, each of the first relay, the third relay, the fourth relay, and the fifth relay being a single-blade single-position relay, the second relay being a double-blade double-position relay, such that the second relay includes a first blade, a second blade, and four ports,
The first knife is connected with the constant current source circuit and the acquisition unit, the second knife is grounded, the first port and the fourth port are both connected with one end of the third relay and one end of the fourth relay at the same time, the second port and the third port are both connected with the second connection endpoint, the other end of the third relay is connected with the third connection endpoint, the other end of the fourth relay and one end of the fifth relay are both connected with the first connection endpoint, the first connection endpoint is also connected with the acquisition unit and the source electrode of the first switching device, the other end of the fifth relay is connected with one end of the power inductor, the second connection endpoint is connected with the input end of the third current sensor through a first wire, the first wire is arranged in the first current sensor in a penetrating mode, the other end of the power inductor is connected with the first node through a second wire, the second wire is arranged in the second current sensor in a penetrating mode, the first output end of the third current sensor is connected with the first output end of the third current sensor, and the second output end of the third current sensor is connected with the first output unit.
4. The test apparatus for testing a two-pin device and a three-pin device according to claim 3, wherein the constant current source circuit comprises a constant current source, a high voltage diode, and a first power supply, the test circuit further comprises an operational amplifier circuit comprising two input terminals and an output terminal,
The output end of the operational amplifier circuit is simultaneously connected with the acquisition unit and the second input end of the operational amplifier circuit, the first input end of the operational amplifier circuit is simultaneously connected with the output end of the constant current source and the positive electrode of the high voltage diode, the input end of the constant current source is connected with the positive electrode of the first power supply, the negative electrode of the first power supply is grounded, and the negative electrode of the high voltage diode is connected with the first knife.
5. The test apparatus for testing a two-pin device and a three-pin device according to claim 3, wherein the gate driving circuit includes an operational amplifier, a first diode, a second diode, a first resistor, a second resistor, a driving signal source, a second power source, and a third power source, the operational amplifier includes an input terminal, an output terminal, a positive power source terminal, and a negative power source terminal,
the input end of the operational amplifier is connected with the driving signal source, the positive power end of the operational amplifier is connected with the positive electrode of the second power supply, the negative power end of the operational amplifier is connected with the negative electrode of the third power supply, the negative electrode of the second power supply and the positive electrode of the third power supply are simultaneously grounded, the output end of the operational amplifier is simultaneously connected with the positive electrode of the first diode and the negative electrode of the second diode, the negative electrode of the first diode is connected with one end of the first resistor, the positive electrode of the second diode is connected with one end of the second resistor, and the other end of the first resistor and the other end of the resistor are simultaneously connected with the grid electrode of the first switching device.
6. The test apparatus for testing a two-pin device and a three-pin device according to claim 3, wherein the voltage supply circuit comprises a high-power programmable power supply, a first capacitor, a second capacitor, and a second switching device,
the drain electrode of the first switching device is simultaneously connected with one end of the capacitor and the source electrode of the second switching device, the grid electrode of the second switching device inputs a driving signal, the drain electrode of the second switching device is simultaneously connected with one end of the capacitor and one end of the first relay, the other end of the relay is connected with the positive electrode of the high-power programmable power supply, and the negative electrode of the high-power programmable power supply, the other end of the capacitor and the other end of the capacitor are all connected with a first node.
7. A test method for testing a two-pin device and a three-pin device, comprising the steps of:
step S1: providing a test apparatus and a device under test for testing two-pin and three-pin devices as claimed in claim 4, mounting the device under test on the test apparatus through a connection terminal of the test apparatus;
step S2: the states of the first relay to the fifth relay are adjusted for the first time, the voltage between all connecting endpoints of the device to be tested is measured, whether the device to be tested is a three-pin device is judged according to the measurement result, if yes, the step S3 is executed, and if not, the step S4 is executed;
Step S3: the states of the first relay to the fifth relay are adjusted for the second time, reverse recovery time parameter test is conducted, and then the test is finished;
step S4: thirdly, adjusting the states of the first relay to the fifth relay, measuring the voltage between each connecting endpoint of the device to be tested, judging whether the device to be tested is a two-pin device according to the measurement result, if so, executing the step S5, and if not, ending the test;
step S5: and fourthly, adjusting the states of the first relay to the fifth relay, performing reverse recovery time parameter test, and ending the test.
8. A test method for testing a two-pin device and a three-pin device as defined in claim 7,
when the device to be tested is a triode, the first connecting end point is connected with the drain electrode of the triode, the second connecting end point is connected with the grid electrode of the triode, and the third connecting end point is connected with the source electrode of the triode;
when the device to be tested is a diode, the first connection terminal is connected with the cathode of the diode, and the second connection terminal is connected with the anode of the diode.
9. The method of testing a two-pin device and a three-pin device according to claim 7, wherein step 2 comprises:
Releasing the first relay, the second relay and the fifth relay, closing the third relay and the fourth relay, and simultaneously releasing the second switching device;
setting the output current of the constant current source for the first time, sampling the actually measured threshold voltage of the device to be tested through the operational amplifier circuit and the acquisition unit, judging whether the threshold voltage is in a set range, judging whether the device to be tested is a three-leg device which is correctly installed and is not damaged, if so, executing the step S3, and if not, executing the step S4.
10. The method for testing two-pin and three-pin devices according to claim 7, wherein step 3 comprises:
closing the first relay, the second relay, the third relay and the fifth relay, and releasing the fourth relay;
and performing reverse recovery time parameter test, sampling and outputting a test result of the switching time parameter and the threshold voltage of the three-pin device.
11. The method of testing a two-pin device and a three-pin device according to claim 7, wherein step 4 comprises:
releasing the first relay, the third relay and the fifth relay, simultaneously releasing the second switching device, and closing the second relay and the fourth relay;
Setting the output current of the constant current source for the second time, sampling the forward voltage drop of the actually measured diode of the device to be tested through the operational amplifier circuit and the acquisition unit, and judging whether the forward voltage drop of the diode is in a set range, thereby judging whether the device to be tested is a two-pin device which is correctly installed and has no damage;
if yes, executing step S5;
if not, ending the test, releasing the second switching device, the first relay and the fifth relay, and setting the first power supply, the second power supply and the third power supply to 0V.
12. The method for testing two-pin and three-pin devices according to claim 7, wherein step S5 comprises:
closing the first relay, the second relay and the fifth relay, and releasing the third relay and the fourth relay;
and performing reverse recovery time parameter test, sampling and outputting a test result of the switch time parameter and forward conduction voltage drop of the two-pin device.
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CN115840123A (en) * 2023-03-01 2023-03-24 佛山市联动科技股份有限公司 Transistor parameter testing device and testing method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670709A (en) * 1984-03-30 1987-06-02 John Iredale Portable audio system and audio cable continuity tester
CN101639514A (en) * 2009-08-24 2010-02-03 天津华云自控股份有限公司 Detecting device for detecting IGBT
CN207007962U (en) * 2017-07-11 2018-02-13 Tcl空调器(中山)有限公司 The performance test circuit and device of a kind of photoelectrical coupler
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