CN116626462A - Dynamic characteristic testing device and method for power device - Google Patents
Dynamic characteristic testing device and method for power device Download PDFInfo
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- CN116626462A CN116626462A CN202310475257.1A CN202310475257A CN116626462A CN 116626462 A CN116626462 A CN 116626462A CN 202310475257 A CN202310475257 A CN 202310475257A CN 116626462 A CN116626462 A CN 116626462A
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- 238000010998 test method Methods 0.000 claims description 4
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/60—Other road transportation technologies with climate change mitigation effect
- Y02T10/70—Energy storage systems for electromobility, e.g. batteries
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Abstract
The invention relates to the technical field of power electronics, and discloses a dynamic characteristic testing device and method for a power device.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a dynamic characteristic testing device and method of a power device.
Background
The switch time tester and the reverse recovery time tester on the market at present are two independent measurement systems, and when a customer needs to test two parameters at the same time, the two parameters need to be carried out at separate stations, the test time is long, and the equipment investment is large. In addition, when the rising and falling time of a tested power device in a switch time test or the DIDT parameter condition in a reverse recovery time test is adjusted, the current technology is generally realized by manually welding to replace an external grid series resistor or using a potentiometer, the debugging stage in the early stage of new product introduction is troublesome, the manual welding resistor is not easy to replace and debug, and the tester and the device are easy to damage; the potentiometer is easy to change value for a long time, and the potentiometer is large in temperature drift, so that inaccurate measurement is easy to cause. In a more frequent application environment where customers need to replace mass-produced products for testing, the current approach is very inconvenient.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect that a device cannot be used for testing the switching time and the reverse recovery time of a power device in the prior art, so as to provide a device and a method for testing the dynamic characteristics of the power device.
In order to achieve the above purpose, the present invention provides the following technical solutions:
in a first aspect, an embodiment of the present invention provides a dynamic characteristic testing apparatus for a power device, including: the power device comprises a first switch circuit, a second switch circuit, a power inductor, an adjustable grid driving resistor array and an operational amplifier circuit, wherein the control end of the first power device is connected with the first end of the second switch circuit, the first end of the first power device is connected with the first end of the first switch circuit, the second end of the first power device is connected with the second end of the first switch circuit through the power inductor, and the second end of the first power device is also connected with the second end of the second switch circuit; the control end of the second power device is connected with the third end of the second switch short circuit, the first end of the second power device is connected with the second end of the first power device, the second end of the second power device is connected with the first grounding end and the third end of the first switch circuit, and the second end of the second power device is also connected with the fourth end of the second switch short circuit; the first switch circuit is connected with an external power supply; the fifth end of the second switch circuit is connected with the first end of the adjustable grid driving resistor array, the sixth end of the second switch circuit is connected with the first driving power supply, the seventh end of the second switch circuit is connected with the second grounding end, and the eighth end of the second switch circuit is connected with the third grounding end; the second end of the adjustable grid driving resistor array is connected with a driving signal through an operational amplifier circuit; the positive electrode power supply end of the operational amplifier circuit is connected with the second driving power supply, and the negative electrode power supply end of the operational amplifier circuit is connected with the third driving power supply; the first driving power supply is connected with the third grounding end at the grounding end; the grounding end of the second driving power supply is connected with the second grounding end; the grounding end of the third driving power supply is connected with the second grounding end; when the switching time test is carried out on the second power device, the second end of the first power device is connected with the first end of the first power device through a power inductor by controlling the on-off state of the first switching circuit; the control end of the first power device is connected with a first driving power supply, the second end of the first power device is connected with a third grounding end, the control end of the second power device is connected with the first end of the adjustable grid driving resistor array, and the second end of the second power device is connected with the second grounding end; when the reverse recovery time test is carried out on the second power device, the second end of the first power device is connected with the second end of the first power device through a power inductor by controlling the on-off state of the first switch circuit; the control end of the first power device is connected with the first end of the adjustable grid driving resistor array, the second end of the first power device is connected with the second grounding end, the control end of the second power device is connected with the first driving power supply, and the second end of the second power device is connected with the third grounding end by controlling the on-off state of the second switching circuit.
In one embodiment, the first switching circuit includes: the first single-pole single-placed relay and the second single-pole single-placed relay, wherein the first end of the first single-pole single-placed relay is connected with the first end of the first power device, and the second end of the first single-pole single-placed relay is connected with the second end of the first power device through a power inductor; the first end of the second single-pole single-placed relay is connected with the second end of the first single-pole single-placed relay, and the second end of the second single-pole single-placed relay is connected with the second end of the second power device; the first single-pole single-placed relay is connected with the second single-pole single-placed relay in series and then connected with an external power supply; when the switching time of the second power device is tested, the first single-pole single-set relay is controlled to be closed, and the second single-pole single-set relay is controlled to be opened; and when the reverse recovery time test is carried out on the second power device, the first single-pole single-placed relay is controlled to be opened, and the second single-pole single-placed relay is controlled to be closed.
In one embodiment, the second switching circuit includes: the first double-knife double-placed relay is connected with the control end of the first power device, the second end of the first double-knife double-placed relay is connected with the second end of the first power device, the third end of the first double-knife double-placed relay is connected with the first end of the adjustable grid driving resistor array, the fourth end of the first double-knife double-placed relay is connected with the first driving power supply, the fifth end of the first double-knife double-placed relay is connected with the second grounding end, and the sixth end of the first double-knife double-placed relay is connected with the third grounding end; the first end of the second double-pole double-placed relay is connected with the control end of the second power device, the second end of the second double-pole double-placed relay is connected with the second end of the second power device, the third end of the second double-pole double-placed relay is connected with the first end of the adjustable grid driving resistor array, the fourth end of the second double-pole double-placed relay is connected with the first driving power supply, the fifth end of the second double-pole double-placed relay is connected with the second grounding end, and the sixth end of the sixth double-pole double-placed relay is connected with the third grounding end; when the switching time test is carried out on the second power device, the first end of the first double-knife double-placed relay is controlled to be connected with the fourth end of the first double-knife double-placed relay, the second end of the first double-knife double-placed relay is controlled to be connected with the sixth end of the first double-knife double-placed relay, the first end of the second double-knife double-placed relay is controlled to be connected with the third end of the second double-knife double-placed relay, and the second end of the second double-knife double-placed relay is controlled to be connected with the fifth end of the second double-knife double-placed relay; when the reverse recovery time test is carried out on the second power device, the first end of the first double-knife double-placed relay is controlled to be connected with the third end of the first double-knife double-placed relay, the second end of the first double-knife double-placed relay is controlled to be connected with the fifth end of the first double-knife double-placed relay, the first end of the second double-knife double-placed relay is controlled to be connected with the fourth end of the second double-knife double-placed relay, and the second end of the second double-knife double-placed relay is controlled to be connected with the sixth end of the second double-knife double-placed relay.
In one embodiment, an adjustable gate drive resistor array includes: the first resistor array branch circuit and the second resistor array branch circuit are connected in anti-parallel.
In one embodiment, the first resistive array branch includes: the device comprises a first diode, a plurality of first resistors and a plurality of first controllable switches, wherein each first resistor is connected with one first controllable switch in parallel; the first ends of all the first resistors are connected in series and connected with the cathode of the first diode, and the second ends of all the first resistors are connected in series and connected with the second ends of the adjustable grid driving resistor array; the anode of the first diode is connected with a driving signal through an operational amplifier circuit.
In one embodiment, the second resistive array branch includes: the second diode, a plurality of second resistors and a plurality of second controllable switches, wherein each second resistor is connected with one second controllable switch in parallel; the first ends of all the second resistors are connected in series and then connected with the cathodes of the second diodes, and the second ends of all the second resistors are connected in series and then connected with the second ends of the adjustable grid driving resistor array; the anode of the second diode is connected with a driving signal through an operational amplifier circuit.
In an embodiment, the dynamic characteristic test device of a power device further includes: and the power supply module is connected with the first switch circuit in parallel and is used for providing a test power supply.
In one embodiment, a power module includes: the first capacitor, the second capacitor, the controllable switch and the programmable power supply, wherein the first end of the first capacitor is connected with the first end of the first power device, and the second end of the first capacitor is connected with the second end of the second power device; the first end of the second capacitor is connected with the first end of the first capacitor through a controllable switch, and the second end of the second capacitor is connected with the second end of the second power device; a programmable power supply connected in parallel with the second capacitor; and when the switching time test and the reverse recovery time are carried out on the second power device, controlling the controllable switch to be closed.
In a second aspect, an embodiment of the present invention provides a method for testing dynamic characteristics of a power device, including: when the switching time test is carried out on the second power device, the second end of the first power device is connected with the first end of the first power device through a power inductor by controlling the on-off state of the first switching circuit; the control end of the first power device is connected with a first driving power supply, the second end of the first power device is connected with a third grounding end, the control end of the second power device is connected with the first end of the adjustable grid driving resistor array, and the second end of the second power device is connected with the second grounding end; when the reverse recovery time test is carried out on the second power device, the second end of the first power device is connected with the second end of the first power device through a power inductor by controlling the on-off state of the first switch circuit; the control end of the first power device is connected with the first end of the adjustable grid driving resistor array, the second end of the first power device is connected with the second grounding end, the control end of the second power device is connected with the first driving power supply, and the second end of the second power device is connected with the third grounding end by controlling the on-off state of the second switching circuit.
In an embodiment, the switching time test process is performed on the second power device, and further includes: controlling the first power device to be turned off and the second power device to be turned on; when the current of the power inductor reaches a first preset value, the second power device is controlled to be turned off; and after the first preset time, controlling the second power device to be conducted.
In an embodiment, performing a reverse recovery time test procedure on the second power device further includes: controlling the first power device to be turned off and the second power device to be turned on; after a second preset time, controlling the first power device to be turned on and the second power device to be turned off; when the current of the power inductor reaches a second preset value, the first power device is controlled to be turned off; and after the third preset time, controlling the first power device to be conducted.
The technical scheme of the invention has the following advantages:
the dynamic characteristic testing device and the method for the power device provided by the invention realize the switching time test and the reverse recovery time test in a grid drive multiplexing mode, thereby realizing the reduction of equipment cost, the reduction of debugging time in the initial stage of DUT test and the reduction of overall test time, accelerating the test time of mass production products and reducing the test cost, and paving a road for popularization and application.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram showing a specific example of a test apparatus according to an embodiment of the present invention;
FIG. 2 is a circuit configuration diagram of a test device according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an adjustable gate drive resistor array according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an open circuit of an adjustable gate drive resistor array according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a turn-off circuit of an adjustable gate drive resistor array according to an embodiment of the present invention;
FIG. 6 is a simplified diagram of a switching time measurement loop according to an embodiment of the present invention;
FIG. 7 is a timing chart of the switch time measurement according to an embodiment of the present invention;
FIGS. 8 and 9 are diagrams illustrating the current direction during the switching time measurement according to embodiments of the present invention;
FIG. 10 is a simplified diagram of a reverse recovery time measurement loop according to an embodiment of the present invention;
FIG. 11 is a timing diagram of reverse recovery time measurement according to an embodiment of the present invention;
fig. 12 and 13 are both the current directions in the reverse recovery time measurement process according to the embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
An embodiment of the present invention provides a dynamic characteristic testing device for a power device, as shown in fig. 1, including: the circuit comprises a first switch circuit 1, a second switch circuit 2, a power inductor L, an adjustable grid driving resistor array 3 and an operational amplifier circuit 4.
As shown in fig. 1, the control terminal of the first power device HDUT is connected to the first terminal of the second switch circuit 2, the first terminal thereof is connected to the first terminal of the first switch circuit 1, the second terminal thereof is connected to the second terminal of the first switch circuit 1 through the power inductor L, and the second terminal thereof is also connected to the second terminal of the second switch circuit 2.
As shown in fig. 1, the control terminal of the second power device DUT is connected to the third terminal of the second switch, the first terminal is connected to the second terminal of the first power device HDUT, the second terminal is connected to the first ground terminal p_gnd, the third terminal of the first switch circuit 1, and the second terminal is also connected to the fourth terminal of the second switch.
Specifically, the first power device HDUT and the second power device DUT may be the power devices under test, but in each test, only one of the power devices can be subjected to a switching time test and a reverse recovery time test.
As shown in fig. 1, a first switch circuit 1 connected to an external power supply; the external power supply is a controllable power supply, namely, the parameters such as amplitude, switching time and the like are controllable.
As shown in fig. 1, the fifth end of the second switch circuit 2 is connected to the first end of the adjustable gate driving resistor array 3, the sixth end is connected to the first driving power VEE, the seventh end is connected to the second ground terminal vg_gnd, and the eighth end is connected to the third ground terminal GND.
Specifically, the second switching circuit 2 may be a switching channel gating circuit, i.e. the on-off state of each branch in the second switching circuit 2, and may determine whether the control end of the first power device HDUT and the control end of the second power device DUT are connected to the first driving power supply VEE or the adjustable gate driving resistor array 3, and determine whether the second end of the first power device HDUT and the second end of the second power device DUT are connected to the second ground terminal vg_gnd or the third ground terminal GND, so as to form a switching time test loop and a reverse recovery time test loop.
As shown in fig. 1, the second end of the adjustable gate driving resistor array 3 is connected to a driving signal through an operational amplifier circuit 4, wherein the driving signal is output by a driving signal source VG, and the driving signal is used for driving the first power device HDUT and the second power device DUT to be turned on or off.
As shown in fig. 1, the operational amplifier circuit 4 has a positive power supply terminal connected to the second driving power supply vg+ and a negative power supply terminal connected to the third driving power supply VG-.
In the embodiment of the present invention, the ground terminal of the first driving power VEE is connected to the third ground terminal GND; the ground terminal of the second driving power supply VG+ is connected with the second ground terminal VG_GND; the ground terminal of the third driving power source VG-is connected with the second ground terminal VG_GND, namely, the first driving power source VEE and the second driving power source VG+ and the third driving power source VG-are not commonly grounded, and the second driving power source VG+ and the third driving power source VG-are commonly grounded.
Specifically, when the switching time test is performed on the second power device DUT, the second end of the first power device HDUT is connected to the first end thereof through the power inductor L by controlling the on-off state of the first switching circuit 1; by controlling the on-off state of the second switch circuit 2, the control end of the first power device HDUT is connected with the first driving power supply VEE, the second end of the first power device HDUT is connected with the third ground end GND, the control end of the second power device DUT is connected with the first end of the adjustable gate driving resistor array 3, and the second end of the second power device DUT is connected with the second ground end vg_gnd.
Specifically, when the reverse recovery time test is performed on the second power device DUT, the second end of the first power device HDUT is connected with the second end of the first power device HDUT through the power inductor L by controlling the on-off state of the first switch circuit 1; by controlling the on-off state of the second switch circuit 2, the control end of the first power device HDUT is connected to the first end of the adjustable gate driving resistor array 3, the second end of the first power device HDUT is connected to the second ground terminal vg_gnd, and the control end of the second power device DUT is connected to the first driving power supply VEE, and the second end of the second power device DUT is connected to the third ground terminal GND.
The above control methods for the first switch circuit 1 and the second switch circuit 2 are both methods for performing dynamic characteristic test on the second power device DUT, and when performing dynamic test on the first power device HDUT, the control methods for the first switch circuit 1 and the second switch may be adaptively modified by referring to the above methods.
In one embodiment, as shown in fig. 2, the first switch circuit 1 includes: the first single-pole relay K1 and the second single-pole relay K2.
As shown in fig. 2, a first single-pole single-set relay K1 has a first end connected to a first end of the first power device HDUT and a second end connected to a second end of the first power device HDUT through a power inductor L; the first end of the second single-pole single-placed relay K2 is connected with the second end of the first single-pole single-placed relay K1, and the second end of the second single-pole single-placed relay K2 is connected with the second end of the second power device DUT; the first single-pole single-placed relay K1 and the second single-pole single-placed relay K2 are connected in series and then connected with an external power supply.
Specifically, when the switching time test is performed on the second power device DUT, the first single-pole single-set relay K1 is controlled to be closed, and the second single-pole single-set relay K2 is controlled to be opened; when the reverse recovery time test is carried out on the second power device DUT, the first single-pole single-set relay K1 is controlled to be opened, and the second single-pole single-set relay K2 is controlled to be closed.
In one embodiment, as shown in fig. 2, the second switch circuit 2 includes: the first double-knife double-placed relay K3 and the second double-knife double-placed relay K4.
As shown in fig. 2, the first dual knife dual relay K3 has a first end connected to the control end of the first power device HDUT, a second end connected to the second end of the first power device HDUT, a third end connected to the first end of the adjustable gate driving resistor array 3, a fourth end connected to the first driving power VEE, a fifth end connected to the second ground terminal vg_gnd, and a sixth end connected to the third ground terminal GND.
As shown in fig. 2, the first end of the second double-pole relay K4 is connected to the control end of the second power device DUT, the second end is connected to the second end of the second power device DUT, the third end is connected to the first end of the adjustable gate driving resistor array 3, the fourth end is connected to the first driving power VEE, the fifth end is connected to the second ground terminal vg_gnd, and the sixth end is connected to the third ground terminal GND.
Specifically, when the switching time test is performed on the second power device DUT, the first end of the first double-knife double-placed relay K3 is controlled to be connected with the fourth end thereof, the second end of the first double-knife double-placed relay K3 is controlled to be connected with the sixth end thereof, the first end of the second double-knife double-placed relay K4 is controlled to be connected with the third end thereof, and the second end of the second double-knife double-placed relay K4 is controlled to be connected with the fifth end thereof.
Specifically, when the reverse recovery time test is performed on the second power device DUT, the first end of the first double-knife double-placed relay K3 is controlled to be connected with the third end thereof, the second end of the first double-knife double-placed relay K3 is controlled to be connected with the fifth end thereof, the first end of the second double-knife double-placed relay K4 is controlled to be connected with the fourth end thereof, and the second end of the second double-knife double-placed relay K4 is controlled to be connected with the sixth end thereof.
In a specific embodiment, the dynamic characteristic testing device of the power device further includes: a power supply module connected in parallel with the first switching circuit 1 for supplying a test power.
Optionally, as shown in fig. 2, the power module includes: the POWER supply comprises a first capacitor C1, a second capacitor C2, a third controllable switch S1 and a programmable POWER supply HV_POWER, wherein a first end of the first capacitor C1 is connected with a first end of a first POWER device HDUT, and a second end of the first capacitor C1 is connected with a second end of a second POWER device DUT; a first end of the second capacitor C2 is connected with the first end of the first capacitor C1 through a third controllable switch S1, and a second end of the second capacitor C2 is connected with a second end of the second power device DUT; a programmable POWER supply HV_POWER connected in parallel with the second capacitor C2; and when the switching time test and the reverse recovery time are carried out on the second power device DUT, the third controllable switch S1 is controlled to be closed.
Referring to fig. 2, when testing the switching time parameter of the second power device DUT, the first single-pole single-relay K1 is closed, the second single-pole single-relay K2 is released, the first double-pole double-relay K3 and the second double-pole double-relay K4 are controlled by the same control signal, and the topology state is: the G, S pole of the first power device HDUT is respectively connected to GND and VEE of the first driving power supply VEE, and the first power device HDUT is in a grid negative pressure off-state at the moment; the G, S pole of the second power device DUT is connected to GF/GS terminal and VG_GND terminal, respectively, of the adjustable gate drive resistor array 3, and the drive signal source VG can control the on and off of the second power device DUT.
In one embodiment, the adjustable gate drive resistor array 3 includes: the first resistor array branch circuit and the second resistor array branch circuit are connected in anti-parallel.
Optionally, as shown in fig. 3, the first resistor array branch includes: the device comprises a first diode D1, a plurality of first resistors (PR 1-PR 8) and a plurality of first controllable switches (K_PR 1-K_PR 8), wherein each first resistor is connected with a second controllable switch in parallel; the first ends of all the first resistors are connected in series and connected with the cathode of the first diode, and the second ends of all the first resistors are connected in series and connected with the second ends of the adjustable grid driving resistor array 3; the anode of the first diode is connected to the driving signal through the operational amplifier circuit 4.
Optionally, as shown in fig. 3, the second resistor array branch includes: a second diode D2, a plurality of second resistors (NR 1-NR 8) and a plurality of second controllable switches (K_NR1-K_NR8), wherein each second resistor is connected with one second controllable switch in parallel; the first ends of all the second resistors connected in series are connected with the cathodes of the second diodes, and the second ends of all the second resistors connected in series are connected with the second ends of the adjustable grid driving resistor array 3; the anode of the second diode is connected to the driving signal through the operational amplifier circuit 4.
Referring to fig. 3, PR1 to PR8, k_pr1 to k_pr8; NR 1-NR 8, K_NR1-K_NR8 are respectively an adjustable grid driving resistor array 3 formed by relays and resistors, the resistance values of the resistors are selected according to the coding mode of 1248 codes, namely 1 omega, 2 omega, 4 omega … … omega, and 8 open loops and 8 shut loops are respectively arranged, so that R_P and R_N are respectively continuously adjustable in the range of 0 omega-255 omega, and the stepping amount is 1 omega.
In fig. 3, the on loop and the off loop are distinguished by the forward conduction principle of the diode, when the driving signal source VG controls the driving chip to output the DUT on signal, the driving chip outputs vg+ level at positive voltage, and the direction of the driving loop current IG is shown in fig. 4. When the driving signal source VG controls the driving chip to output the DUT turn-off signal, the driving chip outputs VG-level at this time, which is negative, and the direction of the driving loop current IG at this time is as shown in fig. 5.
The embodiment of the invention provides a dynamic characteristic test method of a power device, which comprises the following steps:
(1) When the switching time test is carried out on the second power device, the second end of the first power device is connected with the first end of the first power device through a power inductor by controlling the on-off state of the first switching circuit; the control end of the first power device is connected with a first driving power supply, the second end of the first power device is connected with a third grounding end, the control end of the second power device is connected with the first end of the adjustable grid driving resistor array, and the second end of the second power device is connected with the second grounding end;
(2) When the reverse recovery time test is carried out on the second power device, the second end of the first power device is connected with the second end of the first power device through a power inductor by controlling the on-off state of the first switch circuit; the control end of the first power device is connected with the first end of the adjustable grid driving resistor array, the second end of the first power device is connected with the second grounding end, the control end of the second power device is connected with the first driving power supply, and the second end of the second power device is connected with the third grounding end by controlling the on-off state of the second switching circuit.
In a specific embodiment, the switching time test process is performed on the second power device, and the method further includes:
controlling the first power device to be turned off and the second power device to be turned on; when the current of the power inductor reaches a first preset value, the second power device is controlled to be turned off; and after the first preset time, controlling the second power device to be conducted.
The switching time measuring loop is shown in fig. 6, and the programmable POWER supply hv_power and the high-voltage capacitor groups (C1, C2) are used for providing VDS voltage to the second POWER device DUT; the power inductor L is used as a series inductance load of the DUT and is used for slowing down the rising speed of IDS current; an adjustable gate drive resistor array (R_P, R_N) controls the speed of turning on and off the DUT; the I_sense current sensor is used for detecting the real-time value of IDS; at this time, the first power device HDUT is in an off state, and the body diode thereof functions as a freewheeling diode of the power inductor; VGS, VDS, IDS, respectively connected with oscilloside measuring channels, and used for measuring corresponding switching time waveforms.
A measurement timing diagram of the switching time test is shown in fig. 7. In fig. 7, in state II, the driving signal source VG controls the second power device DUT to be turned on, and the large current loop flows in the dashed line in fig. 8, so that the power inductor has a slow current rising speed.
In fig. 7, when the i_sense current sensor detects that the IDS current reaches the set value Iset through the detection loop of the subsequent stage, the driving signal source VG controls the second power device DUT to turn off to the state III, and the current loop is as shown in fig. 9. The body diode of the first power device HDUT functions as a freewheeling diode as a power inductor.
In fig. 7, VG controls the DUT to enter the conductive state again in state IV, with reference to fig. 8 for the current loop. Waveforms of VGS, VDS and IDS are sampled by an oscilloscope, and then processed by an upper computer to output test results of switching time parameters, such as TDON, TR, TDOFF, TF, EON, EOFF, which are not described herein.
In a specific embodiment, the reverse recovery time test process for the second power device further includes:
(1) Controlling the first power device to be turned off and the second power device to be turned on;
(2) After a second preset time, controlling the first power device to be turned on and the second power device to be turned off;
(3) When the current of the power inductor reaches a second preset value, the first power device is controlled to be turned off;
(4) And after the third preset time, controlling the first power device to be conducted.
When the reverse recovery time is tested, the first single-knife single-set relay K1 is released, the second single-knife single-set relay K2 is closed, the first double-knife double-set relay K3 and the second double-knife double-set relay K4 are controlled by the same control signal, and the state is that: the G, S pole of the first power device HDUT is respectively connected to the GF/GS end and VG_GND of the adjustable grid driving resistor array, and at the moment, a driving signal source VG driving signal can control the on and off of the first power device HDUT; the G, S pole of the second power device DUT is respectively connected to GND and VEE of the first driving power supply VEE, and the second power device DUT is in a grid negative pressure off state.
The reverse recovery time measurement loop is simplified as shown in fig. 10. The programmable POWER supply HV_POWER and the high-voltage POWER supply groups (C1, C2) are used for providing IDS current; the power inductor L is used as a series inductance load of a current loop to control the rising speed of IDS; an adjustable grid driving resistor array (R_P, R_N) is used for controlling the on and off speed of the first power device HDUT and controlling the di/dt current rising (speed) rate parameter during measurement; the I_sense current sensor is used for detecting the real-time value of IDS; at this time, the second power device DUT is in an off state, and the body diode of the second power device DUT acts as a freewheeling diode of the power inductor; VGS, VDS, IDS, respectively connected with oscilloside measuring channels, and used for measuring corresponding switching time waveforms.
The reverse recovery time measurement sequence is shown in fig. 11. In fig. 11, the driving signal source VG controls the first power device HDUT to be turned on, as in fig. 12. At this time, a large current loop flows in a dotted line, and the power inductance gradually increases the current linearly. Since the current loop did not pass through the IDS current sensor, the IDS waveform of the oscilloscope is 0 at this point.
Referring to fig. 11, when the i_sense current sensor detects that the current value reaches the set value IMax through the detection loop of the subsequent stage, the driving signal source VG controls the first power device HDUT to be turned off to reach the state III, and the current loop is as shown in fig. 13. The body diode of the second power device DUT functions as a freewheeling diode for the power inductance. And the reverse recovery time test is to test the reverse recovery time parameter of the second power device DUT body diode.
Referring to fig. 11, in state IV, the driving signal source VG controls the first power device HDUT to be turned on again, and the current loop at this time is referring to fig. 12. Waveforms of VGS, VDS and IDS are sampled by an oscilloscope, and then processed by an upper computer to output test results of switching time parameters, such as TDON, TR, TDOFF, TF, EON, EOFF, which are not described herein.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (11)
1. A dynamic characteristic test apparatus for a power device, comprising: a first switch circuit, a second switch circuit, a power inductor, an adjustable grid driving resistor array and an operational amplifier circuit, wherein,
the control end of the first power device is connected with the first end of the second switching circuit, the first end of the first power device is connected with the first end of the first switching circuit, the second end of the first power device is connected with the second end of the first switching circuit through the power inductor, and the second end of the first power device is also connected with the second end of the second switching circuit;
the control end of the second power device is connected with the third end of the second switch short circuit, the first end of the second power device is connected with the second end of the first power device, the second end of the second power device is connected with the first grounding end and the third end of the first switch circuit, and the second end of the second power device is also connected with the fourth end of the second switch short circuit;
the first switch circuit is connected with an external power supply;
the fifth end of the second switch circuit is connected with the first end of the adjustable grid driving resistor array, the sixth end of the second switch circuit is connected with the first driving power supply, the seventh end of the second switch circuit is connected with the second grounding end, and the eighth end of the second switch circuit is connected with the third grounding end;
the second end of the adjustable grid driving resistor array is connected with a driving signal through the operational amplifier circuit;
the positive electrode power supply end of the operational amplifier circuit is connected with the second driving power supply, and the negative electrode power supply end of the operational amplifier circuit is connected with the third driving power supply;
the grounding end of the first driving power supply is connected with the third grounding end; the grounding end of the second driving power supply is connected with the second grounding end; the grounding end of the third driving power supply is connected with the second grounding end;
when the switching time test is carried out on the second power device, the second end of the first power device is connected with the first end of the first power device through the power inductor by controlling the on-off state of the first switching circuit; the control end of the first power device is connected with the first driving power supply, the second end of the first power device is connected with the third grounding end, the control end of the second power device is connected with the first end of the adjustable grid driving resistor array, and the second end of the second power device is connected with the second grounding end;
when the reverse recovery time test is carried out on the second power device, the second end of the first power device is connected with the second end of the first power device through the power inductor by controlling the on-off state of the first switch circuit; the control end of the first power device is connected with the first end of the adjustable grid driving resistor array, the second end of the first power device is connected with the second grounding end, the control end of the second power device is connected with the first driving power supply, and the second end of the second power device is connected with the third grounding end by controlling the on-off state of the second switching circuit.
2. The dynamic characteristic test apparatus of a power device according to claim 1, wherein the first switching circuit includes: a first single-pole single-placed relay and a second single-pole single-placed relay, wherein,
the first end of the first single-pole single-placed relay is connected with the first end of the first power device, and the second end of the first single-pole single-placed relay is connected with the second end of the first power device through the power inductor;
the first end of the second single-pole single-placed relay is connected with the second end of the first single-pole single-placed relay, and the second end of the second single-pole single-placed relay is connected with the second end of the second power device;
the first single-pole single-placed relay is connected with the second single-pole single-placed relay in series and then connected with an external power supply;
when the switching time of the second power device is tested, the first single-pole single-set relay is controlled to be closed, and the second single-pole single-set relay is controlled to be opened;
and when the reverse recovery time test is carried out on the second power device, the first single-pole single-set relay is controlled to be opened, and the second single-pole single-set relay is controlled to be closed.
3. The dynamic characteristic test apparatus of a power device according to claim 1, wherein the second switching circuit includes: a first double-knife double-placed relay and a second double-knife double-placed relay, wherein,
the first double-pole double-arrangement relay is characterized in that a first end of the first double-pole double-arrangement relay is connected with a control end of the first power device, a second end of the first double-pole double-arrangement relay is connected with a second end of the first power device, a third end of the first double-pole double-arrangement relay is connected with a first end of the adjustable grid driving resistor array, a fourth end of the first double-pole double-arrangement relay is connected with the first driving power supply, a fifth end of the first double-pole double-arrangement relay is connected with the second grounding end, and a sixth end of the first double-pole double-arrangement relay is connected with the third grounding end;
the first end of the second double-pole double-placed relay is connected with the control end of the second power device, the second end of the second double-pole double-placed relay is connected with the second end of the second power device, the third end of the second double-pole double-placed relay is connected with the first end of the adjustable grid driving resistor array, the fourth end of the second double-pole double-placed relay is connected with the first driving power supply, the fifth end of the second double-pole double-placed relay is connected with the second grounding end, and the sixth end of the second double-pole double-placed relay is connected with the third grounding end;
when the switching time test is carried out on the second power device, the first end of the first double-knife double-placed relay is controlled to be connected with the fourth end of the first double-knife double-placed relay, the second end of the first double-knife double-placed relay is controlled to be connected with the sixth end of the first double-knife double-placed relay, the first end of the second double-knife double-placed relay is controlled to be connected with the third end of the second double-knife double-placed relay, and the second end of the second double-knife double-placed relay is controlled to be connected with the fifth end of the second double-knife double-placed relay;
when the reverse recovery time test is carried out on the second power device, the first end of the first double-knife double-placed relay is controlled to be connected with the third end of the first double-knife double-placed relay, the second end of the first double-knife double-placed relay is controlled to be connected with the fifth end of the first double-knife double-placed relay, the first end of the second double-knife double-placed relay is controlled to be connected with the fourth end of the second double-knife double-placed relay, and the second end of the second double-knife double-placed relay is controlled to be connected with the sixth end of the second double-knife double-placed relay.
4. The apparatus for dynamic characteristics testing a power device according to claim 1, wherein the adjustable gate driving resistor array comprises: the first resistor array branch circuit and the second resistor array branch circuit are connected in anti-parallel.
5. The apparatus for testing dynamic characteristics of a power device according to claim 4, wherein the first resistor array branch includes: a first diode, a plurality of first resistors and a plurality of first controllable switches, wherein,
each first resistor is connected with a first controllable switch in parallel;
the first ends of all the first resistors are connected in series and connected with the cathode of the first diode, and the second ends of all the first resistors are connected in series and connected with the second ends of the adjustable grid driving resistor array;
and the anode of the first diode is connected with a driving signal through the operational amplifier circuit.
6. The apparatus for testing dynamic characteristics of a power device according to claim 4, wherein the second resistive array branch includes: a second diode, a plurality of second resistors and a plurality of second controllable switches, wherein,
each second resistor is connected with a second controllable switch in parallel;
the first ends of all the second resistors are connected in series and connected with the cathodes of the second diodes, and the second ends of all the second resistors are connected in series and connected with the second ends of the adjustable grid driving resistor array;
and the anode of the second diode is connected with a driving signal through the operational amplifier circuit.
7. The dynamic characteristic test apparatus of a power device according to claim 1, further comprising:
and the power supply module is connected with the first switch circuit in parallel and is used for providing a test power supply.
8. The dynamic characteristic test apparatus of a power device according to claim 7, wherein the power module comprises: the first capacitor, the second capacitor, the controllable switch and the programmable power supply, wherein,
the first end of the first capacitor is connected with the first end of the first power device, and the second end of the first capacitor is connected with the second end of the second power device;
the first end of the second capacitor is connected with the first end of the first capacitor through the controllable switch, and the second end of the second capacitor is connected with the second end of the second power device;
a programmable power supply connected in parallel with the second capacitor;
and when the switching time test and the reverse recovery time are carried out on the second power device, controlling the controllable switch to be closed.
9. The dynamic characteristic test method of the power device is characterized by comprising the following steps of:
when the switching time test is carried out on the second power device, the second end of the first power device is connected with the first end of the first power device through a power inductor by controlling the on-off state of the first switching circuit; the control end of the first power device is connected with a first driving power supply, the second end of the first power device is connected with a third grounding end, the control end of the second power device is connected with the first end of the adjustable grid driving resistor array, and the second end of the second power device is connected with the second grounding end;
when the reverse recovery time test is carried out on the second power device, the second end of the first power device is connected with the second end of the first power device through a power inductor by controlling the on-off state of the first switch circuit; the control end of the first power device is connected with the first end of the adjustable grid driving resistor array, the second end of the first power device is connected with the second grounding end, the control end of the second power device is connected with the first driving power supply, and the second end of the second power device is connected with the third grounding end by controlling the on-off state of the second switching circuit.
10. The method for testing dynamic characteristics of a power device according to claim 9, wherein the switching time test process is performed on the second power device, further comprising:
controlling the first power device to be turned off and the second power device to be turned on;
when the current of the power inductor reaches a first preset value, the second power device is controlled to be turned off;
and after the first preset time, controlling the second power device to be conducted.
11. The method for testing dynamic characteristics of a power device according to claim 9, wherein performing a reverse recovery time test procedure on the second power device further comprises:
controlling the first power device to be turned off and the second power device to be turned on;
after a second preset time, controlling the first power device to be turned on and the second power device to be turned off;
when the current of the power inductor reaches a second preset value, the first power device is controlled to be turned off;
and after the third preset time, controlling the first power device to be conducted.
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