CN110112038B

CN110112038B - Relay drive circuit

Info

Publication number: CN110112038B
Application number: CN201910499235.2A
Authority: CN
Inventors: 姜欢; 龚李缘; 陈念
Original assignee: Camel Group Wuhan Optics Valley R&d Center Co ltd
Current assignee: Camel Group Wuhan Optics Valley R&d Center Co ltd
Priority date: 2019-06-11
Filing date: 2019-06-11
Publication date: 2020-11-06
Anticipated expiration: 2039-06-11
Also published as: CN110112038A

Abstract

The invention relates to the field of drive circuits, and discloses a relay drive circuit which comprises an NMOS (N-channel metal oxide semiconductor) tube, a triode and a drive relay, wherein a pin 1 and a pin 12 of the drive relay are internally connected with a coil, a pin 4 and a pin 9 of the drive relay are output pins, a pin 3 and a pin 10 of the drive relay are normally closed pins, a pin 5 and a pin 8 of the drive relay are normally open pins, and the pin 4 and the pin 9 of the drive relay are respectively connected with a coil of a conventional relay or a coil of a magnetic latching relay. The invention has the following advantages and effects: the magnetic latching relay has strong driving capability, can be used for driving a magnetic latching relay and a conventional relay at the same time, and solves the problem of weak driving. And secondly, the magnetic latching relay and the conventional relay can be driven, the compatibility is good, and one circuit is used for two relay scenes. And thirdly, the circuit has simple control logic, low complexity and high reliability. Fourthly, the driving capacity is strong, and the class A can be easily achieved depending on the current capacity of the driving relay K1.

Description

Relay drive circuit

Technical Field

The invention relates to the technical field of driving circuits, in particular to a relay driving circuit.

Background

In power supply systems, particularly lithium battery systems in the new energy industry, two types of relays are often used on the main loop of the system. Firstly, a magnetic latching relay; the other is a common conventional relay.

For a single coil magnetic latching relay, the positive and negative directions of current passed by the coil determine whether the main contact is opened or closed, and for a conventional relay, the high and low levels of the coil determine whether the main contact is opened or closed. Therefore, the two relays are driven in different modes, and for the coil magnetic latching relay, a driving circuit of the coil magnetic latching relay needs to control the opening and closing of the magnetic latching relay by changing the direction of current flowing through a control coil. For a common relay, the function of controlling the relay to be closed and opened can be achieved only by controlling the power supply of the coil of the relay.

In the practical application process, the two driving modes are often incompatible, so that the two relays cannot be shared in the same main loop. In order to solve the problem of difficult engineering application, a control circuit capable of driving the two relays simultaneously needs to be designed.

The chinese invention patent "a single coil magnetic latching relay and its driving circuit" (application number: 201710051226.8) discloses a single coil magnetic latching relay and its driving circuit, in which CTR is a control signal and comes from a controller, such as a single chip microcomputer. Under normal conditions, the enable signal EN is at low level, the triode Q1 is cut off, the operational amplifier U1 and U2 do not work, and the relay keeps the original state; when the state of the relay needs to be changed, the enable signal EN is set to be at a high level, the operational amplifiers U1 and U2 work normally, if CTR is at a low level, the output of the CTR signal is still at the low level after being amplified by the operational amplifier U1, the input end of the operational amplifier U2 is pulled up to be at the high level through the resistor R6, and the output is at the high level; otherwise, if the CTR is high, the output of the U1 is high, the output of the U2 is low, and after the relay reaches a preset state, the state can be maintained by controlling EN to be low. The obvious disadvantage in this patent is that the drive current of the relay is insufficient, the drive capability is completely dependent on the output capability of the operational amplifier, which is generally in the mA level. In most cases, the current at the moment of electrifying the magnetic latching relay can reach more than 2A, and the circuit is not suitable for being used in the case of large circuit and is difficult to be compatible with the conventional relay.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a relay driving circuit. The circuit utilizes 2C monostable signals to drive the switching of the relay contacts to realize the switching of the power supply direction of the coil of the single-coil magnetic latching relay, and the driving capability of the circuit is only related to the driving relay, so that the driving capability of the device is improved.

The technical scheme of the invention is as follows: the utility model provides a relay drive circuit, includes NMOS pipe, triode and drive relay, and drive relay's pin 1 passes through inner coil with pin 12 to be connected, and drive relay's pin 4 and pin 9 are output pin, and drive relay's pin 3 and pin 10 are normally closed pin, and drive relay's pin 5 and pin 8 are normally open pin, its characterized in that: pin 4 and pin 9 of drive relay are connected with conventional relay coil or magnetic latching relay coil respectively, gate G of NMOS pipe is connected with enabling signal after through first resistance, source S of NMOS pipe is grounded, connect the second resistance in parallel between source S and gate G of NMOS pipe, drain D of NMOS pipe is connected with pin 3 and pin 8 of drive relay, pin 10 and pin 5 of drive relay are connected with power VCC, pin 1 of drive relay is connected with power VCC, the collecting electrode C of triode is connected with pin 12 of drive relay, the base B of triode passes through the third resistance after with control signal, the projecting pole E of triode is grounded, connect the fourth resistance in parallel between base B and the projecting pole E of triode.

The relay drive circuit according to the above, characterized in that: the voltage stabilizing diode and the common diode are connected in series between the drain D of the NMOS tube and the collector C of the triode.

The relay drive circuit according to the above, characterized in that: the cathodes of the zener diode and the common diode are connected together.

The relay drive circuit according to the above, characterized in that: the rated current of the driving relay is larger than 2A.

The relay drive circuit according to the above, characterized in that: the NMOS tube is an N-channel MOSFET tube.

The relay drive circuit according to the above, characterized in that: the NMOS tube is replaced by an NPN triode, the triode is replaced by an N-channel MOSFET,

pins

3 and 8 of the driving relay are in short circuit and directly connected with VCC, and

pins

5 and 10 of the driving relay are in short circuit and grounded through the N-channel MOSFET.

The invention has the beneficial effects that: firstly, the driving ability is strong, can be used for magnetic latching relay and conventional relay drive simultaneously, has solved the not strong problem of drive. And secondly, the magnetic latching relay and the conventional relay can be driven, the compatibility is good, and one circuit is used for two relay scenes. And thirdly, the circuit has simple control logic, low complexity and high reliability. Fourthly, the driving capacity is strong, and the class A can be easily achieved depending on the current capacity of the driving relay K1.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a circuit schematic of an embodiment.

Detailed Description

The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without any inventive step, are within the scope of the present invention.

As shown in fig. 1, the RELAY driving circuit of the present invention includes an NMOS transistor U1, a transistor Q1, and a driving RELAY K1, wherein a pin 1 and a pin 12 of the driving RELAY K1 are connected through an internal coil, a pin 4 and a pin 9 of the driving RELAY K1 are output pins, the pin 4 and the pin 9 are respectively connected with a RELAY _ a0 and a RELAY _ B0, a pin 3 and a pin 10 of the driving RELAY K1 are normally closed pins, and a pin 5 and a pin 8 of the driving RELAY K1 are normally open pins. A gate G of an NMOS tube U1 is connected with an enable signal EN through a first resistor R1, a source S of the NMOS tube U1 is grounded, a second resistor R2 is connected between the source S of the NMOS tube U1 and the gate G in parallel, a drain D of the NMOS tube U1 is connected with a pin 3 and a pin 8 of a driving relay K1, and a pin 10 and a pin 5 of the driving relay K1 are connected with a power supply VCC.

As shown in fig. 1, pin 1 of the driving relay K1 is connected to a power source VCC, a collector C of the transistor is connected to pin 12 of the driving relay K1, a base B of the transistor passes through a third resistor R3 and then is connected to a control signal CTR, an emitter E of the transistor is grounded, and a fourth resistor R4 is connected in parallel between the base B and the emitter E of the transistor.

As shown in FIG. 1, the invention can connect a zener diode D1, a normal diode D2, a zener diode D1 and the cathode of a normal diode D2 in series between the drain D of the NMOS transistor and the collector C of the triode.

The driving relay K1 can be a signal relay, the current of A level can be easily achieved by selecting the current capacity of the driving relay K1, if the rated current of the driving relay K1 is selected to be larger than 2A, the controlled magnetic latching relay current can stably work for a long time under 2A, the circuit of the invention is convenient to change the design, and if larger current bearing capacity is needed, the driving relay K1 with stronger driving capacity is better. The NMOS transistor U1 of the present invention may be an N-channel MOSFET transistor.

When the circuit of the invention drives the single-coil magnetic latching RELAY, the RELAY _ A0 and the RELAY _ B0 are respectively connected with the positive pole and the negative pole of the coil of the magnetic latching RELAY. CTR is a control signal given by the controller, and EN is an enable signal given by the controller. When the enable signal EN is at a high level and the control signal CTR is at a low level, the U1 NMOS tube is in a closed state, the pin 3 of the drive RELAY K1 is connected with GND through the NMOS tube U1, at the moment, because the CTR is at the low level, the triode Q1 is in a disconnected state, the drive RELAY K1 is in an inactive state, the

pins

9 and 10 are connected, and the

pins

3 and 4 are connected, namely the RELAY _ A0 is connected with GND; RELAY _ B0 is connected to VCC, and when the coil current of the latching RELAY flows from B0 to A0 (negative to positive), the latching RELAY is turned off. When the enable signal EN is at a high level and the control signal CTR is at a high level, the transistor Q1 is in a closed state, the drive RELAY K1 is in an active state at this time, the

pins

9 and 10 are disconnected, the

pins

3 and 4 are disconnected, the

pins

8 and 9 are connected at the same time, the

pins

4 and 5 are connected, that is, the RELAY _ B0 is connected with GND through the NMOS tube U1, the RELAY _ a0 is connected with VCC, at this time, the coil current of the magnetic latching RELAY flows from a0 to B0 (positive to negative), and the magnetic latching RELAY is closed.

When the circuit of the invention drives the conventional RELAY, the RELAY _ A0 is connected with the cathode of the coil of the conventional RELAY, the RELAY _ B0 is connected with the anode of the coil of the conventional RELAY, and the control of the conventional RELAY can be completed only by controlling an EN level signal. When EN is high level, RELAY _ A0 is connected with GND through U1, RELAY _ B0 is connected with VCC, coils B0 to A0 of the RELAY are conducted with current, and the conventional RELAY is closed; when EN is low, RELAY _ A0 is disconnected from GND, the RELAY coil power supply circuit is cut off, and the conventional RELAY is opened.

As a further scheme of the present invention, the NMOS transistor U1 of the present invention may be replaced by an NPN transistor, the transistor Q1 may be replaced by an N-channel MOSFET, and in the connection manner, the

pins

3 and 8 may be shorted to the direct VCC, and the

pins

5 and 10 may be shorted to the ground through the N-channel MOSFET.

Claims

1. The utility model provides a relay drive circuit, includes NMOS pipe, triode and drive relay, and drive relay's pin 1 passes through inner coil with pin 12 to be connected, and drive relay's pin 4 and pin 9 are output pin, and drive relay's pin 3 and pin 10 are normally closed pin, and drive relay's pin 5 and pin 8 are normally open pin, its characterized in that: pin 4 and pin 9 of drive relay are connected with conventional relay coil or magnetic latching relay coil respectively, gate G of NMOS pipe is connected with enabling signal after passing through first resistance, source S of NMOS pipe is grounded, connect the second resistance in parallel between source S and gate G of NMOS pipe, drain D of NMOS pipe is connected with pin 3 and pin 8 of drive relay, pin 10 and pin 5 of drive relay are connected with power VCC, pin 1 of drive relay is connected with power VCC, the collector C of triode is connected with pin 12 of drive relay, the base B of triode passes through the third resistance after and control signal, the projecting pole E of triode is grounded, connect the fourth resistance in parallel between base B and projecting pole E of triode, the NMOS pipe is N channel MOSFET pipe.

2. A relay drive circuit according to claim 1, wherein: the voltage stabilizing diode and the common diode are connected in series between the drain D of the NMOS tube and the collector C of the triode.

3. A relay drive circuit according to claim 2, wherein: the cathodes of the zener diode and the common diode are connected together.

4. A relay drive circuit according to claim 1, wherein: the rated current of the driving relay is larger than 2A.

5. A relay drive circuit according to claim 1, wherein: the NMOS tube is replaced by an NPN triode, the triode is replaced by an N-channel MOSFET, pins 3 and 8 of the driving relay are in short circuit and directly connected with VCC, and pins 5 and 10 of the driving relay are in short circuit and grounded through the N-channel MOSFET.