CN106154157B - Adjustable surge load test device for electromagnetic relay - Google Patents
Adjustable surge load test device for electromagnetic relay Download PDFInfo
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- CN106154157B CN106154157B CN201610875918.XA CN201610875918A CN106154157B CN 106154157 B CN106154157 B CN 106154157B CN 201610875918 A CN201610875918 A CN 201610875918A CN 106154157 B CN106154157 B CN 106154157B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3277—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
- G01R31/3278—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches of relays, solenoids or reed switches
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Abstract
The application provides an adjustable surge load test device for an electromagnetic relay, wherein the device comprises: the device comprises a test operation terminal, a control/acquisition circuit and a surge load generation unit, wherein the surge load generation unit is connected with the electromagnetic relay in a one-to-one correspondence manner, and the test operation terminal is used for issuing an experiment control command to the control/acquisition circuit and receiving contact current sampling information of the electromagnetic relay through the control/acquisition circuit and the surge load generation unit; the control/acquisition circuit is used for adjusting the resistance value of the surge load generation unit according to the experimental control command so as to output surge current to the electromagnetic relay; the surge load generation unit is used for outputting surge current with a preset magnitude to the electromagnetic relay under the control of the control/acquisition circuit, sampling the contact current sampling information of the electromagnetic relay and feeding back the contact current sampling information to the test operation terminal through the control/acquisition circuit. The application can accurately test the surge resistance of the electromagnetic relay.
Description
Technical Field
The application relates to the technical field of electromagnetic relays, in particular to an electromagnetic relay electric contact performance test analysis device, and specifically relates to an adjustable surge load test device for an electromagnetic relay.
Background
Since electromagnetic relays have the advantage that a range of solid state electronic devices cannot be replaced, such as: high conversion depth, large input-output ratio, etc., which are widely used in the fields of industrial control, communication, electric power, etc., and electromagnetic relays are mainly used for controlling the on-off of system power supply and signals.
In the process of actually using the electromagnetic relay, because of distributed inductance and capacitance in an actual circuit, transient overvoltage or overcurrent is generated when the contact of the electromagnetic relay is opened and closed, so that the contact of the electromagnetic relay is damaged by transient arc ablation or is stuck and invalid, and the electric life of an electromagnetic relay product is influenced. Therefore, the surge resistance of the electromagnetic relay product is tested and analyzed through the surge test, so that the method has important significance.
At present, research on the influence of surges on relay contacts is widely focused at home and abroad, but no special test device is used for automatically carrying out surge tests on a plurality of groups of electromagnetic relay test pieces according to the requirements of a test scheme and feeding back test information, and the existing surge test device mainly has the following defects:
1. the surge current time is controlled by adjusting the charge and discharge time of the capacitor, so that the precision is low, and the relationship between the surge current time and the electric life is difficult to quantitatively describe when experimental analysis is performed;
2. when surge test conditions in the test scheme need to be changed or the test conditions of a plurality of electromagnetic relay test pieces are inconsistent, each surge test device needs to be manually adjusted one by one, and the test efficiency is low;
3. in the surge test process, the monitoring of the contact voltage/current waveform is realized through equipment such as an oscilloscope, so that the surge test is difficult to be carried out on a plurality of groups of electromagnetic relay test pieces at the same time, and test information of each test piece in the test process is inconvenient to check in real time by a tester;
4. the circuit structure is fixed, is difficult to flexibly expand, and when the number of test pieces exceeds the allowable number of the equipment, test staff is required to manually switch and test in batches, and the test is long in time consumption.
Accordingly, those skilled in the art are highly required to develop a high-efficiency surge experiment device capable of quantitatively describing the relationship between the surge current time and the electrical life.
Disclosure of Invention
In view of the above, the technical problem to be solved by the present application is to provide an adjustable surge load test device for electromagnetic relay, the problem that the relation between the surge current time and the electric life cannot be quantitatively described by the existing surge test device is solved.
In order to solve the above technical problems, a specific embodiment of the present application provides an adjustable surge load test device for an electromagnetic relay, including: the device comprises a test operation terminal, a plurality of control/acquisition circuits connected with the test operation terminal and a plurality of surge load generation units connected with the control/acquisition circuits, wherein the surge load generation units are connected with the electromagnetic relays in a one-to-one correspondence manner, and the test operation terminal is used for issuing test control commands to the control/acquisition circuits and receiving contact current sampling information of the electromagnetic relays through the control/acquisition circuits and the surge load generation units; the control/acquisition circuit is used for adjusting the resistance value of the surge load generation unit according to the experimental control command so as to output surge current to the electromagnetic relay; the surge load generation unit is used for outputting surge current with a preset magnitude to the electromagnetic relay under the control of the control/acquisition circuit, sampling the contact current sampling information of the electromagnetic relay and feeding back the contact current sampling information to the test operation terminal through the control/acquisition circuit.
According to the above specific embodiments of the present application, the adjustable surge load test device for electromagnetic relay has at least the following advantages: realizing a plurality of electromagnetic relays surge current time of test piece independent control of surge interval time and surge times; full-automatic surge test of a plurality of electromagnetic relay test pieces is completed, and the surge test duration time, the number of completed surge times and the contact current waveform of each electromagnetic relay test piece are displayed in real time; the surge load test can be carried out on one electromagnetic relay test piece independently, and the surge load test under independent test conditions can be carried out on a plurality of electromagnetic relays simultaneously, so that the surge resistance of the electromagnetic relay can be accurately tested; the real-time monitoring and inquiry of relevant test information (such as surge test duration, completed surge times and contact current waveforms) of each electromagnetic relay test piece are supported, and surge load tests can be simultaneously carried out on a plurality of groups of electromagnetic relay contacts according to the requirements of different test schemes, so that the test efficiency is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the scope of the application, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and, together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic block diagram of an adjustable surge load test apparatus for an electromagnetic relay according to an embodiment of the present application;
FIG. 2 is a schematic block diagram of a control/acquisition circuit provided in accordance with an embodiment of the present application;
FIG. 3 is a schematic circuit diagram of a surge load generating unit according to an embodiment of the present application;
FIG. 4 shows a processor control method according to an embodiment of the present application schematic diagram of the control of the surge load generating unit by the acquisition circuit.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the spirit of the present disclosure will be clearly described in the following drawings and detailed description, and any person skilled in the art, after having appreciated the embodiments of the present disclosure, may make alterations and modifications by the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.
The exemplary embodiments of the present application and the descriptions thereof are intended to illustrate the present application, but not to limit the present application. In addition, the same or similar reference numerals are used for the same or similar parts in the drawings and the embodiments.
The terms "first," "second," …, and the like, as used herein, do not denote a particular order or sequence, nor are they intended to limit the application, but rather are merely used to distinguish one element or operation from another in the same technical term.
With respect to directional terms used herein, for example: upper, lower, left, right, front or rear, etc., are merely references to the directions of the drawings. Thus, directional terminology is used for purposes of illustration and is not intended to be limiting.
As used herein, "comprising" "including," "having," "containing," etc., all are open language meaning including but not limited to.
As used herein, "and/or" includes any or all combinations of such things.
The terms "about," "approximately" and the like as used herein are used to modify any quantitative or positional deviation that could vary slightly without such slight variation or positional deviation altering its nature. In general, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. It should be understood by those skilled in the art that the above mentioned values can be adjusted according to the actual requirements, and are not limited thereto.
Certain words used to describe the application will be discussed below or elsewhere in this specification, to provide additional guidance to those skilled in the art in describing the application.
Figure 1 is a schematic block diagram of an adjustable surge load test apparatus for an electromagnetic relay according to an embodiment of the present application, as shown in figure 1 of the drawings, the adjustable surge load test device comprises: a test operation terminal 1, a control/acquisition circuit 2 connected to a plurality of the test operation terminals 1, and a surge load generation unit 3 connected to an electromagnetic relay; the surge load test device is used for completing the surge load test of the electromagnetic relay.
As shown in the figure, the adjustable surge load test device mainly includes: the test operation terminal 1 (mainly composed of an upper computer 11 and a processor 12), a plurality of control/acquisition circuits 3 and a plurality of surge load generating units 3. The upper computer 11, the processor 12 and the control/acquisition circuit 3 are specifically described as follows:
(1) Host computer 11
The upper computer 11 may be a PC equipped with test management software, the PC is connected to the processor 12 via a CAN bus, the PC sends a surge test condition setting command to the processor 12 through the CAN bus, and the PC is also used for displaying surge load test information of the electromagnetic relay fed back by the processor 12 received through the CAN bus; in a specific embodiment of the present application, the surge test condition setting command includes a surge current time, a surge interval time and a surge frequency of each surge load generating unit; the surge load test information comprises the surge test duration time, the number of completed surges and the contact current sampling information of the electromagnetic relay test piece of each surge load generation unit.
(2) Processor 12
In the specific embodiment of the application, the processor 12 can adopt an STM32 singlechip, and the processor 12 is used for receiving a surge test condition setting command sent by the upper computer 11 and feeding back surge load test information of the electromagnetic relay test piece; the processor 12 is further used for controlling the surge load generating units 3 to output surge currents to the electromagnetic relays according to the requirements of surge test conditions through the control/acquisition circuit 2.
(3) Control/acquisition circuit 2
The control/acquisition circuit 2 is used for receiving a control command sent by the processor 12 and testing a specified electromagnetic relay through the surge load generation unit 3 according to the command; the control/acquisition circuit 2 is also used for monitoring contact current sampling information of the electromagnetic relay in the surge test process, and feeding back the monitored contact current sampling information to the processor 12.
Fig. 2 is a schematic block diagram of a control/acquisition circuit according to an embodiment of the present application, and as shown in fig. 2, each control/acquisition circuit 2 includes a board selection circuit 21, a main control unit 22, a data acquisition circuit 23, and a coil driving circuit 24, and each control/acquisition circuit 2 may be connected to 8 surge load generation units 3. Wherein the enable signal input end of the board selection circuit 21 is connected with the circuit selection signal output pin of the processor 12; the data acquisition control I/O port of the main control unit 22 is connected with the data output pin of the data acquisition circuit 23, the coil drive control I/O port of the main control unit 22 is connected with the control input port of the coil drive circuit 24, the CS port, the IN port and the OUT port of the main control unit 22 are connected with the control and data acquisition I/O port of the processor 12; the power supply input ends of the main control unit 22, the data acquisition circuit 23 and the coil driving circuit 24 are all connected with the board selection circuit 21.
Referring again to fig. 2, the board select circuit 21 is mainly composed of a first relay 211, a triode 212, a first resistor 213, and a second resistor 214. The first relay 211 is provided with a coil 2111 and a normally open contact 2112, one ends of the coil 2111 and the normally open contact 2112 of the first relay 211 are short-circuited and then connected with a positive power supply VCC, and the other end of the normally open contact 2112 of the first relay 211 is connected with the power supply input ends of the main control unit 22, the data acquisition circuit 23 and the coil driving circuit 24; the other end of the coil 2111 of the first relay 211 is connected with the collector of the triode 212, the emitter of the triode 212 is grounded, the emitter and the base of the triode 212 are connected through a first resistor 213 and a second resistor 214, a node between the first resistor 213 and the second resistor 214 is an enabling signal input end of the board selection circuit 21, and the enabling signal input end of the board selection circuit 21 is connected with a circuit selection signal output pin of the processor 12.
The data acquisition circuit 23 comprises a voltage dividing circuit, a follower circuit and an a/D conversion chip (not shown in the figure), wherein an E port of the surge load generating unit 3 is connected to an input pin of the a/D conversion chip through the voltage dividing circuit and the follower circuit, and an output pin of the a/D conversion chip is connected with a group of data acquisition control I/O ports of the main control unit 22; in the embodiment of the application, the follower circuit mainly comprises LF356, and the A/D conversion chip may be AD9220.
The coil driving circuit 24 may be composed of a transistor array ULN2803, where 8 control input ports of the transistor array are connected to a set of coil driving control I/O ports of the main control unit 22, and 8 output ports of the transistor array are connected to D ports of the 8 surge load generating units 3, respectively.
The main control unit 22 may adopt an FPGA chip EP2C35F484, a set of data acquisition control I/O ports of the main control unit 22 are connected to data output pins of the data acquisition circuit 23, a set of coil drive control I/O ports of the main control unit 22 are connected to control input ports of the driving circuit 24, and CS ports, IN ports, and OUT ports of the main control unit 22 are connected to a set of control and data acquisition I/O ports of the processor 12.
Fig. 3 is a schematic circuit diagram of a surge load generating unit according to an embodiment of the present application, referring to fig. 3, a specific example of the surge load generating unit 3 is as follows:
the surge load generation unit 3 specifically comprises a third resistor 31, a fourth resistor 32, a fifth resistor 33, an MOS tube 34, a sixth resistor 35 and a seventh resistor 36, wherein one end of the third resistor 31 is connected with a dynamic contact and a static contact of the electromagnetic relay through an A port, and the other end of the third resistor 31 is connected with a B port; a fourth resistor 32 having one end connected to the B port and the other end grounded; a fifth resistor 33 having one end connected to the a port; the drain electrode of the MOS tube 34 is connected with the other end of the fifth resistor 33, the base electrode is connected with the C port, and the source electrode is connected with the E port; a sixth resistor 35, one end of which is connected to the drain of the MOS transistor 34, and the other end of which is connected to the source of the MOS transistor 34; and one end of the seventh resistor 36 is connected with the source electrode of the MOS tube 34, and the other end of the seventh resistor is grounded.
In the specific embodiment of the present application, the resistance value of the third resistor 31 is 7500 ohms; the resistance value of the fourth resistor 32 is 1000 ohms; the resistance value of the fifth resistor 33 is 5.6 ohms; the resistance value of the sixth resistor 35 is 22 ohm; the resistance of the seventh resistor 36 is 0.1 ohm.
The surge load generation unit 3 is used for outputting surge current to the electromagnetic relay according to the instruction of the control/acquisition circuit 2; the surge load generating unit 3 is also used for driving coils (i.e. winding) of the corresponding electromagnetic relays according to the instruction of the control/acquisition circuit 2 so as to enable the electromagnetic relays to operate; the surge load generation unit 3 is also used for sampling contact current in the surge test process of the electromagnetic relay; the surge load generation unit 3 may further control the magnitude of the surge current by adjusting the resistance values of the fifth resistor 33 and the sixth resistor 35.
Fig. 4 is a schematic diagram of a processor for controlling a surge load generating unit through a control/acquisition circuit according to an embodiment of the present application, fig. 4 is a schematic diagram of a processor 12 for controlling a surge load generating unit 3 through a control/acquisition circuit 2 shown in fig. 4, an A port (namely a terminal A) of the surge load generating unit 3 in the figure 3 is connected with the movable and static contact 4-1 of the electromagnetic relay test piece and is used for controlling the on-off of surge currents of the movable and static contact groups 4-1 and 4-3 of the electromagnetic relay; the B port (i.e., terminal B) of the surge load generating unit 3 in fig. 3 is connected to the Bi (i=1, 2 … 8) port of the control/acquisition circuit 2 for feeding back the level state of the electromagnetic relay moving-on stationary contact; in fig. 3, the port C (i.e., terminal C) is connected to the port Ci (i=1, 2 … 8) of the control/acquisition circuit 2, and is configured to receive a control signal from the control/acquisition circuit 2 to the MOS transistor 34; the D port (i.e., terminal D) in fig. 3 is connected to the Di (i=1, 2 … 8) port of the control/acquisition circuit 2, and is used for controlling the action of the electromagnetic relay according to the control command output by the control/acquisition circuit 2; the E port (i.e. terminal E) in fig. 3 is connected to the Ei (i=1, 2 … 8) port of the control/acquisition circuit 2, and is used for outputting the sampled voltage of the electromagnetic relay moving contact set to the control/acquisition circuit 2 during the test; the first end of the third resistor 31 is connected with the first end of the fifth resistor 33 and the movable contact and the stationary contact of the electromagnetic relay; the first end of the fourth resistor 32 is grounded GND; a second end of the third resistor 31 and a second end of the fourth resistor 32 are connected with a terminal B; the second end of the fifth resistor 33 is connected with the first end of the sixth resistor 35 and the drain electrode of the MOS tube 34; the second end of the sixth resistor 35 is connected with the first end of the seventh resistor 36 and the source electrode of the MOS tube 34; the seventh resistor 36 the second end is grounded GND; the third resistor 31 (with a resistance value of 7500 ohms) and the fourth resistor 32 (with a resistance value of 1000 ohms) form a voltage dividing circuit, and are configured to divide the voltage of the movable contact and the static contact of the electromagnetic relay, so that the voltage meets the input level requirement of the control/acquisition circuit 2 (the input level requirement of the control/acquisition circuit 2 is 3.3V), and particularly when the movable contact and the static contact level is 28V, the voltage dividing circuit is turned on: +28V→moving contact group→the third resistor 31→the fourth resistor 32→GND, the level at the terminal B is equal to 28V/(7.5KΩ+1KΩ) × (1KΩ) ≡3.3V, when the moving contact level is 0V, the voltage dividing circuit is disconnected, and the level at the terminal B is 0V; the fifth resistor 33, the sixth resistor 35 and the MOS tube 34 are used for controlling on-off of surge current of the electromagnetic relay moving contact set according to the level state of the terminal C; the seventh resistor 36 (resistance 0.1 ohm) is used to sample the current flowing through the set of contact sets.
The electromagnetic relay portion mainly includes:
the number of the electromagnetic relay test pieces for carrying out surge load test can be flexibly designed according to actual needs and the number of the surge load generation units.
As shown in fig. 4, the surge load test of the electromagnetic relays 1 and 9 will be described in detail as an example: setting surge test conditions (the surge current time of the surge load generating unit 1 is 5ms, the surge interval is 10ms and the surge frequency is 2000 times; the surge current time of the surge load generating unit 9 is 10ms, the surge interval is 10ms and the surge frequency is 1000 times) at a test operation terminal, and sending the surge test conditions to a processor through a CAN bus by the test operation terminal; after the processor enables EN1, EN2, CS1, CS2 ports, test conditions of the electromagnetic relay test pieces 1, 9 are respectively sent to IN ports of the control/acquisition circuit 1 and the control/acquisition circuit 2 through OUT1, OUT2 ports, and a test start command is sent. For electromagnetic relay test piece 1 (9): the C1 port of the control/acquisition circuit 1 (2) outputs a high level, and the MOS tube in the surge load generation unit 1 (9) short-circuits a sixth resistor (22 ohm); the D1 port of the control/acquisition circuit 1 (2) outputs a high level, the electromagnetic relay (9) starts to act, and the control/acquisition circuit 1 (2) starts to continuously acquire voltage data of the terminal E of the surge load generation unit 1 (9); when the control/acquisition circuit 1 (2) detects that the terminal B level of the surge load generation unit 1 (9) is changed from low to high, the port C1 keeps outputting the high level for 5ms (10 ms), in the process the surge loop is turned on: +28V→a movable contact group→a fifth resistor (5.6 ohms) →a MOS tube→the fifth resistor (0.1 ohms) →GND, and the loop current is equal to 28V/(5.6Ω+0.1Ω) ≡5A; then, the port C1 outputs a low level, the MOS transistor is turned off, the sixth resistor is connected to the loop, and the load loop is turned on: +28v→a moving contact group→the fifth resistor (5.6 ohms) →the sixth resistor (22 ohms) →the seventh resistor (0.1 ohms) →gnd, a loop current of 28V/(5.6Ω+22Ω+0.1Ω) ≡1a), the control/acquisition circuit 1 (2) stops the voltage data acquisition to the terminal E of the surge load generation unit 1 (9); the electromagnetic relay test piece 1 (9) completes a surge test, and the control/acquisition circuit 1 (2) feeds back the acquired voltage data of the terminal E of the surge load generation unit 1 (9) to an IN1 port of the processor through an OUT port; the processor adds 1 to the surge times of the electromagnetic relay 1 (9), feeds back the surge times of the electromagnetic relay 1 (9) and voltage data of the terminal E to the test operation terminal through the CAN bus, converts the voltage data of the terminal E into current waveforms of the movable contact group of the electromagnetic relay 1 (9), and displays surge test information; after the C1 port of the control/acquisition circuit 1 (2) continuously outputs a low level for 10ms, performing the next surge test; until the number of surges of 2000 times (1000 times) is completed, the control/acquisition circuit 1 (2) returns test end information to the processor, the processor stops enabling the EN1, EN2, CS1 and CS2 ports, and the surge test of the electromagnetic relay 1 (9) is completed. The adjustable surge load test device for the electromagnetic relay has the characteristics of simple circuit, low cost, flexible expansion according to a test scheme, no need of manual operation in a test process, stable performance and the like.
In summary, the above embodiment of the present application has at least the following advantages:
1. according to the surge test method, surge test conditions can be set through the test operation terminal according to the surge test requirements of the electromagnetic relay, so that the surge current time and the surge test times of one or more groups of electromagnetic relay contacts can be automatically and independently controlled, multiple groups of test schemes can be executed at the same time, and the test time is saved; 2. the upper computer can receive surge test information fed back by the processor in real time, the inquiry of test personnel is facilitated; 3. the circuit structure of the application is simple, the cost is low, the expansion is realized, the test process is full-automatic, the manual intervention is less, the surge test can be simultaneously carried out on a plurality of electromagnetic relays, and the test cost is reduced.
The application provides an adjustable surge load test device for an electromagnetic relay, which is used for realizing independent control of surge current time, surge interval time and surge times of a plurality of electromagnetic relay test pieces at the same time; full-automatic surge test of a plurality of electromagnetic relays is completed, and the surge test duration time, the number of completed surge times and the contact current waveform of each electromagnetic relay are displayed in real time; the surge load test can be carried out on one electromagnetic relay alone, and the surge load test under independent test conditions can be carried out on a plurality of electromagnetic relays at the same time, so that the surge resistance of the electromagnetic relay can be accurately tested; the real-time monitoring and inquiring of relevant test information (such as surge test duration, completed surge times and contact current waveforms) of each electromagnetic relay are supported, and surge load tests can be simultaneously carried out on a plurality of groups of electromagnetic relay contacts according to the requirements of different test schemes, so that the test efficiency is improved.
Those of ordinary skill in the art will appreciate that: the drawing is a schematic diagram of one embodiment and the modules or flows in the drawing are not necessarily required to practice the application.
Those of ordinary skill in the art will appreciate that: the modules in the apparatus of the embodiments may be distributed in the apparatus of the embodiments according to the description of the embodiments, or may be located in one or more apparatuses different from the present embodiments with corresponding changes. The modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.
The embodiments of the application described above may be implemented in various hardware, software code or a combination of both. For example, embodiments of the application may also be program code for performing the above-described methods in a data signal processor (Digital Signal Processor, DSP). The application may also relate to various functions performed by a computer processor, digital signal processor, microprocessor, or field programmable gate array (Field Programmable Gate Array, FPGA). The processor described above may be configured in accordance with the present application to perform specific tasks by executing machine readable software code or firmware code that defines the specific methods disclosed herein. The software code or firmware code may be developed in different programming languages and in different formats or forms. The software code may also be compiled for different target platforms. However, the different code patterns, types and languages of software code and other types of configuration code that perform tasks according to the application do not depart from the spirit and scope of the application.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (5)
1. An adjustable surge load test device for an electromagnetic relay, characterized in that the device comprises: the device comprises a test operation terminal (1), a plurality of control/acquisition circuits (2) connected with the test operation terminal (1) and a plurality of surge load generation units (3) connected with the control/acquisition circuits (2), wherein the surge load generation units (3) are connected with electromagnetic relays in a one-to-one correspondence manner,
the test operation terminal (1) is used for issuing an experiment control command to the control/acquisition circuit (2) and receiving contact current sampling information of the electromagnetic relay through the control/acquisition circuit (2) and the surge load generation unit (3);
the control/acquisition circuit (2) is used for adjusting the resistance value of the surge load generation unit (3) according to the experimental control command so as to output surge current to the electromagnetic relay;
the surge load generation unit (3) is used for outputting surge current with a preset magnitude to the electromagnetic relay under the control of the control/acquisition circuit (2), sampling the contact current sampling information of the electromagnetic relay and feeding back the contact current sampling information to the test operation terminal (1) through the control/acquisition circuit (2);
the test operation terminal (1) specifically comprises:
the upper computer (11) is used for setting surge experiment parameters and displaying contact current waveforms; and
the processor (12) is connected with the upper computer (11) and is used for generating an experiment control command according to the surge experiment parameters;
the control/acquisition circuit (2) comprises in particular: the circuit comprises a board selection circuit (21), a main control unit (22), a data acquisition circuit (23) and a coil driving circuit (24),
an enabling signal input end of the board selection circuit (21) is connected with a circuit selection signal output pin of the processor (12);
the data acquisition control I/O port of the main control unit (22) is connected with the data output pin of the data acquisition circuit (23), the coil drive control I/O port of the main control unit (22) is connected with the control input port of the coil drive circuit (24), and the CS port, the IN port and the OUT port of the main control unit (22) are connected with the control of the processor (12) and the data acquisition I/O port;
the power supply input ends of the main control unit (22), the data acquisition circuit (23) and the coil driving circuit (24) are connected with the board selection circuit (21);
the board select circuit (21) further includes:
the first relay (211) is provided with a coil (2111) and a normally open contact (2112), wherein one end of the coil (2111) is connected with the positive electrode of the power supply after being short-circuited with one end of the normally open contact (2112);
a triode (212) whose collector is connected to the other end of the coil (2111) and whose emitter is grounded;
a first resistor (213) having one end connected to the base of the triode (212) and the other end connected to a circuit selection signal output pin of the processor (12); and
a second resistor (214), one end of the transistor is connected with the emitter of the triode (212), the other end is connected with a circuit selection signal output pin of the processor (12);
the upper computer (11) is a personal computer; the processor (12) is an STM32 singlechip;
the surge load generation unit (3) specifically includes:
a third resistor (31) with a first end connected with the movable contact and the stationary contact of the electromagnetic relay;
a fourth resistor (32) having a first end connected to a second end of the third resistor (31), and a second end grounded;
a fifth resistor (33) having a first end connected to the movable contact of the electromagnetic relay;
a MOS tube (34) with a drain connected to the second end of the fifth resistor (33), a base connected to the C of the control/acquisition circuit (2) i The source is connected with E of the control/acquisition circuit (2) i The ports are connected;
a sixth resistor (35) with a first end connected with the drain electrode of the MOS tube (34) and a second end connected with the source electrode of the MOS tube (34); and
and the first end of the seventh resistor (36) is connected with the source electrode of the MOS tube (34), and the second end of the seventh resistor is grounded.
2. The method for electric power of claim 1 an adjustable surge load test device of a magnetic relay, the resistor is characterized in that the resistance value of the third resistor (31) is 7500 ohms; the fourth resistor (32) the resistance value of (2) is 1000 ohm; the resistance value of the fifth resistor (33) is 5.6 ohms; the resistance value of the sixth resistor (35) is 22 ohms; the resistance value of the seventh resistor (36) is 0.1 ohm.
3. The adjustable surge load test device for an electromagnetic relay according to claim 1, wherein the main control unit (22) is an FPGA chip; the coil driving circuit (24) is a transistor array, the control input end of the transistor array is connected with the coil driving control I/O port of the main control unit (22), and the output port of the transistor array is connected with the electromagnetic relay coil (W) through the surge load generating unit (3).
4. The adjustable surge load test apparatus for an electromagnetic relay according to claim 1, wherein the data acquisition circuit (23) further comprises: a voltage dividing circuit, a follower circuit and an A/D conversion chip, wherein,
the E port of the surge load generating unit (3) is connected to the input pin of the A/D conversion chip through the voltage dividing circuit and the follower circuit, and the output pin of the A/D conversion chip is connected with the data acquisition control I/O port of the main control unit (22).
5. The adjustable surge load test device for an electromagnetic relay according to claim 1, wherein the first end of the fourth resistor (32) is connected to the main control unit (22).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| EP3627165A4 (en) * | 2017-05-16 | 2020-12-02 | Tatsumi Ryoki Co., Ltd | Load system, load test device, and communication terminal |
| CN109117338A (en) * | 2017-06-22 | 2019-01-01 | 许继集团有限公司 | A kind of high-tension apparatus on-line monitoring identification method of sensor, system and acquisition unit |
| CN112305399B (en) * | 2019-08-01 | 2023-01-13 | 欣旺达电动汽车电池有限公司 | Surge testing method and device for front-end acquisition chip of BMS (battery management system) of electric automobile |
| CN110794278B (en) * | 2019-10-23 | 2020-10-27 | 浙江大学 | SiC MOSFET surge performance test method |
| CN113552475B (en) * | 2020-04-24 | 2023-03-31 | 贵州振华群英电器有限公司（国营第八九一厂） | Current surge test device |
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