CN114844348A - Power supply circuit, display panel and display device - Google Patents
Power supply circuit, display panel and display device Download PDFInfo
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- CN114844348A CN114844348A CN202110145442.5A CN202110145442A CN114844348A CN 114844348 A CN114844348 A CN 114844348A CN 202110145442 A CN202110145442 A CN 202110145442A CN 114844348 A CN114844348 A CN 114844348A
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- 230000004044 response Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 51
- 229920001621 AMOLED Polymers 0.000 claims description 28
- 230000001105 regulatory effect Effects 0.000 claims description 5
- 239000003381 stabilizer Substances 0.000 claims description 5
- 230000000087 stabilizing effect Effects 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present disclosure relates to the technical field of power supply circuits, and provides a power supply circuit, a display panel and a display device, wherein the power supply circuit generates a clock signal according to a control signal by using a logic control unit; generating a first driving signal and a second driving signal by using a grid driver; then, according to the response of the first charge pump, the partial node voltage which is different in multiplication ratio from the input voltage is output under the first driving signal or the second driving signal; and generating a negative voltage according to the node division voltage by using a second charge pump, wherein the first driving signal and/or the second driving signal are/is used for indicating the on/off of at least one transistor in the first charge pump and the second charge pump respectively, and the second driving signal and the first driving signal are mutually inverse signals. Therefore, the power supply can be flexibly selected according to specific application scenes, the problem of the size of the inductor is eliminated, the total area of the power supply circuit is effectively reduced, the working efficiency of the power supply can be improved, and the cost of a power supply chip is reduced.
Description
Technical Field
The disclosure relates to the technical field of power circuits, in particular to a power circuit, a display panel and a display device.
Background
Power supplies are important components in electronic products. It is a current technological trend to use fewer power supplies in electronic products to simplify power supply requirements. However, in some special electronic applications, it is also necessary to use multiple power sources for power supply, and in particular in some applications, it is necessary to use both positive and negative power sources for power supply.
The electronic applications of the existing simultaneous positive and negative power sources include: the front end part of the office interface circuit, the liquid crystal display, the OLED (Organic Light-Emitting Diode) display, the CCD (Charge Coupled Device) bias, the power amplifying circuit and the instrument analog input of the traditional telephone. Except the front-end simulation part of the instrument, other parts are applied to large-scale power supplies, and a large number of special mature commercial products are available. Aiming at the front-end simulation part of an instrument and meter, a discrete power circuit combination is generally used for realizing a positive power supply and a negative power supply due to the special requirements of testing.
Compared with the conventional liquid crystal panel, an Active Matrix Organic Light Emitting Diode (AMOLED) panel has the characteristics of fast response speed, high contrast ratio, wide viewing angle and the like. The smart phone is widely used in smart bracelets, smart watches, smart phones, tablet computers, notebook computers and the like. Existing power supply chips and power supply circuits (such as power supplies of AMOLEDs) providing positive and negative power supplies almost all employ DC-DC converters having an inductive architecture.
A DC-DC system that simply uses Buck or LDO as a regulator cannot obtain a stable output voltage when the battery voltage is lower than the system required voltage, and the normal available battery voltage will be required to be higher by adding the voltage drop actually existing in the converter. Since most MCU systems use 3.3V as the system power supply, the available battery voltage is normally above 3.4V, even up to 3.6V, especially in the case of large load currents. One solution to this problem is to use a Boost (Boost) device with Bypass function, and set its output voltage to a level that can maintain the system to continuously operate until the battery power is exhausted, so that the Boost device only performs voltage boosting operation when needed, and directly provides the input to the load when not needed, without any conversion, as shown in fig. 1.
In the conventional power circuit 100 based on an inductor structure and used for an active matrix organic light emitting diode panel, the power circuit 100 has a voltage input terminal VIN, a clock control signal input terminal CTRL, a positive voltage output terminal ELVDD, and a negative voltage output terminal ELVSS, the voltage input terminal VIN of the power circuit 100 is directly powered by connecting a battery port, and the battery port supplies power to other circuits of a chip through a buck converter 102 and an inductor Ls connected in series. Wherein, this power supply circuit 100 still includes: a logic control unit 110 connected to the Voltage input terminal VIN and the clock control signal input terminal CTRL, respectively, a DC-DC converter 120 connected to the Voltage input terminal VIN and the logic control unit 110, a Negative Voltage Charge Pump (Negative Voltage Charge Pump)130, a low dropout linear regulator (LDO)140 connected between the DC-DC converter 120 and the positive Voltage output terminal ELVDD, and an LDO 150 connected between the Negative Voltage Charge Pump 130 and the Negative Voltage output terminal ELVSS. The power circuit 100 is based on an inductance-structured (boost-type or boost-type) DC-DC converter 120, and performs multiplying power boosting or voltage reduction on a voltage accessed by a voltage input terminal VIN to a vicinity of a required voltage, generates an intermediate node voltage VOP having an absolute voltage slightly higher than an output positive voltage and an output negative voltage, and generates an output positive voltage after the intermediate node voltage VOP is reduced by an LDO 140, and provides the output positive voltage to a load circuit of the AMOLED through a positive voltage output terminal ELVDD. A circuit that generates the intermediate node voltage VON by using the negative voltage charge pump 130 and then generates an output negative voltage through the LDO 150 has been developed in a large number of mature commercial products, and the output negative voltage is provided to the load circuit of the AMOLED through the negative voltage output terminal ELVSS.
The AMOLED power supply circuit of the current scheme is a switch power supply framework based on an inductor, the area and the thickness of the inductor severely restrict the selection of the inductor in the application of extremely paying attention to the size and the height of a device such as an intelligent bracelet, an intelligent watch and the like, the circuit design and the product thickness design are influenced, a customer is often forced to select the inductor with a relatively small size but a large direct current impedance DCR, the working efficiency is sacrificed, and the standby time is shortened.
In addition, the noise of the output voltage of the boost-type or buck-type power converter in the prior art is increased, and in electronic products requiring low noise and stable voltage, the application causes serious electromagnetic interference (EMI) and radiation problems due to the periodic charging and discharging process of the inductor, and is severely limited in the occasions sensitive to noise such as radio frequency and the like.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides a power supply circuit, a display panel and a display device, which can flexibly select a power supply according to a specific application scenario, thereby not only eliminating the problem of the size of an inductor and effectively reducing the total area of the power supply circuit, but also improving the working efficiency of the power supply and reducing the cost of a power supply chip and a peripheral circuit.
This disclosure provides a power supply circuit in one aspect, this power supply circuit has voltage input end, control signal input end, malleation output and negative voltage output, and wherein, this power supply circuit still includes:
the logic control unit is connected with the control signal input end and used for generating a clock signal according to the accessed control signal;
a gate driver connected to an output terminal of the logic control unit, the gate driver being configured to generate a first driving signal and a second driving signal according to an input voltage and the clock signal;
a first charge pump, an input terminal of which is connected to the voltage input terminal and an output terminal of the gate driver, respectively, and configured to operate in multiple modes in response to the first driving signal or the second driving signal, so as to obtain different multiplication ratios of the node voltage output by the first charge pump to the input voltage;
a second charge pump having an input terminal connected to the output terminal of the gate driver and the output terminal of the first charge pump, respectively, and configured to generate a negative voltage according to the node voltage in response to the first driving signal or the second driving signal,
the first driving signal and/or the second driving signal are used for indicating the on/off of at least one transistor in the first charge pump and the second charge pump respectively, and the second driving signal and the first driving signal are opposite phase signals.
Preferably, the aforementioned power supply circuit further includes:
the positive voltage stabilizer is connected with the output end of the first charge pump and used for converting the subnode voltage into a first output power supply and outputting the first output power supply to the positive voltage output end;
a negative voltage stabilizer connected with the output end of the second charge pump for converting the negative voltage into a second output power supply and outputting the second output power supply to the negative voltage output end,
the first output power supply is a positive power supply with a first target voltage, and the second output power supply is a negative power supply with a second target voltage.
Preferably, the multiplication ratio of the division node voltage and the input voltage for obtaining the output of the first charge pump is greater than 0 and less than or equal to 1, or greater than 1.
Preferably, the first charge pump has a first input terminal connected to the voltage input terminal, a second input terminal and a third input terminal connected to the gate driver, a first output terminal providing the node voltage, and further comprises:
a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series between the first input terminal and ground, wherein the control terminals of the first transistor and the third transistor are connected in common as the second input terminal to receive the first driving signal, and the control terminals of the second transistor and the fourth transistor are connected in common as the third input terminal to receive the second driving signal;
a first capacitor having a first end connected to a connection node between the first transistor and the second transistor and a second end connected to a connection node between the third transistor and the fourth transistor;
a second capacitor having a connection node between the second transistor and the third transistor as the first input terminal, the second capacitor being connected between the first input terminal and ground;
and a third capacitor connected between the first output terminal and a connection node of the first transistor and ground.
Preferably, the second charge pump has a fourth input terminal connected to the first output terminal, a fifth input terminal and a sixth input terminal connected to the gate driver, and a second output terminal providing the negative voltage, and further includes:
a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series between the fourth input terminal and the second output terminal, wherein the fifth transistor and a control terminal of the seventh transistor are connected in common as the fifth input terminal to which the first drive signal is input, the sixth transistor and a control terminal of the eighth transistor are connected in common as the sixth input terminal to which the second drive signal is input, and a connection node between the sixth transistor and the seventh transistor is grounded;
a fourth capacitor having a first terminal connected to a connection node between the fifth transistor and the sixth transistor, and a second terminal connected to a connection node between the seventh transistor and the eighth transistor;
and a fifth capacitor connected between the second output terminal and a connection node of the eighth transistor and ground.
Preferably, any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a metal oxide semiconductor field effect transistor.
Preferably, the aforementioned power supply circuit is integrated on one chip.
Preferably, the power supply circuit is connected with:
and the voltage stabilizing capacitor is positioned outside the chip and is coupled with the first charge pump.
Preferably, a voltage input terminal of the power circuit is connected to a dc regulated power supply for providing the input voltage.
Preferably, the voltage input terminal of the power circuit is externally connected to the battery supply terminal, the inside of the power circuit is connected to ground through a series-connected buck converter, an inductor and a capacitor, and the connection node of the inductor and the capacitor supplies the input voltage to the first charge pump,
the inductor and the capacitor are distributed outside the power circuit integrated chip.
Preferably, the display panel is an active matrix organic light emitting diode panel.
In another aspect the present disclosure provides a display panel, comprising:
a load circuit for generating a driving current to drive the light emitting element; and
the power supply circuit as described above, which is configured to supply the positive power supply and the negative power supply to the aforementioned load circuit.
Preferably, the aforementioned load circuit includes:
a first transistor, a first end of which is connected with a data signal, a second end of which is connected with a positive voltage output end of the power supply circuit through a second transistor, and a control end of which is connected with an (n) th-stage scanning signal;
a third transistor, a fourth transistor, and the light emitting element, which are connected in series between a connection node of the first transistor and the second transistor and a negative voltage output terminal of the power supply circuit, wherein a control terminal of the fourth transistor and a control terminal of the second transistor are connected in common to receive an (n) th-stage enable signal;
the positive electrode of the storage capacitor is connected with the positive voltage output end of the power supply circuit, the negative electrode of the storage capacitor is connected with the first end of the fifth transistor, the control end of the fifth transistor is connected with an (n-1) th-stage scanning signal, and the second end of the fifth transistor receives low level; and
and a sixth transistor having a first terminal connected to the control terminal of the third transistor, a second terminal connected to the second terminal of the third transistor, and a control terminal connected to the control terminal of the first transistor.
Preferably, the display panel is an active matrix organic light emitting diode panel, and the light emitting device is a light emitting diode.
In another aspect, the present disclosure further provides a display device, including: a display panel as described above.
The beneficial effects of this disclosure are: the present disclosure provides a power supply circuit, a display panel and a display device, wherein the power supply circuit includes: the logic control unit is used for generating a clock signal according to the accessed control signal; a gate driver configured to generate a first driving signal and a second driving signal according to an input voltage and the clock signal; a first charge pump configured to operate in a plurality of modes in response to the first drive signal or the second drive signal to obtain different multiplication ratios of a node voltage output by the first charge pump to an input voltage; and the second charge pump is configured to respond to the first driving signal or the second driving signal and generate a negative voltage according to the partial node voltage, the first driving signal and/or the second driving signal are/is used for indicating the on/off of at least one transistor in the first charge pump and the second charge pump respectively, the second driving signal and the first driving signal are/is a reverse-phase signal, and then the partial node voltage and the negative voltage are processed respectively by the voltage stabilizer to correspondingly generate a positive power supply and a negative power supply required by a subsequent circuit. The power supply circuit adopts an inductance-free scheme of a charge pump structure, can flexibly select a power supply according to a specific application scene, not only eliminates the size problem of the inductance, improves the problem of electromagnetic interference (EMI), effectively reduces the total area of the power supply circuit, but also can reduce the cost of a power supply chip and a peripheral circuit while improving the working efficiency of the power supply.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a power circuit based on an inductor structure for an AMOLED panel disclosed in the prior art;
FIG. 2 is a schematic diagram illustrating a power circuit based on a capacitor structure for an AMOLED panel according to an embodiment of the present disclosure;
FIGS. 3a and 3b are schematic diagrams of two charge pumps in the power supply circuit of FIG. 2;
FIG. 3c is a schematic diagram of two charge pumps in the power supply circuit of FIG. 2 in another embodiment;
FIG. 4 is a schematic diagram illustrating a power circuit based on a capacitor structure for an AMOLED panel according to a second embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an active matrix organic light emitting diode panel according to a third embodiment of the disclosure;
FIG. 6 is a schematic diagram of a load circuit in the AMOLED panel shown in FIG. 5.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure is described in detail below with reference to the accompanying drawings.
The first embodiment is as follows:
fig. 2 shows a schematic structure diagram of a power circuit based on a capacitor structure for an active matrix organic light emitting diode panel according to a first embodiment of the present disclosure, fig. 3a and 3b show a schematic structure diagram of two charge pumps in the power circuit shown in fig. 2 in one implementation, and fig. 3c shows a schematic structure diagram of two charge pumps in the power circuit shown in fig. 2 in another implementation, respectively.
Referring to fig. 2 to 3b, a first embodiment of the present disclosure provides a power circuit 200 based on a capacitor structure for an active matrix organic light emitting diode panel, the power circuit 200 having a voltage input terminal VIN, a control signal input terminal CTRL, a positive voltage output terminal ELVDD, and a negative voltage output terminal ELVSS, the power circuit 200 further including: a logic control unit 201, a gate driver 210, a first charge pump 220 and a second charge pump 230,
the logic control unit 201 is connected to the aforementioned control signal input terminal CTRL, and configured to generate a clock signal Qc according to the accessed control signal CTRL;
the gate driver 210 is connected to the output terminal of the logic control unit 201, and the gate driver 210 is configured to generate a first driving signal Qm and a second driving signal Qn according to the input voltage Vin and the clock signal Qc;
the input terminal of the first charge pump 220 is respectively connected to the voltage input terminal VIN and the output terminal of the gate driver 210, and is configured to operate in multiple modes in response to the first driving signal Qm or the second driving signal Qn, so as to obtain different multiplication ratios of the node voltage VOP output by the first charge pump 220 and the input voltage VIN;
the input terminal of the second charge pump 230 is respectively connected to the output terminal of the gate driver 210 and the output terminal of the first charge pump 220, and is configured to generate a negative voltage VOL according to the node voltage VOP in response to the first driving signal Qm or the second driving signal Qn,
the first driving signal Qm and/or the second driving signal Qn are used to indicate the turn-on/turn-off of at least one of the transistors of the first charge pump 220 and the second charge pump 230, respectively, and the second driving signal Qn is an inverse signal of the first driving signal Qm.
Further, the power supply circuit 200 further includes: a positive voltage regulator 240 and a negative voltage regulator 250, wherein the positive voltage regulator 240 is connected to the output terminal of the first charge pump 220, and is configured to convert the node voltage VOP into a first output power Vdd and output the first output power Vdd to the positive voltage output terminal ELVDD; the negative voltage regulator 250 is connected to the output terminal of the second charge pump 230, and is used for converting the negative voltage VON into a second output power Vss, outputting the second output power Vss to the negative voltage output terminal ELVSS,
the first output power supply Vdd is a positive power supply with a first target voltage, and the second output power supply Vss is a negative power supply with a second target voltage.
In the present embodiment, the positive voltage regulator 240 and the negative voltage regulator 250 are both low dropout linear regulators (LDOs), for example, and it is known that the Low Dropout (LDO) linear regulators have the outstanding advantages of low cost, low noise, and small static current, and they require few external components and low loss. LDO (Low dropout) regulators with positive output voltage usually use a power transistor (also called pass device) as PNP, which transistor allows saturation, so the regulator can have a very low dropout voltage, usually around 200 mV; in contrast, the voltage drop of the conventional linear regulator using the NPN composite power transistor is about 2V. The negative output LDO uses an NPN as its pass device, which operates in a similar mode as the PNP device of the positive output LDO. A more recent development is the use of CMOS power transistors, which are capable of providing the lowest drop-out voltage.
Further, the first Charge Pump 220 is a Variable-rate Charge Pump (Ratio Variable Charge Pump), and a multiplication Ratio of the voltage VOP at the node of the output of the first Charge Pump 220 to the input voltage Vin is greater than 0 and less than or equal to 1, or greater than 1.
Further, referring to fig. 3a and 3b, in one embodiment, the first charge pump 220 has a first input terminal connected to the voltage input terminal VIN, a second input terminal connected to the gate driver 210, and a third input terminal, and a first output terminal providing the node-divided voltage VOP, and further includes: a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a capacitor C1, a capacitor C2, and a capacitor C3,
the transistor Q1, the transistor Q2, the transistor Q3 and the transistor Q4 are connected in series between the first input terminal and the ground, the control terminals of the transistor Q1 and the transistor Q3 are connected together as the second input terminal to receive the first driving signal Qm, the control terminals of the transistor Q2 and the transistor Q4 are connected together as the third input terminal to receive the second driving signal Qn;
a capacitor C3 having a first terminal connected to the connection node between the transistors Q1 and Q2, a second terminal connected to the connection node between the transistors Q3 and Q4, a connection node between the transistors Q2 and Q3 serving as the first input terminal, and a capacitor C1 connected between the first input terminal and ground; the capacitor C2 is connected between the first output terminal and the node connecting the transistor Q1 to ground.
Further, the second charge pump 230 has a fourth input terminal connected to the first output terminal, a fifth input terminal and a sixth input terminal connected to the gate driver 210, a second output terminal providing the negative voltage VOL, and further includes: a transistor Q5, a transistor Q6, a transistor Q7, a transistor Q8, a capacitor C4, a capacitor C5, and a capacitor C6,
the transistor Q5, the transistor Q6, the transistor Q7 and the transistor Q8 are connected in series between the fourth input terminal and the second output terminal, the control terminal of the transistor Q5 and the control terminal of the transistor Q7 are connected together as the fifth input terminal, the first driving signal Qm is connected, the control terminal of the transistor Q6 and the control terminal of the transistor Q8 are connected together as the sixth input terminal, the second driving signal Qn is connected, and the connection node of the transistor Q6 and the transistor Q7 is grounded;
the capacitor C4 is connected between the aforementioned fourth input terminal and the connection node of the transistor Q5 and ground;
a first end of the capacitor C5 is connected to the connection node between the transistor Q5 and the transistor Q6, and a second end is connected to the connection node between the transistor Q7 and the transistor Q8;
the capacitor C6 is connected between the aforementioned second output terminal and the connection node of the transistor Q8 and ground.
Further, any one of the Transistor Q1, the Transistor Q2, the Transistor Q3, the Transistor Q4, the Transistor Q5, the Transistor Q6, the Transistor Q7, and the Transistor Q8 is a Metal Oxide Semiconductor field Effect Transistor (MOS Transistor).
Furthermore, the transistor Q1, the transistor Q2, the transistor Q3, the transistor Q4, the transistor Q5, the transistor Q6, the transistor Q7 and the transistor Q8 are all N-type MOS transistors. Certainly, the disclosure is not limited thereto, the transistor Q1, the transistor Q2, the transistor Q3, the transistor Q4, the transistor Q5, the transistor Q6, the transistor Q7, and the transistor Q8 may also be all P-type MOS transistors or others, and their corresponding driving signals and circuit connection relations may be adaptively changed, which is not described herein again.
Further, referring to fig. 3c, in another embodiment, the aforementioned first charge pump 220 and the second charge pump 230 can be designed and simplified to be integrated into a circuit, and by multiplexing the gate driver 210 and reducing part of the voltage stabilizing capacitance, on one hand, the circuit density is increased, the wafer area required by the gate driver is reduced, thereby reducing the overall area of the circuit, and on the other hand, the corresponding power loss is also reduced. It is intended to connect the control terminals of the transistor Q1, the transistor Q3, the transistor Q5, and the transistor Q7 in common to the gate driver 210 to access the aforementioned first drive signal Qm, and to connect the control terminals of the transistor Q2, the transistor Q4, the transistor Q6, and the transistor Q8 in common to the gate driver 210 to access the aforementioned second drive signal Qn and to supply the node-divided voltage VOP to the subsequent positive voltage regulator 240 and the negative voltage VOL to the subsequent negative voltage regulator 250, respectively.
Specifically, the first charge pump 220 transfers the input voltage Vin to the intermediate node to generate the node voltage VOP by using its own input/output pass function (1-time mode); if the input voltage Vin is insufficient, the input voltage Vin is boosted to a certain multiplying factor (such as 1.33 times, 1.5 times, 2 times, etc.) by a variable multiplying factor charge pump (the first charge pump 220) to generate a node voltage VOP; alternatively, when the input voltage Vin is particularly high, the voltage drop function (e.g., 0.33 times, 0.5 times, etc.) of the variable charge pump (the first charge pump 220) can be used to output the voltage VOP. The sub-node voltage VOP is then stepped down by the LDO (positive voltage regulator 240) to generate a first output power Vdd, and the first output power Vdd is provided to a subsequent stage circuit through a positive voltage output terminal ELVDD. The circuit for generating the intermediate node voltage VON by the negative charge pump 130 and then generating the output negative voltage through the LDO 150 has been a large number of mature commercial products, and therefore will not be described in detail herein.
Further, the logic control unit 210, the first charge pump 220, the second charge pump 230, the positive voltage regulator 240, and the negative voltage regulator 250 of the power circuit 200 are integrated on a chip.
Further, the power supply circuit 200 is connected with: a voltage stabilizing capacitor Cm, which is located outside the chip and coupled to the first charge pump 220.
Furthermore, the voltage stabilizing capacitor Cm can be designed to be changed into 1 or more sub-capacitors according to different multiplying power requirements.
In the first embodiment shown in fig. 2, a dc regulated power supply is connected to the voltage input terminal VIN of the power circuit 200, and the dc regulated power supply is configured to provide the input voltage VIN, and specifically, the dc regulated power supply includes a buck converter 202 and an inductor Ls connected in series between the battery supply terminal VBAT and the voltage input terminal VIN.
Further, the display panel is an Active Matrix Organic Light Emitting Diode (AMOLED) panel.
Example two:
fig. 4 is a schematic structural diagram of a power circuit based on a capacitor structure for an active matrix organic light emitting diode panel according to a second embodiment of the disclosure.
In the second embodiment shown in fig. 4, the circuit structure and principle of the power circuit 200 are substantially the same as those of the first embodiment, except that: the power supply source of the input voltage Vin is different from the external dc regulator in the first embodiment, which is partially integrated on the chip of the power circuit 200 by using the dc regulator inside the power system (or chip), wherein the battery power supply terminal VBAT is connected outside the voltage input terminal Vin, the battery power supply terminal VBAT is connected inside the voltage input terminal Vin by the series connection of the buck converter 202, the inductor Ls and the capacitor Ci1, and the connection node of the inductor Ls and the capacitor Ci1 provides the input voltage Vin to the first charge pump 220,
the inductor Ls and the capacitor Ci1 are distributed outside the power circuit 200 integrated chip, the buck converter 202 is integrated inside the power chip, and a ground capacitor Ci2 is coupled to a connection node between the voltage input terminal VIN and the battery supply terminal VBAT.
The AMOLED power supply circuit in the prior art is based on a switch power supply framework of an inductor, and in the application occasions with compact sizes such as an intelligent bracelet and an intelligent watch, the size (area and height) of the inductor is too large, so that the circuit design and the product thickness design can be influenced, the client is indirectly influenced to be forced to thicken the height of the bracelet and the watch, and meanwhile, the inductor with a relatively small size but a large direct current impedance DCR is forced to be selected, so that the working efficiency is sacrificed, and the standby time is shortened.
The embodiment of the disclosure adopts an inductance-free scheme of a charge pump structure, directly eliminates the influence of the size of the inductance on the product design, and effectively reduces the total area of a power circuit;
in the first embodiment, an external direct-current stabilized power supply is used as an input power supply, so that the cost and the total area of a circuit can be saved, and the selection of different customers or application scenes is facilitated; price and efficiency advantages still exist even with the use of an external power source;
the voltage-doubling charge pump (the first charge pump 220) and the negative charge pump (the second charge pump) are completely symmetrical in structure, and nearly 100% of efficiency conversion can be obtained under the ideal condition without considering switching loss and driving loss. Compared with system power supplies with other structures, the efficiency loss on the LDO is the same, the efficiency of the stabilized voltage power supply with the Buck circuit outside is generally much higher than that of the Boost or Buck-Boost, so the overall efficiency of the stabilized voltage power supply is obviously superior to that of the power supplies with other structures, and the stabilized voltage power supply with the Buck circuit is externally or internally arranged, so that the efficiency of the power supply circuit 200 can be improved;
in addition, the power circuit 200 can eliminate the problem of electromagnetic interference EMI commonly existing in the power circuit with an inductive architecture, thereby further improving the working efficiency of the power supply and reducing the cost of the power chip and the peripheral circuit.
Example three:
fig. 5 shows a schematic structure diagram of an active matrix organic light emitting diode panel according to a third embodiment of the disclosure, and fig. 6 shows a schematic structure diagram of a load circuit in the active matrix organic light emitting diode panel shown in fig. 5.
Referring to fig. 5 and fig. 6, in another aspect, a second embodiment of the present disclosure also provides a display panel 10, where the display panel 10 includes:
a load circuit 300 for generating a driving current to drive the light emitting element DLE; and
as with the power supply circuit 200 described above, the power supply circuit 200 is configured to provide positive power and negative power to the aforementioned load circuit 300.
Referring to fig. 6, the load circuit 300 is a circuit product mature in the prior art, and is described schematically, for example, including: a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, and a transistor T6, and a storage capacitor Cst and a light emitting element DLE,
the first terminal of the transistor T1 is connected to the DATA signal DATA, the second terminal is connected to the positive voltage output terminal ELVDD of the power circuit 200 through the transistor T2, and is connected to the first output power source, and the control terminal is connected to the (n) th SCAN signal SCAN [ n ];
the transistor T3, the transistor T4, and the light emitting element DLE are connected in series between the connection node of the transistor T1 and the transistor T2 and the negative voltage output terminal ELVSS of the aforementioned power supply circuit 200, and the control terminal of the transistor T4 and the control terminal of the transistor T2 are commonly connected to the (n) th stage enable signal EM [ n ];
the storage capacitor Cst is connected in series with the transistor T5, the positive electrode of the storage capacitor Cst is connected to the positive voltage output terminal ELVDD of the power circuit 200, the negative electrode is connected to the first terminal of the transistor T5, the control terminal of the transistor T5 is connected to the (n-1) th SCAN signal SCAN [ n-1], and the second terminal receives the low level Vint;
the transistor T6 has a first terminal connected to the control terminal of the transistor T3, a second terminal connected to the second terminal of the transistor T3, and a control terminal connected to the control terminal of the transistor T1.
Further, the display panel 10 is an active matrix organic light emitting diode panel (AMOLED), and the light emitting element DLE is a light emitting diode.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, and the transistor T6 are all thin film transistors, specifically, the transistor T3 is a driving thin film transistor (Driver TFT), and the transistor T1 is a switching thin film transistor (Switch TFT). The remaining transistor combinations are used as a compensation circuit to cooperatively compensate for a change in the driving current for driving the light emitting element DLE caused by a shift in the threshold voltage of the driving tft T3, and to stabilize the potential of the gate of the driving tft T3, so as to stabilize the driving current for driving the light emitting element DLE generated by the load circuit 300, and the stabilization of the driving current for driving the light emitting element DLE does not affect the light emitting brightness of the light emitting element DLE, thereby improving the image quality of the display panel to which the load circuit 300 is applied.
In this embodiment, the first terminal is a source and the corresponding second terminal is a drain. In another embodiment, the first end may be a drain, and the corresponding second end may be a source.
Example four:
on the other hand, the present disclosure also provides a display device (not shown) including the display panel 10 as described in the foregoing embodiments, and more specifically, the display panel 10 is an active matrix organic light emitting diode panel (AMOLED).
To sum up, the power circuit 200, the display panel 10 and the display device (not shown) provided in the embodiment of the present disclosure, wherein the power circuit 200 has a voltage input terminal VIN, a control signal input terminal CTRL, a positive voltage output terminal ELVDD and a negative voltage output terminal ELVSS, and a logic control unit 201 in the power circuit 200 is utilized to generate a clock signal Qc according to an accessed control signal CTRL; generating a first driving signal Qm and a second driving signal Qn by using the gate driver 210 according to the input voltage Vin and the clock signal Qc; the first charge pump 220 is then used to respond to the first driving signal Qm or the second driving signal Qn to operate in multiple modes, so as to output the node voltage VOP with different multiplication ratios from the input voltage Vin; then, the second charge pump 230 generates a negative voltage VON according to the node voltage VOP in response to the first driving signal Qm or the second driving signal Qn, and then the voltage regulators (the positive voltage regulator 240 and the negative voltage regulator 250) respectively process the node voltage VOP and the negative voltage VON to correspondingly generate the positive power Vdd and the negative power Vss required by the subsequent circuits, wherein the first driving signal Qm and/or the second driving signal Qn are used to respectively indicate the turn-on and turn-off of at least one transistor of the first charge pump 220 and the second charge pump 230, and the second driving signal Qn and the first driving signal Qm are inverse signals. The power supply circuit 200 adopts an inductance-free scheme of a charge pump structure, so that the problem of the size of an inductor can be eliminated, the problem of electromagnetic interference (EMI) is solved, and the area of a power supply chip is effectively reduced;
in the first embodiment, an external direct-current stabilized power supply is used as an input power supply, so that the cost and the total area of a circuit can be saved, and the selection of different customers or application scenes is facilitated; price and efficiency advantages still exist even with the use of an external power source;
the voltage-doubling charge pump (the first charge pump 220) and the negative charge pump (the second charge pump) are completely symmetrical in structure, and nearly 100% efficiency conversion can be obtained under the ideal condition without considering switching loss and driving loss. Compared with system power supplies with other structures, the efficiency loss on the LDO is the same, the efficiency of the stabilized voltage power supply with the Buck circuit outside is generally much higher than that of the Boost or Buck-Boost, so the overall efficiency of the stabilized voltage power supply is obviously superior to that of the power supplies with other structures, and the stabilized voltage power supply with the Buck circuit is externally or internally arranged, so that the efficiency of the power supply circuit 200 can be improved;
in addition, the power circuit 200 can eliminate the problem of electromagnetic interference EMI commonly existing in the power circuit with an inductive architecture, and reduce the cost of the power chip and the peripheral circuit while further improving the working efficiency of the power supply.
Therefore, the power supply circuit, the display panel and the display device provided with the power supply circuit have high practicability and compatibility, and are suitable for popularization and application.
It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (15)
1. A power supply circuit for a display panel, the power supply circuit having a voltage input terminal, a control signal input terminal, a positive voltage output terminal and a negative voltage output terminal, wherein the power supply circuit further comprises:
the logic control unit is connected with the control signal input end and used for generating a clock signal according to the accessed control signal;
a gate driver connected to an output of the logic control unit, the gate driver configured to generate a first driving signal and a second driving signal according to an input voltage and the clock signal;
a first charge pump having an input connected to the voltage input and the output of the gate driver, respectively, configured to operate in multiple modes in response to the first or second drive signals to obtain a different multiplication ratio of a node voltage output by the first charge pump to an input voltage;
a second charge pump having an input terminal connected to the output terminal of the gate driver and the output terminal of the first charge pump, respectively, and configured to generate a negative voltage according to the node voltage in response to the first driving signal or the second driving signal,
the first driving signal and/or the second driving signal are used for indicating the on/off of at least one transistor in the first charge pump and the second charge pump respectively, and the second driving signal and the first driving signal are opposite phase signals.
2. The power supply circuit of claim 1, further comprising:
the positive voltage stabilizer is connected with the output end of the first charge pump and used for converting the sub-node voltage into a first output power supply and outputting the first output power supply to the positive voltage output end;
a negative voltage stabilizer connected with the output end of the second charge pump and used for converting the negative voltage into a second output power supply and outputting the second output power supply to the negative voltage output end,
the first output power supply is a positive power supply with a first target voltage, and the second output power supply is a negative power supply with a second target voltage.
3. The power supply circuit according to claim 2, wherein a multiplication ratio of a division node voltage to an input voltage at which the first charge pump output is obtained is greater than 0 and less than or equal to 1, or greater than 1.
4. The power supply circuit of claim 3, wherein the first charge pump has a first input connected to the voltage input, a second input and a third input connected to the gate driver, a first output providing the split node voltage, and further comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor connected in series between the first input terminal and ground, wherein the first transistor and a control terminal of the third transistor are connected in common to serve as the second input terminal and receive the first driving signal, and the second transistor and a control terminal of the fourth transistor are connected in common to serve as the third input terminal and receive the second driving signal;
a first capacitor having a first terminal connected to a connection node between the first transistor and the second transistor and a second terminal connected to a connection node between the third transistor and the fourth transistor;
a second capacitor, a connection node of the second transistor and the third transistor serving as the first input terminal, the second capacitor being connected between the first input terminal and ground;
a third capacitor connected between the first output terminal and a connection node of the first transistor and ground.
5. The power supply circuit of claim 4, wherein the second charge pump has a fourth input connected to the first output, a fifth input and a sixth input connected to the gate driver, a second output providing the negative voltage, and further comprising:
a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series between the fourth input terminal and the second output terminal, wherein the control terminal of the fifth transistor and the control terminal of the seventh transistor are connected together to serve as the fifth input terminal, the first driving signal is input, the control terminal of the sixth transistor and the control terminal of the eighth transistor are connected together to serve as the sixth input terminal, the second driving signal is input, and a connection node of the sixth transistor and the seventh transistor is grounded;
a fourth capacitor, a first end of which is connected to a connection node between the fifth transistor and the sixth transistor, and a second end of which is connected to a connection node between the seventh transistor and the eighth transistor;
a fifth capacitor connected between the second output terminal and a connection node of the eighth transistor and ground.
6. The power supply circuit according to claim 5, wherein any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a metal oxide semiconductor field effect transistor.
7. The power supply circuit of claim 5, wherein the power supply circuit is integrated on one chip.
8. The power supply circuit of claim 7, wherein the power supply circuit has connected thereto:
and the voltage stabilizing capacitor is positioned outside the chip and is coupled with the first charge pump.
9. The power supply circuit of claim 8, wherein a regulated dc power supply is coupled to the voltage input of the power supply circuit and is configured to provide the input voltage.
10. The power supply circuit of claim 8, wherein a voltage input terminal of the power supply circuit is externally connected to a battery supply terminal, internally connected to ground through a series connection of a buck converter, an inductor and a capacitor, and a connection node of the inductor and the capacitor provides the input voltage to the first charge pump,
the inductor and the capacitor are distributed outside the power supply circuit integrated chip.
11. The power supply circuit according to claim 9 or 10, wherein the display panel is an active matrix organic light emitting diode panel.
12. A display panel, comprising:
a load circuit for generating a driving current to drive the light emitting element; and
a power supply circuit as claimed in any one of claims 1 to 11, configured to provide positive and negative power to the load circuit.
13. The display panel of claim 12, wherein the load circuit comprises:
a first end of the first transistor is connected with a data signal, a second end of the first transistor is connected with a positive voltage output end of the power supply circuit through a second transistor, and a control end of the first transistor is connected with an (n) th-stage scanning signal;
a third transistor, a fourth transistor, and the light emitting element, which are connected in series between a connection node of the first transistor and the second transistor and a negative voltage output terminal of the power supply circuit, wherein a control terminal of the fourth transistor and a control terminal of the second transistor are connected in common to access an (n) th stage enable signal;
the positive electrode of the storage capacitor is connected with the positive voltage output end of the power supply circuit, the negative electrode of the storage capacitor is connected with the first end of the fifth transistor, the control end of the fifth transistor is connected with an (n-1) th-stage scanning signal, and the second end of the fifth transistor receives a low level; and
and a first end of the sixth transistor is connected with the control end of the third transistor, a second end of the sixth transistor is connected with the second end of the third transistor, and the control end of the sixth transistor is connected with the control end of the first transistor.
14. The display panel of claim 13, wherein the display panel is an active matrix organic light emitting diode panel and the light emitting elements are light emitting diodes.
15. A display device, comprising: a display panel according to any one of claims 12 to 14.
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Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050112841A (en) * | 2004-05-28 | 2005-12-01 | 삼성에스디아이 주식회사 | Charge pumping circuit, power supply and display device using the same |
| CN1794334A (en) * | 2004-12-21 | 2006-06-28 | 株式会社瑞萨科技 | Semiconductor integrated circuit for liquid crystal display driver |
| CN101088211A (en) * | 2004-12-28 | 2007-12-12 | 罗姆股份有限公司 | Power supply circuit, charge pump circuit, and portable appliance therewith |
| US20090108888A1 (en) * | 2007-10-30 | 2009-04-30 | Gebara Fadi H | Switched-Capacitor Charge Pumps |
| CN102290983A (en) * | 2011-06-16 | 2011-12-21 | 北京大学 | Charge pump |
| JP2012182871A (en) * | 2011-02-28 | 2012-09-20 | Panasonic Corp | Charge pump circuit and switching device |
| KR20140079044A (en) * | 2012-12-18 | 2014-06-26 | 엘지디스플레이 주식회사 | Power supply and flat panel display using the same |
| KR20140098367A (en) * | 2013-01-31 | 2014-08-08 | 엘지디스플레이 주식회사 | Power supply and flat panel display using the same |
| CN106057138A (en) * | 2015-04-01 | 2016-10-26 | 矽创电子股份有限公司 | Power Circuit, Gate Driving Circuit and Display Module |
| CN106817021A (en) * | 2015-12-01 | 2017-06-09 | 台湾积体电路制造股份有限公司 | Charge pump circuit |
| KR20180031467A (en) * | 2016-09-20 | 2018-03-28 | 삼성전자주식회사 | Reconfigurable Bipolar Output Charge Pump Circuit and Integrated Circuit including the same |
| CN108231027A (en) * | 2018-01-15 | 2018-06-29 | 南京熊猫电子制造有限公司 | A kind of liquid crystal display of low-power consumption |
| JP2019154092A (en) * | 2018-02-28 | 2019-09-12 | シャープ株式会社 | Internal voltage generating circuit |
| CN209642547U (en) * | 2019-02-27 | 2019-11-15 | 刘鸿睿 | A kind of charge pump conversion circuit |
| DE112018006926T5 (en) * | 2018-01-23 | 2020-10-08 | Shindengen Electric Manufacturing Co., Ltd. | CONTROL DEVICE AND CONTROL METHOD FOR CONTROL DEVICE |
| CN111969845A (en) * | 2020-09-04 | 2020-11-20 | 广东工业大学 | Mixed type reconfigurable charge pump circuit |
-
2021
- 2021-02-02 CN CN202110145442.5A patent/CN114844348B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050112841A (en) * | 2004-05-28 | 2005-12-01 | 삼성에스디아이 주식회사 | Charge pumping circuit, power supply and display device using the same |
| CN1794334A (en) * | 2004-12-21 | 2006-06-28 | 株式会社瑞萨科技 | Semiconductor integrated circuit for liquid crystal display driver |
| CN101088211A (en) * | 2004-12-28 | 2007-12-12 | 罗姆股份有限公司 | Power supply circuit, charge pump circuit, and portable appliance therewith |
| US20090108888A1 (en) * | 2007-10-30 | 2009-04-30 | Gebara Fadi H | Switched-Capacitor Charge Pumps |
| JP2012182871A (en) * | 2011-02-28 | 2012-09-20 | Panasonic Corp | Charge pump circuit and switching device |
| CN102290983A (en) * | 2011-06-16 | 2011-12-21 | 北京大学 | Charge pump |
| KR20140079044A (en) * | 2012-12-18 | 2014-06-26 | 엘지디스플레이 주식회사 | Power supply and flat panel display using the same |
| KR20140098367A (en) * | 2013-01-31 | 2014-08-08 | 엘지디스플레이 주식회사 | Power supply and flat panel display using the same |
| CN106057138A (en) * | 2015-04-01 | 2016-10-26 | 矽创电子股份有限公司 | Power Circuit, Gate Driving Circuit and Display Module |
| CN106817021A (en) * | 2015-12-01 | 2017-06-09 | 台湾积体电路制造股份有限公司 | Charge pump circuit |
| KR20180031467A (en) * | 2016-09-20 | 2018-03-28 | 삼성전자주식회사 | Reconfigurable Bipolar Output Charge Pump Circuit and Integrated Circuit including the same |
| CN108231027A (en) * | 2018-01-15 | 2018-06-29 | 南京熊猫电子制造有限公司 | A kind of liquid crystal display of low-power consumption |
| DE112018006926T5 (en) * | 2018-01-23 | 2020-10-08 | Shindengen Electric Manufacturing Co., Ltd. | CONTROL DEVICE AND CONTROL METHOD FOR CONTROL DEVICE |
| JP2019154092A (en) * | 2018-02-28 | 2019-09-12 | シャープ株式会社 | Internal voltage generating circuit |
| CN209642547U (en) * | 2019-02-27 | 2019-11-15 | 刘鸿睿 | A kind of charge pump conversion circuit |
| CN111969845A (en) * | 2020-09-04 | 2020-11-20 | 广东工业大学 | Mixed type reconfigurable charge pump circuit |
Non-Patent Citations (1)
| Title |
|---|
| 郑然;魏廷存;王佳;高德远;: "TFT-LCD驱动芯片内置电荷泵频率及开关网络优化", 液晶与显示, no. 02, 15 April 2009 (2009-04-15) * |
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