CN209642547U

CN209642547U - A kind of charge pump conversion circuit

Info

Publication number: CN209642547U
Application number: CN201920247514.5U
Authority: CN
Inventors: 刘鸿睿
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-02-27
Filing date: 2019-02-27
Publication date: 2019-11-15
Anticipated expiration: 2029-02-27

Abstract

A kind of charge pump conversion circuit belongs to pressure regulation conversion circuit technical field more particularly to a kind of charge pump conversion circuit.The utility model provides a kind of energy loss a kind of small charge pump conversion circuit.The utility model includes multiple charge pumps being sequentially connected in series, and is connected between structural feature adjacent charge pump by output port selection control switch；The charge pump includes the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube, and control switch includes third PMOS tube, third NMOS tube, the 4th PMOS tube and the 4th NMOS tube；The source electrode of first PMOS tube is connected with input anode, first capacitor one end, third PMOS tube source electrode respectively, the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube grid be connected with charge pump switches signal input part.

Description

A kind of charge pump conversion circuit

Technical field

The utility model belongs to pressure regulation conversion circuit technical field more particularly to a kind of charge pump conversion circuit.

Background technique

Traditional Switching Power Supply must use inductance, and inductance have the shortcomings that high line loss, strong jamming, frangible, heavy.

Summary of the invention

The utility model provides a kind of a kind of the hard of the small charge pump conversion circuit of energy loss aiming at the above problem Part basis.

To achieve the above object, the utility model adopts the following technical solution, and the utility model includes multiple is sequentially connected in series Charge pump, select control switch connected by output port between structural feature adjacent charge pump；

The charge pump includes the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube, control switch packet Include the 3rd PMOS pipe, third NMOS tube, the 4th PMOS tube and the 4th NMOS tube；

The source electrode of first PMOS tube is connected with input anode, first capacitor one end, third PMOS tube source electrode respectively, and first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube grid be connected with charge pump switches signal input part, The drain electrode of one PMOS tube is connected with the drain electrode of the first NMOS tube, third capacitor one end respectively, the source electrode of the first NMOS tube respectively with The first capacitor other end, second capacitor one end, the source electrode of the second PMOS tube, the source electrode of third NMOS tube, the 4th PMOS tube source Extremely it is connected；

The drain electrode of second PMOS tube is connected with the drain electrode of third the capacitor other end, the second NMOS tube respectively, the second NMOS tube Source electrode be connected respectively with input cathode, the second capacitor other end, the 4th NMOS tube source electrode, the 4th NMOS tube drain electrode respectively with Negative pole of output end, the 4th PMOS tube drain electrode be connected, third PMOS tube drain electrode respectively with third NMOS tube drain electrode, output head anode phase Even；

The grid and digital quantity input port phase of third PMOS tube, third NMOS tube, the 4th PMOS tube and the 4th NMOS tube Even.

A kind of charge pump conversion circuit, including multiple charge pumps being sequentially connected in series, it is characterised in that between adjacent charge pump Control switch is selected to be connected by output port；

The number of the charge pump is 8, and first order charge pump includes NMOS tube T1~T8, T1 drain electrode respectively with input E1 Anode, the input terminal of three-terminal regulator chip U14, the one end capacitor C53, the one end capacitor C9, T5 drain electrode, the one end capacitor C10 are connected；

Input E1 cathode respectively with ground wire, the C53 other end, the ground terminal of three-terminal regulator chip U14, the one end capacitor C54, T4 Source electrode, the one end resistance R3, the one end resistance R4, T8 source electrode, the one end capacitor C11 are connected；

The output end of U14 respectively with the C54 other end, the input terminal of three-terminal regulator chip U13, diode D5 anode, two poles Pipe D4 anode, diode D3 anode are connected；

The ground terminal of U13 is grounded, the output end of the U13 VCCI1 with the one end capacitor C12, UCC21521ADW chip U1 respectively End is connected, and capacitor C12 other end ground connection, 3 feet that the INA of U1 terminates 8051 chip U12 are connected, and the INB of U1 terminates 8051 chips 4 feet of U12 are connected, and the end the GND ground connection of U1, the end EN, the end DT, the end VCCI2 of U1 is connected；

The end VDDA of U1 respectively with the one end resistance R1, the source electrode of T1, the drain electrode of T2, the one end capacitor C1, diode D4 cathode It is connected；

T2 source electrode is connected with D3 cathode, T3 drain electrode, T6 source electrode, T7 drain electrode, the one end capacitor C10, the one end capacitor C11 respectively；

T3 source electrode is connected with the end VSSA of the C1 other end, T4 drain electrode, U1 respectively；

The end OUTA of U1 is connected with the one end capacitor C5, T3 grid, the one end capacitor C3 respectively, the capacitor C3 other end respectively with T1 Grid, the resistance R1 other end, diode D6 anode are connected, and D6 cathode is connected with the C9 other end, diode D7 cathode respectively, D7 sun Pole is connected with the one end resistance R2, the one end capacitor C4, T5 grid respectively, the R2 other end respectively with D5 cathode, T5 source electrode, T6 drain electrode, The one end capacitor C2, the end VDDB of U1 are connected, and the C2 other end is connected with the end VSSB of T7 source electrode, T8 drain electrode, U1 respectively；

The end OUTB of U1 is connected with the one end capacitor C6, T7 grid, the capacitor C4 other end respectively, T8 grid respectively with resistance R4 The other end, the C5 other end are connected, and the C6 other end is connected with the resistance R3 other end, T4 grid respectively；

T2 grid connects T7 grid, and T6 grid connects T3 grid.

As a preferred embodiment, the control signal input mouth of control switch and charge pump switches described in the utility model It is connected with the control signal output mouth of controller.

As another preferred embodiment, the control signal input mouth of control switch described in the utility model passes through driving electricity Road is connected with the control signal output mouth of controller.

As another preferred embodiment, charge pump described in the utility model generates the voltage at two times of relationships；Control switch For selecting to connect rear stage charge pump in any two ports of previous stage charge pump；Controller controls these into two times of relationships Voltage syntagmatic.

As another preferred embodiment, the input that controller described in the utility model measures entire charge pump regulating circuit is defeated Voltage, electric current out.

As another preferred embodiment, controller described in the utility model generates the control signal of charge pump gate driving.

As another preferred embodiment, controller described in the utility model and peripheral components, external device communication.

As another preferred embodiment, controller described in the utility model is single-chip microcontroller.

As another preferred embodiment, charge pump described in the utility model is two partial pressure charge pumps.

As another preferred embodiment, charge pump described in the utility model includes the two partial pressure bridge arms in left and right, divides bridge arm It is connected with input terminal with control switch both ends, divides bridge arm and control switch includes multiple concatenated switching tubes, divide bridge arm Central node be connected with the central node of control switch.

As another preferred embodiment, left partial pressure bridge arm described in the utility model includes NMOS tube T1, T2, T3, T4, the right side point Breaking the bridge arm includes NMOS pipe T5, T6, T7, T8, and control switch includes NMOS tube T9, T10, T11, T12；

The drain electrode of T4 is connected with input terminal VIN+, the one end capacitor C2, the drain electrode of T8, the drain electrode of T12 respectively, the source electrode point of T4 Be not connected with the drain electrode of T3, the one end capacitor C3, the source electrode of T3 respectively with the capacitor C2 other end, the one end capacitor C1, the source electrode of T7, T6 Drain electrode, the drain electrode of source electrode, T10 of T11, the drain electrode of T2 be connected, the source electrode of the T2 drain electrode phase with the capacitor C3 other end, T1 respectively Even, the source electrode of T1 is connected with the source electrode of the capacitor C1 other end, the source electrode of input terminal VIN-, T5, T9 respectively；

The drain electrode of T5 is connected with the source electrode of T6, the one end capacitor C4 respectively, the capacitor C4 other end respectively with the source electrode of T8, T7 Drain electrode is connected；

The drain electrode of T9 is connected with the source electrode of T10, output end VOUT- respectively, T11 drain electrode respectively with the source electrode of T12, output VOUT+ is held to be connected.

As another preferred embodiment, T1, T3 conducting described in the utility model, T2, T4 cut-off are a kind of working condition； T1, T3 cut-off, T2, T4 conducting are another working condition, and two states are constantly switched fast, and the time respectively accounts for 50%；Two The conducting of bridge arm corresponding position NMOS tube, off state are opposite (such as T4 conducting, T8 cut-off).

As another preferred embodiment, control signal described in the utility model is multidigit binary control signal.

As another preferred embodiment, the digit of multidigit binary control signal described in the utility model and of charge pump Number is identical.

As another preferred embodiment, the number of charge pump described in the utility model is 8 or 16.

As another preferred embodiment, controller described in the utility model uses pid algorithm, and output valve is converted into integer change I/O mouth after amount directly by controller is output to control switch.

As another preferred embodiment, the input terminal of circuit described in the utility model adds a gating switch, which opens It closes and is disconnected before impulse noise generation, impulse noise recloses after disappearing.

As another preferred embodiment, charge pump described in the utility model is eight.

As another preferred embodiment, the source electrode and the 5th of the first NMOS tube of the utility model afterbody charge pump The source electrode of PMOS tube is connected, and the drain electrode of the 5th PMOS tube is connected with the drain electrode of the anode of output buffer, the 5th NMOS tube respectively, The source electrode of 5th NMOS tube connects the source electrode of the second NMOS tube of afterbody charge pump；The grid of 5th PMOS tube meets Bit0PMOS The grid of control terminal, the 5th NMOS tube connects Bit0NMOS control terminal；The negative terminal of buffer connects the output end of buffer.

As another preferred embodiment, the utility model is not when having impulse noise, the 5th PMOS tube and the 5th NMOS tube Control terminal level be consistent, for DAC input digital quantity lowest order；And when there is impulse noise, the control of the 5th PMOS tube For end control level to be high, the 5th NMOS tube control terminal control level is low, output and previous circuit disconnection, isolation impulse noise.

As another preferred embodiment, the high level of the utility model switch control signal is at least higher than power input voltage The threshold voltage (0.7V) of a NMOS out, the threshold voltage (0.7V) of a low level out PMOS at least lower than ground voltage.

As another preferred embodiment, NMOS tube described in the utility model uses CSD16570Q5B type NMOS tube.

As another preferred embodiment, the utility model circuit turns off T2, T6 when just powering on, and drives to the grid of T3, T7 Dynamic signal applies oscillator signal, after a period of time, circuit stability reuses opposite after determining that the upper tube of upside half-bridge is controllable Mode, it is ensured that the down tube of downside half-bridge is controllable, later just enter normal state of a control.

Control switch as another preferred embodiment, between the utility model first order charge pump and second level charge pump Including NMOS tube T9~T12, T9 drain electrode is connected with the end VDDA of input E1 anode, UCC21521ADW chip U2 respectively, T9 grid Pole is connected with the one end R16, the one end resistance R8, the one end capacitor C16 respectively, another termination NPN triode T16 base stage of R16, T16 collection Electrode is connected with the one end resistance R18, the one end resistance R17 respectively, the resistance R17 other end respectively with diode D7 cathode, PNP tri- Pole pipe T13 emitter is connected, and T13 base stage connects the R18 other end, the T13 collector connecting resistance R8 other end；

T9 source electrode respectively with the emitter of T16, T10 drain electrode, U2 the end VSSB be connected, T10 grid respectively with the OUTA of U2 End, the one end capacitor C14 be connected, T10 source electrode respectively with T11 drain electrode, the emitter of PNP triode T14, the one end resistance R13, U2 The end VSSA, NMOS tube T6 source electrode be connected, T11 grid is connected with the end OUTB of the capacitor C16 other end, U2 respectively, T11 source electrode It is connected respectively with the end VSSB of T12 drain electrode, U2；

T12 grid is connected with the one end resistance R10, the one end resistance R12, the one end resistance R23, the C14 other end respectively, and R10 is another One termination T14 collector, the one end T14 base stage connecting resistance R14, the resistance R14 other end respectively with the R13 other end, NPN triode T15 collector is connected, and T15 base stage connects the R12 other end, and T15 emitter is connected with the R23 other end, T12 source electrode, ground wire respectively；U2 The end INA, INB corresponding with 17 feet of 8051 chip U12,28 feet be respectively connected；The VCCI1 of U2 terminates LM7805CT chip U13 Output end, the end the GND ground connection of U2, the end EN, DT, VCCI2 of U2 is connected.

As another preferred embodiment, the utility model second level charge pump includes NMOS tube T17~T24, T17 drain electrode point Do not drain with the one end resistance R22, the one end capacitor C28, diode D13 anode, the one end capacitor C24, diode D11 anode, T21 phase Even, another termination PNP triode T13 collector of R22；T17 grid respectively with the one end resistance R9, diode D10 cathode, capacitor The one end C15 be connected, T17 source electrode respectively with the R9 other end, D10 anode, the one end capacitor C51, T18 drain electrode, the one end capacitor C22 phase Even, T18 grid is connected with the end OUTB of T20 grid, the one end capacitor C17, T23 grid, UCC21521ADW chip U3 respectively, T18 source electrode is connected with the C28 other end, the one end capacitor C13, T19 drain electrode, T22 source electrode, T23 drain electrode respectively；

T19 grid is connected with the capacitor C15 other end, the end OUTA of U3, T24 grid, T22 grid respectively, T19 source electrode difference With the C22 other end, T20 drain electrode be connected, T20 source electrode respectively with NMOS tube T12 drain electrode, the end VSSA, VSSB of U3, the C13 other end, T24 source electrode is connected；

The C51 other end is connected with D13 cathode, D1 anode respectively, D1 cathode respectively with the C24 other end, diode D2 cathode, The one end resistance R7 is connected, and D11 cathode is connected with D2 anode, the one end capacitor C52 respectively, and the C52 other end is positive with diode D12 respectively Pole, the one end resistance R19, T21 source electrode, the one end capacitor C23 are connected, and T21 grid is another with D12 cathode, the R19 other end, C17 respectively End is connected；The C23 other end is connected with T23 source electrode, T24 drain electrode respectively；

The end INA, INB of U3 is corresponding connected with 3, the 4 of 8051 chip U12 respectively.

Control switch as another preferred embodiment, between the utility model second level charge pump and third level charge pump Including NMOS tube T25~T28, T25 drain electrode respectively with NMOS tube T21 drain electrode, diode D9 anode is connected, D9 cathode respectively with PNP triode T29 collector, the one end capacitor C25, the end VDDB of VDDA, U5 of UCC21521ADW chip U5, UCC21521ADW The end VDDB of chip U4 is connected, and T29 emitter connects the cathode of diode D2, T29 base stage respectively with resistance R7, the one end resistance R20 It is connected；

T25 grid is connected with the end OUTB of T27 grid, U4 respectively, and T25 source electrode connects T26 drain electrode, and T26 grid is respectively and surely Pressure pipe D8 anode, T28 grid, the end OUTA of U4 are connected, and D8 cathode connects the R20 other end；T26 source electrode respectively with the source NMOS tube T22 Pole, T27 drain electrode are connected, and T27 source electrode is connected with the C25 other end, the end VSSB of U4, T28 drain electrode respectively, and T28 source electrode connects NMOS tube T24 source electrode；

The end INA, INB of U4 is corresponding connected with 16, the 27 of 8051 chip U12 respectively.

As another preferred embodiment, the utility model third~eight grade charge pump includes the first~eight NMOS tube, and first NMOS tube (T30, by taking third level charge pump as an example) drain electrode drains with the one end first capacitor (C29), the 5th NMOS tube (T34) respectively It is connected, the first NMOS tube source electrode is connected with the one end the second capacitor (C21), the second NMOS tube (T31) drain electrode respectively；

The second capacitor other end is connected with third NMOS tube (T32) source electrode, the drain electrode of the 4th NMOS tube (T33) respectively, and second NMOS tube source electrode respectively with the first capacitor other end, the one end third capacitor (C18), third NMOS tube drain electrode, the 6th NMOS tube (T35) source electrode, the 7th NMOS pipe (T36) drain electrode be connected, the third capacitor other end respectively with the 4th NMOS tube source electrode, the 8th NMOS tube source electrode is connected；

5th NMOS tube source electrode is connected with the drain electrode of the 6th NMOS tube, the 4th one end capacitor (C26) respectively, and the 4th capacitor is another End is connected with the 7th NMOS tube source electrode, the drain electrode of the 8th NMOS tube respectively；

First NMOS tube grid is connected with third NMOS tube grid, the 6th NMOS tube grid, the 8th NMOS tube grid respectively, Second NMOS tube grid is connected with the 4th NMOS tube grid, the 5th NMOS tube grid, the 7th NMOS tube grid respectively.

Control switch as another preferred embodiment, between the utility model third~eight grade charge pump adjacent charge pump Including the 9th NMOS tube~the 12nd NMOS tube (T38, T39, T40, T41, between third level charge pump and fourth stage charge pump Control switch for), the drain electrode of the 9th NMOS pipe drains with the 5th NMOS tube of prime charge pump to be connected, the 9th NMOS tube source Pole respectively with the first NMOS tube of rear class charge pump drain electrode, the tenth NMOS tube drain electrode is connected, the tenth NMOS tube source electrode respectively with it is preceding Grade charge pump the 6th NMOS tube source electrode, the 11st NMOS tube drain electrode be connected, the 11st NMOS tube source electrode respectively with rear class charge 4th NMOS tube source electrode of pump, the drain electrode of the 12nd NMOS tube are connected.

Control switch as another preferred embodiment, between the utility model third level charge pump and fourth stage charge pump The nine, the 11 NMOS tube grids be connected with the port OUTB of UCC21521ADW chip U6, the ten, the 12 NMOS tube grids with The port OUTA of U6 is connected；

Nine, the 11 NMOS tube grids of the control switch between fourth stage charge pump and level V charge pump with The port OUTB of UCC21521ADW chip U7 is connected, and the ten, the 12 NMOS tube grids are connected with the port OUTA of U7；

Nine, the 11 NMOS tube grids of the control switch between level V charge pump and the 6th grade of charge pump with The port OUTB of UCC21521ADW chip U8 is connected, and the ten, the 12 NMOS tube grids are connected with the port OUTA of U8；

Nine, the 11 NMOS tube grids of the control switch between the 6th grade of charge pump and the 7th grade of charge pump with The port OUTB of UCC21521ADW chip U9 is connected, and the ten, the 12 NMOS tube grids are connected with the port OUTA of U9；

Nine, the 11 NMOS tube grids of the control switch between the 7th grade of charge pump and the 8th grade of charge pump with The port OUTB of UCC21521ADW chip U10 is connected, and the ten, the 12 NMOS tube grids are connected with the port OUTA of U10；

The end VDDA, the end VDDB of U6~U10 is connected, and the end VSSA, the end VSSB of U6~U10 is connected, the end INA, the end INB of U6 It is corresponding with 15,26 feet of 8051 chip U12 respectively to be connected；

The end INA, the end INB of U7 is corresponding with 14,25 feet of U12 respectively to be connected；

The end INA, the end INB of U8 is corresponding with 13,24 feet of U12 respectively to be connected；

The end INA, the end INB of U9 is corresponding with 12,23 feet of U12 respectively to be connected；

The end INA, the end INB of U10 is corresponding with 11,22 feet of U12 respectively to be connected.

As another preferred embodiment, the 6th NMOS tube source electrode and NMOS tube T100 of the 8th grade of charge pump of the utility model Drain electrode is connected, and T100 source electrode is connected with NMOS tube T101 drain electrode, the one end capacitor C56 respectively, and T101 source electrode connects the 8th grade of charge pump The 8th NMOS tube source electrode, the capacitor C56 other end ground connection；

T100 grid connects the end OUTB of UCC21521ADW chip U11, and T101 grid connects the end OUTA of U11, U11 and The end VDDA, the end VDDB of UCC21521ADW chip U10 is connected, and U11 is connected with the end VSSA of U10, the end VSSB；

The end INA, the end INB of U11 is corresponding with 10,21 feet of U12 respectively to be connected.

As another preferred embodiment, the first NMOS tube of charge pump at different levels in the utility model third~eight grade charge pump Grid is connected, and the 5th NMOS tube grid of charge pumps at different levels is connected, the first NMOS tube grid respectively with PMOS tube T105 drain electrode, NMOS tube T103 drain electrode be connected, T105 source electrode respectively with the end VDDA of UCC21521ADW chip U5, the one end resistance R21, PMOS Pipe T104 source electrode, the one end resistance R15, UCC21521ADW chip U6 the end VDDA be connected, the resistance R15 other end respectively with capacitor The one end C27, T105 grid are connected, and the C27 other end is connected with the end OUTB of U5, the one end capacitor C30 respectively, C30 other end difference Be connected with the one end resistance R5, T103 grid, the R5 other end respectively with the end VSSA of U5, the one end resistance R11, the source NMOS tube T102 Pole, T103 source electrode, the end VSSB of U6 are connected；

The R21 other end is connected with the one end capacitor C19, T104 grid respectively, the C19 other end respectively with the end OUTA of U5, electricity Hold the one end C20 to be connected, the C20 other end is connected with the R11 other end, T102 grid respectively.

As another preferred embodiment, the first NMOS tube drain electrode of third level charge pump described in the utility model connects NMOS tube T25 source electrode, the 4th NMOS pipe source electrode connect NMOS tube T27 source electrode.

As another preferred embodiment, three-terminal regulator chip U14 described in the utility model uses LM7809CT chip.

As another preferred embodiment, input E1 described in the utility model is 25.6V.

Secondly, T100, T101 described in the utility model use IRF540 type NMOS tube.

In addition, 18 feet of U12 described in the utility model are connected with 12MHz crystal oscillator one end, the one end capacitor C7 respectively, C7 is another End is connected with 20 feet of the one end capacitor C8, U12 respectively, the capacitor C8 other end 19 feet with the 12MHz crystal oscillator other end, U12 respectively It is connected.

The utility model beneficial effect.

The utility model charge pump pressure regulation conversion circuit is not necessarily to inductance element, and energy loss is small, and pressure regulation is convenient, high-efficient.

The multiple charge pumps of the utility model are sequentially connected in series, and select the connecting pin between adjacent charge pump by control switch Mouth makes charge pump regulating circuit export the voltage met the requirements, it can be achieved that multiple partial pressure and combinations of voltages.

The utility model provides a kind of hardware foundation of charge pump conversion circuit that energy loss is small.

Detailed description of the invention

Fig. 1 is the utility model schematic block circuit diagram.

Fig. 2 is the utility model charge pump block diagram.

Fig. 3 is the charge pump and control switch that the utility model is made of metal-oxide-semiconductor.

Fig. 4 is the utility model control from view of profit power measurement component connection figure.

Fig. 5 is that the utility model using the mode of gating switch eliminates charge pump impulse noise figure.

The waveform (50 μ s/div) of gate drive signal when Fig. 6 is the utility model circuit start.

Fig. 7 is inverting function figure of the utility model phase inverter to half-bridge metal-oxide-semiconductor dead zone.

Fig. 8 is 8 DAC circuit schematic diagrams of the utility model.

Fig. 9~Figure 11 is the partial enlarged view of Fig. 8.

Figure 12 is the utility model as reduction voltage circuit embodiment circuit diagram.

Figure 13~Figure 20 is the partial enlarged view of Figure 12.

Specific embodiment

As shown in Figure 1, the utility model includes multiple charge pumps being sequentially connected in series, pass through output end between adjacent charge pump Mouth selection control switch is connected.

The control signal output mouth of the control signal input mouth and controller of the control switch and charge pump switches It is connected.

The control signal input mouth of the control switch passes through the control signal output mouth of driving circuit and controller It is connected.

The charge pump generates the voltage at two times of relationships；Control switch connects rear stage charge pump previous for selecting On any two ports of grade charge pump；Controller controls these into the syntagmatic of the voltage of two times of relationships.

The controller measures voltage, the electric current of the input and output of entire charge pump regulating circuit.

The controller generates the control signal of charge pump gate driving.

The controller and peripheral components, external device communication.

The controller is single-chip microcontroller.Controller can be also using the circuit of discrete component composition, logic circuit, FPGA circuitry Deng.

As shown in figure 3, the charge pump include left and right two partial pressure bridge arms, partial pressure bridge arm and control switch both ends with it is defeated Enter end to be connected, divides bridge arm and control switch includes multiple concatenated switching tubes, divide the central node and control switch of bridge arm Central node be connected.

The left partial pressure bridge arm includes NMOS tube T1, T2, T3, T4, and right partial pressure bridge arm includes NMOS tube T5, T6, T7, T8, Control switch includes NMOS tube T9, T10, T11, T12；

T1, T3 conducting, T2, T4 cut-off are a kind of working condition；T1, T3 cut-off, T2, T4 conducting are another work State, two states are constantly switched fast, and the time respectively accounts for 50%；The conducting of two bridge arm corresponding position NMOS tubes, cut-off shape State is opposite (such as T4 conducting, T8 cut-off).

In the first working condition, U_C3=U_DE；In second of working condition, U_C3=U_CD.Due to be added in capacitor C3, C1, C2 both end voltage cannot be mutated, and final D point voltage can reach the median of C, E two o'clock voltage.Facilitated using two bridge arms Improve output power.The input and output of this two partial pressures charge pump are exchanged, the charge pump of two multiplication of voltages can be obtained, that is, export Voltage is twice of input voltage.

The size of circuit final output voltage from depend on charge pump units at different levels between two kinds of tandem states combination, Every to pass through one-step charge pump unit, the interval (i.e. the voltage of C, E two o'clock in Fig. 2) of output voltage just halves, and is finally reached foot Enough fine degree.Switch between grade be exactly control rear stage charge pump connect previous stage charge pump any two voltage class it Between, it realizes output voltage control from ground voltage to value a certain total input voltage.

As the control section in Fig. 3 exports D, E two of VOUT and charge pump when T9, T11 are connected, and T10, T12 end Point is connected, otherwise is connected with C, D two o'clock.Conducting that controller is switched by driving circuit drive control, off state, cut in real time Change the getting type of F, G point and charge pump.

The control signal is multidigit binary control signal, suitable for the charge pump of two partial pressures, the output of control circuit Voltage makes itself and this binary numeral Linear proportional.

If charge pump only has level-one, only one group of control switch, control signal only needs one, and resolution ratio is exactly 0.5. If charge pump has n grades, resolution ratio is justIn n grades of charge pump systems, if the corresponding binary number of control signal For x, input voltage U_i, output voltage is

The digit of the multidigit binary control signal is identical as the number of charge pump.

The number of the charge pump is 8 or 16.

The controller uses pid algorithm, and output valve is converted into after integer variable and is directly exported by the I/O mouth of controller To control switch.

It can be inputted and export exchange, charge pump has the interchangeable characteristic of input and output, realizes boosting, booster circuit Feed-forward control manner can be used.The final output voltage U of circuit is determined first_o, this voltage must be always greater than input voltage , resolution voltage is then determined according to circuit charge-pump (by taking two partial pressures as an example) series nInput voltage U is measured again_i, root According to input voltage obtain booster circuit control switch state using binary mode (closest to input terminal switch as lowest order, It is 0 that switch, which is all placed in lower ends, otherwise is 1, sees Fig. 2) corresponding numerical value isIt can be by booster circuit and reduction voltage circuit grade Connection, not only may be implemented to boost, but also may be implemented to be depressured.

As shown in figure 4, the output power of the utility model measuring circuit, if output power it is larger (in such as exemplary circuit, The electric current of 1A is exported under 10V output), then use higher switching frequency (such as 100kHz)；(such as show if output power is smaller In the case of exporting 10V in example circuit, when circuit output zero load), then use lower switching frequency (such as 1kHz).In this way, both protecting It has demonstrate,proved in high-power output, the electric current that circuit can be sufficiently large, and has realized in small-power output, be unlikely to system function Excess waste is consumed in the charge and discharge of mos gate electrode capacitance.

The input power and output power of the utility model real-time measurement circuit, calculate efficiency；Switching frequency it is too low and The excessively high reduction that can all lead to efficiency, therefore efficiency value can be made to reach by real-time regulating switch frequency (such as 1kHz-100kHz) Highest.

In the program of the controller, the driving of all control switches and charge pump switches signal statement are put together execution (impulse noise all being concentrated on a time point) adds a gating switch in the output end of entire circuit, which opens It closes and is disconnected before impulse noise generation, impulse noise recloses after disappearing；Reduce influence of the impulse noise to circuit.

The input terminal of the circuit adds a gating switch, which disconnects before impulse noise generation, impulse Noise recloses after disappearing；Reduce influence of the impulse noise to circuit.

The case where tri- road impulse noise of Tu5Shi is superimposed, left side are that impulse noise is concentrated the scheme eliminated, and right side is that do not have Concentrate the scheme of impulse noise measure.Although impulse noise is very strong as it can be seen that noise is superimposed by left side scheme, impulse noise Root be metal-oxide-semiconductor on state in program switching control, the time can determine, final due to the presence of gating switch Output noise is simultaneously little；And the scheme on right side, due to not having concentration impulse noise, each position of final output voltage is all folded Added with the impulse noise on each road, this impulse noise that is frequent, occurring at random is difficult to eliminate.

As shown in figure 8, being embodiment of the utility model as digital analog converter (DAC) circuit.The charge pump Including the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube, control switch includes third PMOS tube, third NMOS tube, the 4th PMOS tube and the 4th NMOS tube；

The drain electrode of second PMOS tube is connected with the drain electrode of third the capacitor other end, the second NMOS tube respectively, the second NMOS tube Source electrode be connected respectively with input cathode, the second capacitor other end, the 4th NMOS tube source electrode, the 4th NMOS tube drain electrode respectively with Negative pole of output end, the 4th PMOS tube source electrode be connected, third PMOS tube drain electrode respectively with third NMOS tube drain electrode, output head anode phase Even；

The charge pump is eight.

The source electrode of first NMOS tube of the utility model afterbody charge pump is connected with the source electrode of the 5th PMOS tube, and the 5th The drain electrode of PMOS tube is connected with the drain electrode of the anode of output buffer, the 5th NMOS tube respectively, and the source electrode of the 5th NMOS tube connects most The source electrode of second NMOS tube of rear stage charge pump；The grid of 5th PMOS tube connects Bit0PMOS control terminal, the 5th NMOS tube Grid connects Bit0NMOS control terminal；The negative terminal of buffer connects the output end of buffer.

In above-mentioned DAC, reference voltage is exactly the input voltage of circuit, and the digital quantity of input is exactly the control of control switch Signal, the simulation output of DAC are exactly the final output voltage of charge pump.DAC essence is a reduction voltage circuit, but not due to DAC It needs to export too big electric current, is not here the full circuit for using NMOS, in this way, respectively for the ease of the integrated of CMOS technology A metal-oxide-semiconductor control gets up to facilitate many, controls each half-bridge and is controlled respectively without two metal-oxide-semiconductors using opposite level, Only need a control signal.It, can be by two metal-oxide-semiconductors the (the i.e. the 5th in the control of the last one control switch of circuit PMOS tube and the 5th NMOS tube) it controls respectively, this level-one control switch can be used as gating switch simultaneously, inhibit impulse noise (see Fig. 5).

For the utility model when not having impulse noise, the control terminal level of the 5th PMOS tube and the 5th NMOS tube keeps one It causes, the lowest order of digital quantity is inputted for DAC；And when there is impulse noise, the 5th PMOS tube control terminal control level be height, the 5th NMOS tube control terminal control level is low, output and previous circuit disconnection, isolation impulse noise；

The high level of the utility model switch control signal is at least higher by the threshold value electricity of a NMOS than power input voltage It presses (0.7V), the threshold voltage (0.7V) of a low level out PMOS at least lower than ground voltage；Guarantee that NMOS and PMOS is effective Ground control.

The charge pump is two partial pressure charge pumps.

The NMOS tube uses CSD16570Q5B type NMOS tube；Conducting resistance is small, is lost low.

It as shown in figure 12, is embodiment of the utility model as reduction voltage circuit.First order charge pump includes NMOS tube T1 ~T8, T1 drain electrode respectively with input E1 anode, the input terminal of three-terminal regulator chip U14, the one end capacitor C53, the one end capacitor C9, T5 Drain electrode, the one end capacitor C10 are connected；

The end OUTA of U1 is connected with the one end capacitor C5, T3 grid, the one end capacitor C3 respectively, the capacitor C3 other end respectively with T1 Grid, the resistance R1 other end, diode D6 anode are connected, and D6 cathode is connected with the C9 other end, diode D7 cathode respectively, D7 Anode is connected with the one end resistance R2, the one end capacitor C4, T5 grid respectively, and the R2 other end is leaked with D5 cathode, T5 source electrode, T6 respectively Pole, the one end capacitor C2, the end VDDB of U1 are connected, and the C2 other end is connected with the end VSSB of T7 source electrode, T8 drain electrode, U1 respectively；

T2 grid connects T7 grid, and T6 grid connects T3 grid.

The utility model circuit is when just powering on, shutdown T11 (i.e. the end INB of U2 always input low level), (i.e. to T10 The end INA of U2 inputs oscillator signal, and frequency usually applies oscillator signal in the gate drive signal of 10kHz to 100kHz), passes through (such as 100ms) for a period of time, after the down tube of downside half-bridge is controllable, T14 and T15 constitute latching circuit, this circuit is a positive feedback Circuit does not have foreign intervention such as, is finally only capable of output high level or low level.But output end is connected with resistance R1, makes electricity Road has sufficiently high output impedance (about 5k Ω in this circuit arrangement), to be passed through by gate drivers by the end OUTA of U2 C14 drives indirectly.But this impedance is enough to drive the grid of subsequent metal-oxide-semiconductor T12 when MOS driving signal is direct current.If Latching circuit is not used directly to drive the grid of T12 by capacitor C14, then when this metal-oxide-semiconductor is turned off or is connected for a long time, Capacitor C14, which can leak electricity, causes the conducting off state of T12 uncertain.But latching circuit exports low and high level shape when just powering on State is uncertain, by applying the oscillator signal of certain time to this circuit output, can make the pressure drop of C14 that can effectively pass just Pass gate drive signal.When its judgment criteria, T12 can guarantee cut-off when T10 ends, and T12 can guarantee conducting when T10 is connected.In During practical realization, a constant time lag value can be set, in this delay value, the gate drive signal of T10 keeps oscillation State, setting 100ms can meet exhausted application demand.

T10 is turned off again, applies the oscillator signal of 100ms to T11 grid, it is ensured that the down tube of downside half-bridge is controllable, Zhi Houbian It no longer forces or to be forced shutdown T10, T11 to T10, T11 time oscillation signal, the conducting of T10, T11, off state are by defeated Control program determines out.

Control switch between the utility model first order charge pump and second level charge pump includes NMOS tube T9~T12, T9 drain electrode respectively with input E1 anode, UCC21521ADW chip U2 the end VDDA is connected, T9 grid respectively with the one end R16, electricity Hinder the one end R8, the one end capacitor C16 be connected, another termination NPN triode T16 base stage of R16, T16 collector respectively with resistance R18 mono- End, the one end resistance R17 are connected, and the resistance R17 other end is connected with diode D7 cathode, PNP triode T13 emitter respectively, T13 base stage connects the R18 other end, the T13 collector connecting resistance R8 other end；

The utility model second level charge pump includes NMOS tube T17~T24, T17 drain electrode respectively with the one end resistance R22, electricity Appearance one end C28, diode D13 anode, the one end capacitor C24, diode D11 anode, T21 drain electrode are connected, another termination PNP of R22 Triode T13 collector；T17 grid is connected with the one end resistance R9, diode D10 cathode, the one end capacitor C15 respectively, the source T17 Pole respectively with the R9 other end, D10 anode, the one end capacitor C51, T18 drain electrode, the one end capacitor C22 be connected, T18 grid respectively with T20 Grid, the one end capacitor C17, T23 grid, the end OUTB of UCC21521ADW chip U3 are connected, and T18 source electrode is another with C28 respectively End, the one end capacitor C13, T19 drain electrode, T22 source electrode, T23 drain electrode are connected；

The C51 other end is connected with D13 cathode, D1 anode respectively, D1 cathode respectively with the C24 other end, diode D2 cathode, The one end resistance R7 is connected, and D11 cathode is connected with D2 anode, the one end capacitor C52 respectively, and the C52 other end is positive with diode D12 respectively Pole, the one end resistance R19, T21 source electrode, the one end capacitor C23 are connected, and T21 grid is another with D12 cathode, the R19 other end, C17 respectively One end is connected；The C23 other end is connected with T23 source electrode, T24 drain electrode respectively；

Control switch between the utility model second level charge pump and third level charge pump includes NMOS tube T25~T28, T25 drain electrode respectively with NMOS pipe T21 drain electrode, diode D9 anode is connected, D9 cathode respectively with PNP triode T29 collector, The one end capacitor C25, the end VDDB of VDDA, U5 of UCC21521ADW chip U5, UCC21521ADW chip U4 the end VDDB phase Even, T29 emitter connects the cathode of diode D2, and T29 base stage is connected with resistance R7, the one end resistance R20 respectively；

The utility model third~eight grade charge pump includes the first~eight NMOS tube, the first NMOS tube (T30, with the third level For charge pump) drain is connected with the one end first capacitor (C29), the drain electrode of the 5th NMOS tube (T34) respectively, the first NMOS tube source electrode It is connected respectively with the one end the second capacitor (C21), the second NMOS tube (T31) drain electrode；

Control switch between the utility model third~eight grade charge pump adjacent charge pump includes the 9th NMOS tube~the 12 NMOS tubes (T38, T39, T40, T41, by taking the control switch between third level charge pump and fourth stage charge pump as an example), The drain electrode of 9th NMOS tube drains with the 5th NMOS tube of prime charge pump to be connected, the 9th NMOS tube source electrode respectively with rear class charge pump The first NMOS tube drain electrode, the tenth NMOS tube drain electrode be connected, the tenth NMOS tube source electrode respectively with the 6th NMOS of prime charge pump Pipe source electrode, the 11st NMOS tube drain electrode be connected, the 11st NMOS tube source electrode respectively with the 4th NMOS tube source electrode of rear class charge pump, The drain electrode of 12nd NMOS tube is connected.

Nine, the 11 NMOS tube grid of the control switch between the utility model third level charge pump and fourth stage charge pump Pole is connected with the port OUTB of UCC21521ADW chip U6, and the ten, the 12 NMOS tube grids are connected with the port OUTA of U6；

6th NMOS tube source electrode of the 8th grade of charge pump of the utility model is connected with NMOS tube T100 drain electrode, T100 source electrode point It is not connected with NMOS tube T101 drain electrode, the one end capacitor C56, T101 source electrode connects the 8th NMOS tube source electrode of the 8th grade of charge pump, electricity Hold C56 other end ground connection；

The switching drive signal of NMOS gate is coupled in circuit by grid capacitance, forms impulse noise.T100, Control switch of the T101 as most rear class charge pump, while as gating switch, by controlling T100, T101, in impulse noise Before arrival, output end and circuit are disconnected, disappear in impulse noise and then terminate to output in circuit.

The first NMOS tube grid of charge pump at different levels is connected in the utility model third~eight grade charge pump, charge pumps at different levels The 5th NMOS tube grid be connected, the first NMOS tube grid respectively with PMOS tube T105 drain electrode, NMOS tube T103 drain electrode is connected, T105 source electrode respectively with the end VDDA of UCC21521ADW chip U5, the one end resistance R21, PMOS tube T104 source electrode, resistance R15 mono- End, the end VDDA of UCC21521ADW chip U6 are connected, and the resistance R15 other end is connected with the one end capacitor C27, T105 grid respectively, The C27 other end is connected with the end OUTB of U5, the one end capacitor C30 respectively, the C30 other end respectively with the one end resistance R5, T103 grid Be connected, the R5 other end respectively with the end VSSA of U5, the one end resistance R11, NMOS tube T102 source electrode, T103 source electrode, U6 the end VSSB It is connected；

The first NMOS tube drain electrode of the third level charge pump connects NMOS tube T25 source electrode, and the 4th NMOS tube source electrode meets NMOS Pipe T27 source electrode.

The three-terminal regulator chip U14 uses LM7809CT chip.

The input E1 is 25.6V.

Described T100, T101 use IRF540 type NMOS tube；Grid capacitance is small.

18 feet of the U12 are connected with 12MHz crystal oscillator one end, the one end capacitor C7 respectively, the C7 other end respectively with capacitor C8 One end, 20 feet of U12 are connected, and the capacitor C8 other end is connected with 19 feet of the 12MHz crystal oscillator other end, U12 respectively.

The operating voltage of charge pumps at different levels with series increase exponential damping.Close to the charge pump and control switch of input terminal Operating voltage it is relatively high, remaining is relatively low.The circuit part of different operating voltage uses different control modes.In circuit Relatively the charge pump and control switch of input power use respective control mode, rear class charge pump, using same group of control Signal processed is controlled.

It is 25.6V by the operating voltage highest of charge pump and control switch that T1-T12 and some peripheral cells form. The grid source breakdown voltage and drain-source breakdown voltage of metal-oxide-semiconductor CSD16570Q5B is respectively less than this value, therefore, this circuit different operating The metal-oxide-semiconductor of voltage range, grid will control respectively.In this circuit arrangement, by the metal-oxide-semiconductor that gate drivers directly drive be T3 and T7, the secondary work power supply of gate drivers are derived from bootstrap capacitor C1 and C2, and finally stable voltage is electric thus for bootstrap capacitor The output voltage of lotus pump, therefore, the driving voltage (source electrode relative to the two metal-oxide-semiconductors) of the grid of grid T3 and T7 is thus The half of charge pump input voltage, i.e. 12.8V.This gate drive signal is transmitted to identical with its working condition by C3, C4 T1, T5, therefore the gate drive signal amplitude of T1, T5 are also 12.8V, but since R1, R2 are by the DC voltage of T1, T5 grid It is fixed as its source voltage, real gate source voltage is only the half of 12.8V, i.e. 6.4V.

The gate source voltage amplitude of T3, T7 are 12.8V, and still, when closed, source voltage is the two metal-oxide-semiconductors 12.8V, source voltage is 0 when cut-off.If adding gate source voltage, the grid voltage (electricity over the ground of the two metal-oxide-semiconductors Pressure) it is 25.6V.This signal can be used as the driving signal of remaining metal-oxide-semiconductor.Equally, the gate source voltage maximum value of these metal-oxide-semiconductors is grid The half of pole tension, i.e. 12.8V.

The metal-oxide-semiconductor driving method for the second level charge pump being made of T17-T24 and its peripheral cell is different.Due to it Operating voltage halves, and the power supply of the gate drivers secondary of this level-one is directly derived from the input terminal 12.8V of charge pump, and by grid The metal-oxide-semiconductor that driver output end directly drives is the down tube and T19, T23 of all half-bridges.The gate drive signal of T17 and T21 point It is not coupled to form by the gate drive signal of T19, T23 by capacitor C15, C17.Since voltage reduces, this level-one T17, T21 Gate drive signal do not use the source voltage of T17, T21 as dc point, but use two two poles D10, D12 Pipe limits the potential minimum of T17, T21 grid, to make to couple the gate driving signal to come by capacitor C15, C17 All it is added on the grid of T17, T21.

Since the operating voltage of preceding two-stage charge pump is different, the driving method of their own control switch is not yet Together.Different with the metal-oxide-semiconductor working characteristics of charge pump, control switch is not always switch state of the work in high frequency, very may be used Can be connected or be all off within a very long time, this means that its control signal transmitting cannot simply make Gate drive signal is transmitted with capacitor.This just needs circuit to generate a voltage more higher than input voltage, continues for generating Ground gate drive signal.In the control switch of first order charge pump, this lasting signal higher than input voltage is by T1, T5 Switching drive signal generated after D6, D7 and C9.The gate drive signal of T1, T5 are its gate drive voltage relative to each From the half of source voltage amplitude 12.8V, it finally can produce the voltage that one is higher by 6.4V than input voltage and (ignore diode pressure Drop).In order to save the more expensive gate drivers of price, one group of control signal control simultaneously or more two and half is used only here Bridge.Gate drivers directly control the downside upper tube of half-bridge and the down tube of upside half-bridge.The upper tube of half-bridge is on the downside of directly driving Because the upper tube gate drivers secondary work voltage of downside half-bridge is easier to obtain, the gate drivers secondary work of upper tube Make the output that voltage can directly be derived from first order charge pump control switch；And directly drive the mode and electricity of the down tube of upside half-bridge Coupled latching circuit when the starting on road (altogether there are two latching circuit in figure, first be T13, T16, R16, R17, The circuit of R18, R8, R22 composition, second circuit for T14, T15, R12, R13, R14, R10, R23 composition) state can not It determines related.The benefit that two metal-oxide-semiconductors that gate drive signal directly drives are located at two half-bridges is can be in state electricity Line state closes a metal-oxide-semiconductor of half-bridge when uncertain by force, so that two metal-oxide-semiconductors be avoided to simultaneously turn on charge pump short circuit.

Circuit is forced shutdown the upper tube of downside half-bridge when just powering on, and forces to the grid of the down tube of upside half-bridge Apply oscillator signal, after a period of time, circuit stability reuses opposite side after determining that the down tube of downside half-bridge is controllable Formula, it is ensured that the upper tube of upside half-bridge is controllable, just enters normal state of a control later.It is directly driven by gate drivers at the two After dynamic metal-oxide-semiconductor obtains control, circuit also needs for the control signal of the two MOS pipes to be transmitted on corresponding opposite side half-bridge (i.e. the gate drive signal of the T11 grid that is coupled to T9 by C16, the gate drive signal of T10 are coupled to T12 grid by C14 Pole).Here add the transmission method of latching circuit using capacitor.The effect of capacitor is the side for transmitting gate drive signal steeper Edge, and the effect of latching circuit is to maintain the state after gate drive signal transmitting.The output of latching circuit resistance with higher It is anti-, to enable its output voltage easily to be controlled by the driving signal of gate drivers, and this impedance is far smaller than metal-oxide-semiconductor Grid source resistance, MOS pipe can also be controlled effectively.

The control switch of second level charge pump is similar with first order charge pump, also need one be higher than this charge pump it is defeated Enter the higher voltage of ceiling voltage.But this voltage is no longer by the grid of two metal-oxide-semiconductors in top side in this grade of charge pump Driving signal generates, but is generated by the half-bridge intermediate point of upside two by capacitor bootstrapping, if not considering the pressure drop of diode, The end value of boosting is that 12.8V+6.4V=19.2V (analyzes this grade of charge pump for the time being with the input voltage minimum point of this charge pump As reference).Circuit using this structure is because this voltage more higher than input voltage not only provides an electricity Pressure, also needs certain output power.Because of the gate drive signal electricity of metal-oxide-semiconductor in rear class all charge pump and control switch Stream all provides (reason sees below) by this circuit substantially, can provide enough power using the circuit of this structure.Due to The voltage class of circuit is different, and the gate drive signal of metal-oxide-semiconductor directly controls two groups of half-bridges in the control switch of this grade of charge pump Upper down tube, controlled without carrying out capacitor and latching circuit, need not also consider starting problem.But this mode need to be examined Consider the driving problems of the metal-oxide-semiconductor of top side.This needs the gate drivers secondary offer one to driving upper tube metastable Operating voltage.Specific solution is, when two half-bridge down tubes are connected, the intermediate point of downside half-bridge is low level 0V, this When, gate drivers secondary voltage is provided by charge pump input voltage by D9.When down tube is turned off, the gate driving of down tube Signal is 0V, and the voltage that this signal obtains after D8, R20 and T29 reverse phase is 19.2V, at this point, gate drivers secondary negative terminal Voltage is 6.4V, and gate drivers secondary voltage is still 12.8V.In real work, due to pressure drop of diode, triode etc. because Element, control switch this voltage when two states switch may slightly change, but this variation can be slowed down by C25, grid Driver still can steady operation.

The input highest of remaining grade of charge pump has already decreased to 6.4V, and (low-voltage relative to third level charge pump inputs End, this point is as with reference to ground), gate drivers secondary connects the collector of the T29 at 12.8V, this voltage is enough to control these electricity Any one metal-oxide-semiconductor in lotus pump and control switch.All oscillator signals of these charge pumps are all driven by one group of gate drive signal It is dynamic, but this group of gate drive signal is not directly connected to the grid of each metal-oxide-semiconductor after gate drivers outflow, but Respectively by one group of phase inverter connection, this group of phase inverter is made of T102-T105 and its peripheral circuit.This is because grid The transient current of driver output is limited, the gate drivers model UCC21521ADW selected in this reduction voltage circuit example, Its peak point current only has 5A or so, and the metal-oxide-semiconductor quantity for needing to drive is 4 × 6=24, the grid of metal-oxide-semiconductor CSD16570Q5B Capacitor is about 0.015 μ F, and total capacitance is 0.015 μ F × 24=0.36 μ F, needs the charge to be (when 12V) full of (emptying) is electric 0.36 μ F × 12V=4.32 μ C, filling and (put) electricity primary time isThis time is quite very long, It is effectively controlled to metal-oxide-semiconductor, at least increases to original 10 times of electric current, this time is foreshortened to originalIt is all The energy that capacitor charge and discharge once consumes is 3 × 0.015 μ F × (12V)²=6.48 μ J, under the switching frequency of 100KHz, Power is 6.48 μ J × 100kHz=648mW.

On startup, the gate drivers secondary voltage of first order charge pump is provided circuit by C1, C2, and C1, C2 are in electricity Voltage is 0 when road just starts, therefore gate drivers can not drive any one metal-oxide-semiconductor, and all metal-oxide-semiconductors are off-state, C1, C2 will not be electrically charged.A start-up circuit is needed, allows circuit in rigid starting, C1, C2 can be charged to gate drivers In workable range.This scheme is realized by U14 and D3-D5.When 25.6V is added in the input terminal of three terminal regulator 7809 When, output end exports 9V, this voltage is added on the anode of C1, C2 by D4, D5.Circuit powers on flashy impulse electricity Pressure is transmitted to the grid of T4, T8 by the interelectrode capacity of each component, and T4, T8 transient switching, C1, C2 are electrically charged.Circuit is rigid When powering on, the grid of T4, T8 are drawn high by moment, and after a period of time has passed, C1, C2 voltage reach gate drivers secondary can be with The voltage of work, circuit start starting of oscillation, finally tend towards stability.

8051 single-chip microcontroller of the utility model is settable, and there are two global variables:

Char state and char voltage；

Char voltage is the voltage value variable of output, changes this value and changes output voltage；

Char state variable is used to record the state of charge pump switches signal, for controlling P1 mouthfuls of output level；Become Four front twos are one group after amount, and latter two are one group, control two groups of charge pumps respectively；First group of charge pump is the 1st, 2 grade Charge pump, second group of charge pump are 3-8 grades of charge pumps；By constantly negating 4 after this variable, oscillator signal is realized Output；

The Dead Zone of first group of charge pump control signal of the utility model: dead zone is low level when exporting from single-chip microcontroller, And it is output to gate drivers input terminal；

The Dead Zone of second group of charge pump control signal: the level state in dead zone is output to gate drivers after being negated Input terminal, when being output to gate drivers input terminal after negating, dead zone level is low level.

The value of voltage and the linear relationship of output voltage, in a manner of binary, one by one with the state of control switch It is corresponding.

Two pairs of switching signals are generated in the process of interruption, the gate drivers output of the first order, second level charge pump is direct Control metal-oxide-semiconductor, and the gate drivers of all charge pumps of rear class output control signal after, by metal-oxide-semiconductor reverse phase, strengthening electric current Metal-oxide-semiconductor is just controlled after fan-out capability.After this control signal is inverted, the level state for controlling signal can be inverted.Fig. 7 exhibition The Dead Zone of two groups of control signals is shown.The figure in left side is first group of charge pump, that is, the 1st, 2 grade of all half-bridges of charge pump Switching signal, the switching signal of this group of charge pump, dead zone is low level when exporting from single-chip microcontroller, and is output to gate driving Device input terminal.And the figure on right side, then it is second group of charge pump, i.e., the switching signal of 3-8 grades all half-bridges of charge pump.This is opened OFF signal is increased since the metal-oxide-semiconductor of driving is relatively more using phase inverter (see the region between U5, U6 two elements of attached drawing 12) Output electric current, so, the level state in dead zone is also negated.The control voltage directly exported by single-chip microcontroller is upside Figure, after inverter, result is the figure of downside, this voltage output to gate drivers input terminal drives 3-8 grades The MOS tube grid of charge pump.

Claims

1. a kind of charge pump conversion circuit, including multiple charge pumps being sequentially connected in series, it is characterised in that lead between adjacent charge pump Output port selection control switch is crossed to be connected；

The charge pump includes the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube, and control switch includes the Three PMOS tube, third NMOS tube, the 4th PMOS tube and the 4th NMOS tube；

The source electrode of first PMOS tube is connected with input anode, first capacitor one end, third PMOS tube source electrode respectively, the first PMOS The grid of pipe, the first NMOS tube, the second PMOS tube and the second NMOS tube is connected with charge pump switches signal input part, the first PMOS The drain electrode of pipe is connected with the drain electrode of the first NMOS tube, third capacitor one end respectively, and the source electrode of the first NMOS tube is electric with first respectively The appearance other end, second capacitor one end, the source electrode of the second PMOS tube, the source electrode of third NMOS tube, the source electrode of the 4th PMOS tube are connected；

The drain electrode of second PMOS tube is connected with the drain electrode of third the capacitor other end, the second NMOS tube respectively, the source of the second NMOS tube Pole is connected with input cathode, the second capacitor other end, the 4th NMOS tube source electrode respectively, the 4th NMOS tube drain electrode respectively with output Cathode, the drain electrode of the 4th PMOS tube is held to be connected, the drain electrode of third PMOS tube is connected with the drain electrode of third NMOS tube, output head anode respectively；

Third PMOS tube, third NMOS tube, the 4th PMOS tube and the 4th NMOS tube grid be connected with digital quantity input port.

2. a kind of charge pump conversion circuit according to claim 1, it is characterised in that the charge pump is eight.

3. a kind of charge pump conversion circuit according to claim 2, it is characterised in that the first NMOS of afterbody charge pump The source electrode of pipe is connected with the source electrode of the 5th PMOS tube, the 5th PMOS tube drain electrode respectively with the anode of output buffer, the 5th The drain electrode of NMOS tube is connected, and the source electrode of the 5th NMOS tube connects the source electrode of the second NMOS tube of afterbody charge pump；5th PMOS The grid of pipe connects Bit0 PMOS control terminal, and the grid of the 5th NMOS tube connects Bit0 NMOS control terminal；The negative terminal of buffer connects slow Rush the output end of device.

4. a kind of charge pump conversion circuit, including multiple charge pumps being sequentially connected in series, it is characterised in that lead between adjacent charge pump Output port selection control switch is crossed to be connected；

The number of the charge pump is 8, and first order charge pump includes NMOS tube T1~T8, T1 drain electrode respectively with input E1 just Pole, the input terminal of three-terminal regulator chip U14, the one end capacitor C53, the one end capacitor C9, T5 drain electrode, the one end capacitor C10 are connected；

Input E1 cathode respectively with ground wire, the C53 other end, the ground terminal of three-terminal regulator chip U14, the one end capacitor C54, the source T4 Pole, the one end resistance R3, the one end resistance R4, T8 source electrode, the one end capacitor C11 are connected；

The output end of U14 respectively with the C54 other end, the input terminal of three-terminal regulator chip U13, diode D5 anode, diode D4 Anode, diode D3 anode are connected；

The ground terminal of U13 is grounded, the output end of the U13 end the VCCI1 phase with the one end capacitor C12, UCC21521ADW chip U1 respectively Even, capacitor C12 other end ground connection, 3 feet that the INA of U1 terminates 8051 chip U12 are connected, and the INB of U1 terminates 8051 chip U12's 4 feet are connected, and the end the GND ground connection of U1, the end EN, the end DT, the end VCCI2 of U1 is connected；

The end VDDA of U1 is connected with the one end resistance R1, the source electrode of T1, the drain electrode of T2, the one end capacitor C1, diode D4 cathode respectively；

The end OUTA of U1 is connected with the one end capacitor C5, T3 grid, the one end capacitor C3 respectively, the capacitor C3 other end respectively with T1 grid Pole, the resistance R1 other end, diode D6 anode are connected, and D6 cathode is connected with the C9 other end, diode D7 cathode respectively, D7 anode It is connected respectively with the one end resistance R2, the one end capacitor C4, T5 grid, the R2 other end drains with D5 cathode, T5 source electrode, T6 respectively, is electric Appearance one end C2, the end VDDB of U1 are connected, and the C2 other end is connected with the end VSSB of T7 source electrode, T8 drain electrode, U1 respectively；

The end OUTB of U1 is connected with the one end capacitor C6, T7 grid, the capacitor C4 other end respectively, and T8 grid is another with resistance R4 respectively End, the C5 other end are connected, and the C6 other end is connected with the resistance R3 other end, T4 grid respectively；

T2 grid connects T7 grid, and T6 grid connects T3 grid.