CN109871059B - Ultralow voltage L DO circuit - Google Patents
Ultralow voltage L DO circuit Download PDFInfo
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- CN109871059B CN109871059B CN201910139295.3A CN201910139295A CN109871059B CN 109871059 B CN109871059 B CN 109871059B CN 201910139295 A CN201910139295 A CN 201910139295A CN 109871059 B CN109871059 B CN 109871059B
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Abstract
The invention relates to an ultralow voltage L DO circuit which comprises a L DO circuit and a power circuit, wherein the power circuit is externally connected with an input power supply and used for receiving input voltage of the input power supply, boosting the input voltage when the input voltage is lower than a first preset reference voltage to obtain target voltage, sequentially stabilizing and boosting the input voltage when the input voltage is higher than the first preset reference voltage to obtain target voltage, and finally inputting the target voltage into a L DO circuit, and L DO circuit is externally connected with the input power supply and a load and used for receiving and obtaining required voltage based on the input voltage and the target voltage and inputting the required voltage into the load.
Description
Technical Field
The invention relates to the technical field of L DO, in particular to an ultra-low voltage L DO circuit.
Background
As the lower supply voltage of the power management chip can enable the circuit to work in the near-threshold voltage and sub-threshold voltage region, a large number of designs can prove that the dynamic power consumption and the static power consumption are reduced when the power supply voltage is lower than 0.5V, so that the circuit obtains the maximum energy conversion efficiency.
According to the report of international technology for semiconductor Industry (ITRS), when the rated System On Chip (SOC) design power supply voltage reaches 6nm, it will be lowered to 0.6v, so as to ensure the energy conversion efficiency of L DO, it is necessary to lower the input power supply voltage of L DO while lowering the chip power supply voltage (output voltage of L DO).
In the conventional power management system, L DO and DC-DC have different characteristics and play different roles. L DO has smaller ripple and higher power rejection ratio compared with DC-DC, and is more suitable for level-sensitive modules such as analog modules, radio frequency modules, digital-to-analog converters and analog-to-digital converters, particularly, digital chips become level-sensitive when the power supply voltage is lower than 0.5V, while in the conventional analog L DO, an error amplifier therein is difficult to work at a lower input power voltage, and if the output voltage is continuously reduced when the input power voltage satisfying the performance is adopted, the energy conversion efficiency is greatly reduced.
In recent years, a large number of digital L DO designs are provided at home and abroad, and a design of replacing an error amplifier by a comparator and a shift register is proposed for solving the problem of input power supply voltage, but the new problems of increased ripple and reduced power supply rejection ratio are brought, which is not in line with the original purpose of supplying power to a chip by using L DO, and how to ensure small ripple and high power supply rejection ratio while reducing L DO input voltage is a problem needing to be researched at present.
Disclosure of Invention
The invention provides an ultra-low voltage L DO circuit, which is used for solving the problem that the conventional L DO circuit cannot be compatible with low ripple, high power supply rejection ratio and energy conversion efficiency during low-voltage output.
The invention solves the technical problems that the ultra-low voltage L DO circuit is characterized by comprising a L DO circuit and a power supply circuit, wherein the input end of the power supply circuit and the first input end of the L DO circuit are both used for externally inputting a power supply, and the output end of the power supply circuit is connected with the second input end of the L DO circuit;
the power supply circuit is used for judging whether the received input voltage is smaller than a first preset reference voltage, if so, performing multiple boosting processing on the input voltage to obtain a first target voltage and inputting the first target voltage to the L DO circuit, and if not, performing voltage stabilization and multiple boosting processing on the input voltage in sequence to obtain a second target voltage and inputting the second target voltage to the L DO circuit, wherein the first target voltage and the second target voltage are both used for supplying power to the L DO circuit;
the L DO circuit is used for processing the input voltage received by the first input end of the L DO circuit to obtain a required voltage based on a second preset reference voltage and inputting the required voltage to a load.
The invention has the advantages that a lightweight local generation power supply is introduced into an L DO circuit, two paths of power supply are adopted, one path is used for directly inputting voltage to L DO, and the other path is used for supplying power to L DO after the input voltage is stabilized and boosted by the lightweight local generation power supply, namely when the voltage of the input power supply is lower, the voltage of the power supply is boosted, and when the voltage of the input power supply is higher, the voltage of the power supply is stabilized, so that the L DO circuit can work under the working environment of ultralow or wide voltage range, even if the load of the L DO circuit is an ultralow voltage digital module or other modules sensitive to power supply level (such as an ultralow voltage analog module, an ultralow voltage radio frequency module, an ultralow voltage DAC/ADC and the like), the DO circuit can also work normally, and the low ripple wave and high power supply rejection ratio is ensured while the energy conversion efficiency is improved.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the power supply circuit includes: a voltage stabilizing and regulating circuit and a booster circuit;
the input end of the voltage stabilizing and adjusting circuit is the input end of the power supply circuit and is used for judging whether the received input voltage is smaller than a first preset reference voltage or not, and if so, the input voltage is input to the booster circuit; if not, stabilizing the value of the input voltage to the value of the first preset reference voltage to obtain a new input voltage and inputting the new input voltage to the booster circuit;
and the output end of the boost circuit is the output end of the power supply circuit, and is used for boosting the input voltage input by the voltage stabilization regulating circuit by multiple times to obtain the first target voltage or the second target voltage and inputting the first target voltage or the second target voltage to the L DO circuit.
Further, the voltage regulation circuit includes: the first error amplifier, the first power tube and the first feedback resistance network;
the first error amplifier is externally connected with the input power supply, and the output end of the first error amplifier is connected with the grid electrode of the first power tube; the negative electrode of the first error amplifier is connected with the first feedback resistance network or a power supply for externally connecting the first preset reference voltage, and the positive electrode of the first error amplifier is connected with the power supply for externally connecting the first preset reference voltage or the first feedback resistance network; the source electrode or the drain electrode of the first power tube is used for being externally connected with the input power supply, and the drain electrode or the source electrode is connected with the first feedback resistance network and the booster circuit; the first feedback resistance network is also connected with the booster circuit.
Further, the first power tube is a weak output power tube.
The invention has the further beneficial effects that because the requirement of the working current of the control part in L DO is smaller, and the weak output power tube can ensure that the current output to the L DO circuit by the power circuit is smaller, the L DO current is ensured to be stable.
Further, when the first power tube is a PMOS tube, the negative electrode of the first error amplifier is externally connected with a power supply of the second preset reference voltage, and the positive electrode of the first error amplifier is connected with the first feedback resistance network; the source electrode of the first power tube is used for being externally connected with the input power supply, and the drain electrode of the first power tube is connected with the first feedback resistance network and is used for being externally connected with the booster circuit; the first feedback resistance network is also connected with the booster circuit;
when the first power tube is an NMOS tube, the negative electrode of the first error amplifier is connected with the first feedback resistance network, and the positive electrode of the first error amplifier is externally connected with a power supply of the first preset reference voltage; the drain electrode of the first power tube is used for being externally connected with the input power supply, and the source electrode of the first power tube is connected with the first feedback resistance network and the booster circuit; the first feedback resistance network is also connected with the booster circuit.
Further, the boost circuit is specifically configured to boost the input voltage input by the voltage regulation circuit by twice, obtain the first target voltage or the second target voltage, and input the first target voltage or the second target voltage to the L DO circuit.
The voltage stabilizing circuit has the further beneficial effects that the voltage stabilizing circuit can control the input of the booster circuit according to the first preset reference voltage so as to control the output target voltage and prevent the circuit breakdown caused by the target voltage being higher than the rated working voltage of the L DO circuit, and the value of the first preset reference voltage is related to the rated working voltage.
Further, the booster circuit includes: the power supply comprises a double-rate Pickery charge pump, a first energy storage capacitor, a second energy storage capacitor and a filter capacitor, wherein the first energy storage capacitor, the second energy storage capacitor and the filter capacitor are respectively connected with the double-rate Pickery charge pump;
a first input end of the double-rate Pirikeley charge pump is connected with the voltage-stabilizing regulating circuit, a second input end of the double-rate Pirikeley charge pump is an output end of the power supply circuit, and the double-rate Pirikeley charge pump is used for boosting the input voltage input by the voltage-stabilizing regulating circuit by two times to obtain the first target voltage or the second target voltage and inputting the first target voltage or the second target voltage to the L DO circuit;
the first energy storage capacitor and the second energy storage capacitor are also used for being externally connected with an asynchronous square wave pulse modulation circuit so as to store square wave information of two asynchronous square wave pulses input by the asynchronous square wave pulse modulation circuit and assist the double-fold Pirikele charge pump to carry out boosting operation;
the filter capacitor is further connected with the L DO circuit and is used for eliminating burrs and ripples of the first target voltage and the second target voltage.
The invention has the further beneficial effects that: the use of a Pirikele charge pump can reduce the minimum input voltage standard and increase the working voltage range.
Further, the peak values of the two asynchronous pulse square waves are equal to the value of the input voltage of the input power supply.
Further, the L DO circuit includes a second error amplifier, a second power transistor, and a second feedback resistance network;
the input end of the second error amplifier is the second input end of the L DO circuit, the output end of the second error amplifier is connected with the grid electrode of the second power tube, the negative electrode of the second error amplifier is connected with the second feedback resistance network and used for being externally connected with a power supply of a second preset reference voltage, the positive electrode of the second error amplifier is used for being externally connected with the power supply of the second preset reference voltage or connected with the first feedback resistance network, the source electrode or the drain electrode of the second power tube is the first input end of the L DO circuit, the drain electrode or the source electrode of the second error amplifier is connected with the second feedback resistance network and used for being externally connected with the load, and the second feedback resistance network is also used for being externally.
Furthermore, when the second power tube is a PMOS tube, the cathode of the second error amplifier is used for being externally connected with a power supply of second preset reference voltage, and the anode of the second error amplifier is connected with the second feedback resistance network;
when the second power tube is an NMOS tube, the negative electrode of the second error amplifier is connected with the second feedback resistance network, the positive electrode of the second error amplifier is used for being externally connected with a power supply of the second preset reference voltage, the drain electrode of the second power tube is the first input end of the L DO circuit, the source electrode of the second power tube is connected with the second feedback resistance network and is used for being externally connected with the load, and the second feedback resistance network is also used for being externally connected with the load.
Drawings
FIG. 1 is a block diagram of an ultra low voltage L DO circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of an ultra low voltage L DO circuit according to another embodiment of the present invention;
fig. 3 is a power circuit diagram according to another embodiment of the invention.
FIG. 4 is a circuit diagram of an L DO circuit according to another embodiment of the present invention;
fig. 5 is a circuit diagram of L DO according to another embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Example one
An ultra-low voltage L DO circuit 100 is shown in FIG. 1 and comprises a L DO circuit and a power circuit which are connected with each other, wherein the power circuit is further used for externally connecting an input power supply and is used for receiving input voltage of the input power supply, conducting multiple boosting processing on the input voltage when the input voltage is lower than a first preset reference voltage to obtain a first target voltage and inputting the first target voltage to a L DO circuit, conducting voltage stabilization and multiple boosting processing on the input voltage in sequence when the input voltage is higher than the first preset reference voltage to obtain a second target voltage and inputting the second target voltage to the L DO circuit, wherein the first target voltage and the second target voltage are both used for supplying power to the L DO circuit, and the L DO circuit is further used for externally connecting the input power supply and a load and is used for receiving the input voltage, processing the input voltage to obtain required voltage based on the second preset reference voltage and inputting the required voltage to the load.
It should be noted that, the energy conversion efficiency of the L DO circuit is ensured by directly connecting L DO circuit with the input power supply or the preceding stage circuit, in addition, the power supply circuit supplies power to the L DO circuit, so that the L DO circuit can keep high performance under the condition of ultra-low voltage input, the power supply circuit part boosts the input voltage when the input voltage is low, ensures the circuit performance, stabilizes the voltage when the input voltage is high, and prevents the circuit from breaking down, in addition, the two target voltages are inconsistent, such as the first preset reference voltage is 0.6V, the input voltages are 0.4, 0.8 and 1.2 respectively, the control part of the output voltages (required voltages) are 0.8, 1.2 and 1.2. L DO is mainly an error amplifier part, when the power supply voltage (provided by the input power supply) is too high, the circuit is broken down, the system fails, such as the highest working voltage of the circuit is 1.2V, and the voltage stabilization function is to ensure that the target voltage does not exceed 1.2V.
In this embodiment, a lightweight locally generated power supply is introduced into an L DO circuit, and two power supplies are adopted, one power supply is that an input voltage directly supplies power to a L DO, and the other power supply is that an input voltage supplies power to a L DO after being stabilized and boosted by the lightweight locally generated power supply, that is, the power supply voltage is boosted when the input power supply voltage is low, and the power supply voltage is boosted after being stabilized when the input power supply voltage is high, so that the L DO circuit can work in an ultralow or wide voltage range working environment, and can work normally even if a load of the L DO circuit is an ultralow voltage digital module or other modules sensitive to a power supply level (such as an ultralow voltage analog module, an ultralow voltage radio frequency module, an ultralow voltage DAC/ADC and the like), and the low ripple and high power supply rejection ratio is ensured while the energy conversion efficiency is improved.
Example two
On the basis of the first embodiment, as shown in fig. 2, the power supply circuit includes a voltage stabilization regulating circuit and a voltage boost circuit, the voltage stabilization regulating circuit is externally connected with an input power supply and is used for receiving an input voltage and inputting the input voltage to the voltage boost circuit when the input voltage is lower than a first preset reference voltage, the voltage stabilization regulating circuit is used for stabilizing the value of the input voltage to the value of the first preset reference voltage when the input voltage is higher than the first preset reference voltage to obtain a new input voltage and inputting the new input voltage to the voltage boost circuit, and the voltage boost circuit is connected with an L DO circuit and is used for multiplying the input voltage input by the voltage stabilization regulating circuit to obtain a first target voltage or a second target voltage and inputting the first target voltage or the second target voltage to the L DO circuit.
Preferably, as shown in fig. 3, the voltage regulation circuit includes: the power amplifier comprises a first error amplifier, a first power tube and a first feedback resistance network. The input end of the first error amplifier is connected with the input power supply, and the output end of the first error amplifier is connected with the grid electrode of the first power tube; the negative electrode of the first error amplifier is connected with the first feedback resistance network or externally connected with a power supply of a first preset reference voltage, and the positive electrode of the first error amplifier is externally connected with the power supply of the first preset reference voltage or connected with the first feedback resistance network; the source electrode or the drain electrode of the first power tube is externally connected with an input power supply, and the drain electrode or the source electrode is connected with the first feedback resistance network and the booster circuit; the first feedback resistance network is also connected with the booster circuit.
Preferably, the first power tube is a weak output power tube.
The weak output power transistor is referred to as a power transistor because it is applied to power conversion, since it is not substantially different from the second power transistor and other MOS transistors used in the design. The maximum difference between the weak output power tube and the second power tube lies in that the output power requirement is different, so that the size of the weak output power tube is far smaller than that of the second power tube.
Preferably, when the first power transistor is a PMOS transistor, the negative electrode of the first error amplifier is externally connected with a power supply of a first preset reference voltage, and the positive electrode of the first error amplifier is connected with the first feedback resistance network; the source electrode of the first power tube is externally connected with an input power supply, and the drain electrode of the first power tube is connected with the first feedback resistance network and an external load; the first feedback resistance network is also externally connected with a load; when the first power tube is an NMOS tube, the cathode of the first error amplifier is connected with the first feedback resistance network, and the anode of the first error amplifier is externally connected with a power supply with a first preset reference voltage; the drain electrode of the first power tube is externally connected with an input power supply, and the source electrode of the first power tube is connected with the first feedback resistance network and the booster circuit; the first feedback resistance network is also connected with the booster circuit.
Preferably, the voltage boost circuit is specifically configured to boost the input voltage input by the voltage regulation circuit by twice to obtain the first target voltage or the second target voltage, and input the first target voltage or the second target voltage to the L DO circuit.
Preferably, as shown in fig. 3, the boost circuit includes a double-fold-piracy charge pump, and a first energy storage capacitor, a second energy storage capacitor and a filter capacitor respectively connected to the double-fold-piracy charge pump, the double-fold-piracy charge pump is further connected to the voltage regulation circuit and the L DO circuit respectively, and is configured to perform double-fold boosting on an input voltage input by the voltage regulation circuit to obtain a first target voltage or a second target voltage and input the first target voltage or the second target voltage to the L DO circuit, the first energy storage capacitor and the second energy storage capacitor are further externally connected to an asynchronous square wave pulse modulation circuit respectively, and are configured to store square wave information of two asynchronous square waves input by the asynchronous square wave pulse modulation circuit, so as to assist the double-fold-piracy charge pump to perform boosting operation on the input voltage input by the voltage regulation circuit, and the filter capacitor is further connected to the L DO circuit and is externally grounded, and is configured to eliminate glitches and ripples of the first target voltage and the second target.
Preferably, the peak values of the two asynchronous pulsed square waves are both equal to the value of the input voltage to the power supply.
For example, fig. 3 shows a specific embodiment of a power supply circuit, which includes an error amplifier 201, a weak output power transistor 202, and voltage dividing resistors R21 and R22, which form a weak output low dropout linear regulator, and the main function of this part is to adjust the input voltage VDD to vdd.r according to the requirement of the application by using a reference voltage; the asynchronous square wave pulse modulation 204 consists of two inverters INV1 and INV2, and the part has the function of modulating the peak-to-peak value of the input square wave pulse, so as to achieve the purpose of controlling the output voltage; the role of the part of the piracy charge pump and filter capacitor 203 is to boost the modulated voltage vdd.r and the pulse square wave with the peak value of vdd.r by two times, and finally output a proper voltage VS to power the error amplifier 102 of the main circuit. The connection details of the circuit are shown in the figure and are not described herein.
In summary, the power circuit needs a reference voltage and two asynchronous pulse square waves as input, and the three input signals can be generated internally or input externally. The voltage-stabilizing regulating circuit can be a low-dropout linear voltage regulator with weak output.
A first preset reference voltage at one end of the voltage-stabilizing regulating circuit can be given, when the input voltage is lower than the value, the input voltage is subjected to voltage doubling and boosting through the boosting circuit, the power supply voltage for the first error amplifier is output, and the input voltage is doubled at the moment; when the input voltage is higher than the first preset reference voltage, the voltage-stabilizing regulating circuit starts to work, so that the peak value of the input of the double charge pump is equal to the reference voltage, and the power supply voltage output to the first error amplifier is twice the reference voltage at the moment. By properly selecting the value of the first preset reference voltage, the first error amplifier can be ensured to normally work at a lower input voltage and is not broken down at a higher input voltage.
EXAMPLE III
On the basis of the first or second embodiment, as shown in fig. 4 and 5, the L DO circuit includes a second error amplifier, a second power transistor, and a second feedback resistor network, wherein an input terminal of the second error amplifier is connected to the power circuit, an output terminal of the second error amplifier is connected to a gate of the second power transistor, a negative terminal of the second error amplifier is connected to the second feedback resistor network or a power source externally connected to a second predetermined reference voltage, a positive terminal of the second error amplifier is externally connected to the power source of the second predetermined reference voltage or the first feedback resistor network, a source or a drain of the second power transistor is externally connected to the input power source, and a drain or a source of the second power transistor is connected to the second feedback resistor network and an external load, and the second feedback resistor network is further externally connected to the load.
Preferably, as shown in fig. 4, when the second power transistor is a PMOS transistor, the negative electrode of the second error amplifier is externally connected to a power supply with a second preset reference voltage, and the positive electrode of the second error amplifier is connected to the second feedback resistor network; the source electrode of the second power tube is externally connected with an input power supply, and the drain electrode of the second power tube is connected with the second feedback resistance network and an external load; the second feedback resistance network is also externally connected with a load.
As shown in fig. 5, when the second power transistor is an NMOS transistor, the cathode of the second error amplifier is connected to the second feedback resistor network, and the anode is externally connected to a power supply with a second preset reference voltage; the drain electrode of the second power tube is externally connected with an input power supply, and the source electrode of the second power tube is connected with the second feedback resistance network and an external load; the second feedback resistance network is also externally connected with a load.
It should be noted that the energy conversion efficiency of the L DO circuit is ensured by directly connecting the input power supply or the front stage circuit with the second power tube, and the power supply circuit supplies power to the second error amplifier, so that the L DO circuit can continuously maintain high performance under the condition of ultra-low voltage input.
The power supply circuit has an input terminal connected to the input voltage of L DO (i.e., the input power supply) and an output terminal connected to the supply voltage terminal of the second error amplifier, the power supply circuit is configured to provide power to the second error amplifier such that the second error amplifier in L DO operates properly even at ultra-low input voltages.
When the load current changes, the output voltage (namely the required voltage) of the L DO circuit changes, the change is linearly conducted to the first error amplifier through the first feedback resistance network, the first error amplifier compares the change with the preset reference voltage, the change is acted on the grid voltage of the first power tube, and then the purpose of voltage stabilization is achieved through the first power tube.
Fig. 5 is modified on the basis of fig. 4, in which the second power tube component is changed from PMOS to NMOS, and signals at the positive and negative input ends of the second error amplifier are exchanged. Due to the special property of the NMOS, the supply voltage of the second error amplifier is required to be higher than that of the second power transistor to ensure that the turn-on voltage drop of the NMOS power transistor is reduced. On the other hand, since the NMOS has a larger mobility and a higher intrinsic gain, the area of the NMOS power transistor is greatly reduced compared to the PMOS when the NMOS outputs a load current of the same magnitude. Meanwhile, because the difference value between the output voltage and the power supply voltage of the second error amplifier is more than 300mV, the resistor feedback network can be cancelled, and the output end of the resistor feedback network is directly connected with the input of the negative end of the second error amplifier.
In the embodiment of the present invention, the second error amplifier is used to adjust the output of the second power transistor, the second error amplifier can adopt the existing two-stage CMOS operational amplifier structure, the compensation capacitor of the system is not shown in the figure,
it should be noted that, because the output current of the power circuit is small, the output power is small, and the power circuit has a small volume, and occupies a small area of the ultra-low voltage L DO circuit, the power circuit of the present invention is a lightweight power circuit.
The L DO circuit is manufactured by adopting a 130nm process of Taiwan Leihua electronics company, and when a first preset reference voltage VREF is 0.6V, the whole L DO circuit can output 0.4V-1.1V of high-performance output voltage at 0.5V-1.2V of input voltage, and can be lower by more advanced processes, so that for L DO circuits with other excellent performances, the capability of working at low voltage can be obtained by the method for reducing the input voltage range provided by the invention, and other excellent performances are kept at the same time, therefore, the minimum range of the input voltage of the ultralow voltage L DO is 0.5V-1.2V.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. An ultra-low voltage L DO circuit is characterized in that the circuit is used in an integrated circuit working environment with ultra-low or wide voltage range and comprises a L DO circuit and a power supply circuit, wherein the input end of the power supply circuit and the first input end of the L DO circuit are used for externally inputting a power supply, and the output end of the power supply circuit is connected with the second input end of the L DO circuit;
the power supply circuit is used for judging whether the received input voltage is smaller than a first preset reference voltage, if so, performing multiple boosting processing on the input voltage to obtain a first target voltage and inputting the first target voltage to the L DO circuit, and if not, performing voltage stabilization and multiple boosting processing on the input voltage in sequence to obtain a second target voltage and inputting the second target voltage to the L DO circuit, wherein the first target voltage and the second target voltage are both used for supplying power to the L DO circuit;
the L DO circuit is used for processing the input voltage received by the first input end of the L DO circuit to obtain a required voltage based on a second preset reference voltage and outputting the required voltage.
2. The ultra-low voltage L DO circuit of claim 1, wherein the power supply circuit comprises a regulation circuit and a boost circuit;
the input end of the voltage stabilizing and adjusting circuit is the input end of the power supply circuit and is used for judging whether the received input voltage is smaller than a first preset reference voltage or not, and if so, the input voltage is input to the booster circuit; if not, stabilizing the value of the input voltage to the value of the first preset reference voltage to obtain a new input voltage and inputting the new input voltage to the booster circuit;
and the output end of the boost circuit is the output end of the power supply circuit, and is used for boosting the input voltage input by the voltage stabilization regulating circuit by multiple times to obtain the first target voltage or the second target voltage and inputting the first target voltage or the second target voltage to the L DO circuit.
3. The ultra-low voltage L DO circuit of claim 2, wherein the regulator circuit comprises a first error amplifier, a first power transistor, and a first feedback resistor network;
the first error amplifier is externally connected with the input power supply, and the output end of the first error amplifier is connected with the grid electrode of the first power tube; the negative electrode of the first error amplifier is connected with the first feedback resistance network or a power supply for externally connecting the first preset reference voltage, and the positive electrode of the first error amplifier is connected with the power supply for externally connecting the first preset reference voltage or the first feedback resistance network; the source electrode or the drain electrode of the first power tube is used for being externally connected with the input power supply, and the drain electrode or the source electrode is connected with the first feedback resistance network and the booster circuit; the first feedback resistance network is also connected with the booster circuit.
4. The ultra-low voltage L DO circuit of claim 3, wherein the first power transistor is a weak output power transistor.
5. The ultra-low voltage L DO circuit of claim 3, wherein when the first power transistor is a PMOS transistor, a negative electrode of the first error amplifier is externally connected to a power supply of the second preset reference voltage, and a positive electrode of the first error amplifier is connected to the first feedback resistor network;
when the first power tube is an NMOS tube, the negative electrode of the first error amplifier is connected with the first feedback resistance network, and the positive electrode of the first error amplifier is externally connected with a power supply of the first preset reference voltage; the drain electrode of the first power tube is used for being externally connected with the input power supply, and the source electrode of the first power tube is connected with the first feedback resistance network and the booster circuit; the first feedback resistance network is also connected with the booster circuit.
6. The ultra-low voltage L DO circuit of claim 2, wherein the boost circuit is specifically configured to boost the input voltage inputted from the regulator circuit by twice, obtain the first target voltage or the second target voltage, and input the first target voltage or the second target voltage to the L DO circuit.
7. The ultra-low voltage L DO circuit of claim 6, wherein the boost circuit comprises a double-piracy charge pump, and a first energy storage capacitor, a second energy storage capacitor and a filter capacitor respectively connected to the double-piracy charge pump;
a first input end of the double-rate Pirikeley charge pump is connected with the voltage-stabilizing regulating circuit, a second input end of the double-rate Pirikeley charge pump is an output end of the power supply circuit, and the double-rate Pirikeley charge pump is used for boosting the input voltage input by the voltage-stabilizing regulating circuit by two times to obtain the first target voltage or the second target voltage and inputting the first target voltage or the second target voltage to the L DO circuit;
the first energy storage capacitor and the second energy storage capacitor are also used for being externally connected with an asynchronous square wave pulse modulation circuit so as to store square wave information of two asynchronous square wave pulses input by the asynchronous square wave pulse modulation circuit and assist the double-fold Pirikele charge pump to carry out boosting operation;
the filter capacitor is further connected with the L DO circuit and is used for eliminating burrs and ripples of the first target voltage and the second target voltage.
8. The ultra-low voltage L DO circuit of claim 7, wherein the peak values of said two asynchronous pulsed square waves are both equal to the value of the input voltage of said input power source.
9. The ultra low voltage L DO circuit of claim 3, wherein the L DO circuit comprises a second error amplifier, a second power transistor, and a second feedback resistor network;
the input end of the second error amplifier is a second input end of the L DO circuit, the output end of the second error amplifier is connected with the grid electrode of the second power tube, the negative electrode of the second error amplifier is connected with the second feedback resistance network and used for being externally connected with a power supply of a second preset reference voltage, the positive electrode of the second error amplifier is used for being externally connected with the power supply of the second preset reference voltage or connected with the first feedback resistance network, the source electrode or the drain electrode of the second power tube is a first input end of the L DO circuit, the drain electrode or the source electrode of the second error amplifier is connected with the second feedback resistance network and used for being externally connected with a load, and the second feedback resistance network is also used for being.
10. The ultra-low voltage L DO circuit of claim 9, wherein when said second power transistor is a PMOS transistor, said second error amplifier has a negative electrode for externally connecting to a power supply of said second predetermined reference voltage and a positive electrode connected to said second feedback resistor network, said second power transistor has a source electrode for a first input terminal of said L DO circuit and a drain electrode connected to said second feedback resistor network for externally connecting to said load, said second feedback resistor network further for externally connecting to said load;
when the second power tube is an NMOS tube, the negative electrode of the second error amplifier is connected with the second feedback resistance network, the positive electrode of the second error amplifier is used for being externally connected with a power supply of the second preset reference voltage, the drain electrode of the second power tube is the first input end of the L DO circuit, the source electrode of the second power tube is connected with the second feedback resistance network and is used for being externally connected with the load, and the second feedback resistance network is also used for being externally connected with the load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910139295.3A CN109871059B (en) | 2019-02-25 | 2019-02-25 | Ultralow voltage L DO circuit |
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| CN111399578A (en) * | 2020-04-22 | 2020-07-10 | 安徽华夏显示技术股份有限公司 | Airborne low-voltage stabilization control circuit |
| CN114003081B (en) * | 2021-10-29 | 2022-07-05 | 华中科技大学 | Digital LDO circuit with low-voltage ripple output |
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| CN2826827Y (en) * | 2005-09-29 | 2006-10-11 | 李自祥 | Low-power consumption six wire internal earth voltage regulator with overcurrent and overvoltage protection function |
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| 基于电容倍增技术的LDO补偿方法;应建华等;《微电子学与计算机》;20091105;第26卷(第11期);第102-105页 * |
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