CN201527594U - Ultra-low dropout and high-driving power linear voltage regulator - Google Patents

Abstract

The utility model discloses an ultra-low dropout and high-driving power linear voltage regulator which is based on a circuit formed by a driving circuit (Buffer) (3), a feedback network (4) with resistance voltage-division, an error amplifier (2), a reference circuit (1) and a load (5); and the linear voltage regulator is characterized in that the regulator also comprises an NMOS output pipe (7) and a positive boosting charge pump circuit (8), wherein the NMOS output pipe (7) is configured to receive a voltage signal output by the driving circuit (Buffer) (3) and provide corresponding currents for the load (5); and the positive boosting charge pump circuit (8) is configured to receive a voltage signal VIN outside the linear voltage regulator and supply power for the driving circuit (Buffer) (3). The ultra-low dropout and high-driving power linear voltage regulator is especially applicable to circumstances that an input voltage and an output voltage are close, can supply higher driving power, and remarkably improves efficiency. Therefore, on the premise of guaranteeing two performances of low voltage drop and strong drive, the ultra-low dropout and high-driving power linear voltage regulator saves the area of a chip, saves cost and has stronger implementation.

Description

The linear voltage regulator of a kind of ultra low differential pressure and big driving force

Affiliated technical field

The utility model relates to Analogous Integrated Electronic Circuits, belongs to a kind of linear voltage regulator, the linear voltage regulator of especially a kind of ultra low differential pressure and big driving force.

Background technology

Linear voltage regulator (Low Dropout Regulator) belongs to a kind of of power management IC, is widely used in the portable set.Than DC-DC (DC-to-dc) converter that uses inductance, it has that cost is low, noise is low and characteristics such as quiescent current is low, simultaneously owing to there is not inductance, does not also have the EMI problem.

The conventional linear voltage stabilizer is usually by the PMOS efferent duct, driving circuit (Buffer), and the feedback network of electric resistance partial pressure, error amplifier and reference circuit are formed.Reference circuit adopts band-gap reference (Bandgap reference) usually, and this module produces a reference potential that changes with working environments such as temperature and power supplys hardly.Output voltage VO UT samples by divider resistance R1, R2, and with the positive input of this signal feedback to error amplifier.The negative input of error amplifier connects reference voltage simultaneously, and the output of error amplifier connects the grid of PMOS efferent duct.When other conditions variations of external loading conditioned disjunction cause linear stabilizer output voltage to change, the output of error amplifier also can change accordingly, adjust the conducting state (similar variable resistor) of PMOS output, and then guarantee that output voltage gets back to steady state (SS).Load capacitance CL is used for a such closed loop feedback system of auxiliary control and keeps stable under various applicable cases, and RL is an equivalent load resistance.

The driving force of linear voltage regulator is determined by following formula:

V _DS＞(V _GS-V _TH), the conducting electric current of saturation region PMOS efferent duct satisfies:

$I_D=\frac{1}{2}{\mathrm{\μ}}_P{C}_{\mathrm{OX}}\frac{W}{L}{(V_{\mathrm{SG}}-V_{\mathrm{TH}})}^2$ Formula [1]

μ _pBe the mobility of holoe carrier, C _OXBe the gate oxide electric capacity of unit area, W/L is the breadth length ratio of efferent duct, V _SGFor the gate source voltage of PMOS pipe poor, V _THBe the PMOS pipe threshold.

In order to improve the driving force of PMOS efferent duct, can pass through increases breadth length ratio W/L, but the breadth length ratio increase will increase chip area usually, can bring the increase of chip cost like this, bigger breadth length ratio means bigger stray capacitance simultaneously, can influence the response speed of linear voltage regulator.

NMOS guarantees adequate food and the conducting electric current satisfies: (V _DS＞V _GS-V _THUnder the condition)

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\frac{W}{L}{(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2$ Formula [2]

μ _nBe the mobility of electronic carrier, usually μ _nCompare μ _pGreatly, under same breadth length ratio situation, adopting the NMOS pipe to do driving tube can significantly improve than PMOS driving tube driving force so.

The linear voltage regulator circuit diagram 2 of existing NMOS efferent duct.

Linear voltage regulator pressure drop V _DROPOUTFor:

Linear voltage regulator input voltage V _INWhen dropping to certain critical value, system loses the regulating power to output voltage, V _DROPOUTBe defined as the difference of critical point place input voltage and output voltage.

Do not consider inner static current consumption, the transformation efficiency of linear voltage regulator is:

$\mathrm{\η}=\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IV}}}\×100\%$ Formula [3]

V _INBe linear voltage regulator input voltage, V _OUTBe linear stabilizer output voltage.

Can see, at identical V _OUTSituation under, VIN is low more, efficient is high more.But descending, at V along with VIN _INNear V _OUTThe time, ignore driving circuit pressure drop V _DS(P), approximate have a V _G≈ V _IN, so:

V _DS=V _IN-V _OUTFormula [4]

V _GS-V _TH=V _IN-V _OUT-V _THFormula [5]

Can not satisfy V _DS≤ V _GS-V _THFormula [6]

Promptly can not enter linear zone.

Mean pressure drop V _DROPOUTBe approximately:

V _DROPOUT≈ V _GS+ V _DS(P) formula [7]

V wherein _DS(P) be the pressure drop of driving stage (Buffer).

The pressure drop V that ignores driving stage (Buffer) _DS(P), approximate have:

V _DROPOUT≈ V _GSFormula [8]

Directly adopt NMOS to cause linear voltage regulator pressure drop height, can not satisfy the occasion that efficient is had relatively high expectations.Therefore, in order to overcome above-mentioned shortcoming, existing linear voltage regulator is improved with regard to being necessary very much.

The utility model content

The purpose of this utility model is to overcome the existing deficiency of above-mentioned existing linear voltage regulator circuit, thereby the linear voltage regulator of a kind of NMOS of employing driving tube and charge pump booster circuit is provided, and can satisfy ultra low differential pressure and big driving force simultaneously.

The utility model provides the linear voltage regulator of a kind of ultra low differential pressure and big driving force, based on by driving circuit (Buffer) (3), the feedback network of electric resistance partial pressure (4), error amplifier (2), reference circuit (1), the circuit that load (5) is formed is characterized in that also comprising NMOS efferent duct (7) and forward boosted charge pump circuit (8), wherein:

NMOS efferent duct (7) is configured to accept the voltage signal of driving circuit (Buffer) (3) output, and provides corresponding electric current to load (5);

Forward boosted charge pump circuit (8) is configured to accept the voltage signal VIN of linear voltage regulator outside, and is driving circuit (Buffer) (3) power supply.

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, NMOS efferent duct (7) is configured to the output terminal that grid connects driving circuit (Buffer) (3), the voltage signal VIN of drain connection voltage stabilizer outside, source electrode connects the common VOUT output terminal of feedback network (4) of load (5) and electric resistance partial pressure, and substrate links to each other with source electrode.

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, NMOS efferent duct (7) on the make must adopt P trap technology.

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, forward boosted charge pump circuit (8) is configured to accept the voltage signal VIN of linear voltage regulator outside, and carries out boost operations, and output voltage is N (N＞1) VIN doubly, i.e. N*VIN;

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, the output voltage of forward boosted charge pump circuit (8) is driving circuit (Buffer) (3) power supply;

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, driving circuit (Buffer) (3) is configured to be powered by forward boosted charge pump circuit (8), reception is from the control signal of error amplifier (2), and the control signal of output NMOS efferent duct (7).

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, driving circuit (Buffer) (3) is configured to by forward boosted charge pump circuit (8) power supply, and its output voltage is used for the grid of driving N MOS efferent duct (7).

At the above-mentioned ultra low differential pressure and the linear voltage regulator of big driving force, the grid of NMOS efferent duct (7) is configured to maximum potential can reach N (N＞1) VIN doubly, i.e. N*VIN.

Owing to adopt above-mentioned solution, than the linear voltage regulator that drives of existing P MOS and the linear voltage regulator that drives of NMOS separately, introduce NMOS driving tube and charge pump booster circuit simultaneously, can have the strong driving force of NMOS simultaneously concurrently than PMOS, and low two advantages of pressure drop of linear voltage regulator, thereby be particularly suitable for the approaching occasion of input voltage and output voltage, and can provide stronger driving force again, significantly promote efficient.Therefore the utility model can be saved chip area under the prerequisite that guarantees above two kinds of performances, saves cost, and has very strong exploitativeness.

With reference to following detailed description and accompanying drawing, can more fully understand various other purpose of the present utility model, feature and advantage.

Description of drawings

Fig. 1 is an existing P MOS linear voltage regulator schematic diagram;

Fig. 2 is the linear voltage regulator of the existing NMOS of use;

Fig. 3 is that the NMOS of the band forward boosting charge pump of the utility model use strengthens the driving linear voltage regulator;

Fig. 4 is the preferred circuit of 2 times of forward charge pumps of the utility model use.

Embodiment

The utility model provides the linear voltage regulator (Fig. 3) of a kind of ultra low differential pressure and big driving force, based on by driving circuit (Buffer) (3), the feedback network of electric resistance partial pressure (4), error amplifier (2), reference circuit (1), the circuit that load (5) is formed is characterized in that also comprising NMOS efferent duct (7) and forward boosted charge pump circuit (8), wherein:

NMOS efferent duct (7) is configured to accept the voltage signal of driving circuit (Buffer) (3) output, and provides corresponding electric current to load (5);

Forward boosted charge pump circuit (8) is configured to accept the voltage signal VIN of linear voltage regulator outside, and is driving circuit (Buffer) (3) power supply.

Promote NMOS driving tube grid current potential by introducing charge pump circuit (Chargepump), can fine solution adopt NMOS to cause the high problem of linear voltage regulator pressure drop, and can promote driving force.

V for example _INThe xN of power supply charge pump circuit doubly can provide NV _INVoltage, for example 1.5 times, 2 times, 3 times etc.For example adopt fairly simple 2 times of forward charge pumps (as Fig. 4), only need 2 little stray capacitances and ring oscillator, just can be in CMOS technology fine realization boost function.

INV1 among Fig. 4～INV5 phase inverter looping oscillator, output control signal Φ and Gauge tap S1 and S2 reach V respectively _INBoost to V _CP=2V _INPurpose.

So

V _G(max) can be near NV _IN, satisfy:

V _DS=V _IN-V _OUT≤ NV _IN-V _OUT-V _TH=V _GS-V _THFormula [9]

V _DS≤(V _GS-V _TH)

Promptly enter linear zone, NMOS pipe conducting resistance R _ONFor:

$R_{\mathrm{ON}}=\frac{1}{{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\frac{W}{L}(V_{\mathrm{GS}}-V_{\mathrm{TH}})}$ Formula [10]

Can notice V _GS=V _G-V _OUT, NMOS manages grid current potential V so _GHigh more, R _ONJust more little.

Pressure drop V _DROPOUTFor:

$V_{\mathrm{DROPOUT}}=R_{\mathrm{ON}}\·I_{\mathrm{OUT}}=\frac{I_{\mathrm{OUT}}}{{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\frac{W}{L}(V_{\mathrm{GS}}-V_{\mathrm{TH}})}$ Formula [11]

I _OUTBe load current, same load current is as NMOS pipe grid current potential V _GHigh more, R _ONJust more little, while V _DROPOUTAlso more little, V _INMore near V _OUTThereby, raise the efficiency.

There is charge pump to power: V _GS1=NV _IN-V _OUTFormula [12]

Contrast does not have among Fig. 2 of charge pump power supply: V _GS2=V _IN-V _OUTFormula [13]

V _GS＞V _GS2Formula [14]

In conjunction with formula [2] $I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\frac{W}{L}{(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2$

Under same VOUT condition, the maximum current drive ability of NMOS is along with V _GSLifting, also can promote.

Therefore, using the NMOS efferent duct and having the linear voltage regulator of forward boosting charge pump, compare the linear voltage regulator of PMOS efferent duct and the linear voltage regulator of common NMOS efferent duct, under the same chip size, current driving ability can be significantly promoted, and V can be significantly reduced _DROPOUTVoltage makes input and output voltage more approaching, significantly promotes efficient.

On process choice, adopt P trap CMOS technology, NMOS pipe source and substrate connect together, eliminate the influence of the inclined to one side effect of lining to threshold value.Utilize formula

$V_{\mathrm{TH}}=V_{\mathrm{TH}0}+\mathrm{\γ}(\sqrt{|2{\mathrm{\Φ}}_F+V_{\mathrm{SB}}|}-\sqrt{\left|2{\mathrm{\Φ}}_F\right|})$ Formula [15]

V _TH0Grid voltage when the electron concentration that is defined as the interface equals the majority carrier density of p type substrate, γ is a body-effect coefficient, | 2 Φ F| are surperficial transoid gesture, V _SBBe source lining electric potential difference.

Work as V _SB=0 o'clock, V _TH=V _THO, can eliminate of the influence of the inclined to one side effect of lining to threshold value.

Introduce work engineering of the present utility model below in conjunction with Fig. 3:

The linear voltage regulator of ultra low differential pressure and big driving force comprises the NMOS efferent duct, driving circuit (Buffer), the feedback network of electric resistance partial pressure, error amplifier, reference circuit, load and forward boosted charge pump circuit.

The feedback network of electric resistance partial pressure is connected between NMOS efferent duct and the error amplifier, and the size according to NMOS efferent duct output current provides output voltage, and feedback voltage V FB is provided the inverting input to error amplifier.Feedback network adopts resistance R 1 and R2 divider resistance to constitute, and R1 is connected between VOUT and the VFB, and R2 is connected between VFB and the GND, and the ratio that can be obtained between output voltage VO UT and the feedback voltage V FB by Fig. 3 is VOUT=(1+R1/R2) VFB.

The positive termination reference voltage V REF of error amplifier, negative termination feedback voltage V FB by comparing VREF and VFB, exports suitable voltage to driving circuit (Buffer), plays control NMOS efferent duct gate voltage, and then regulated output voltage.

Driving circuit (Buffer) is to be used for direct driving N MOS efferent duct, because NMOS efferent duct size is generally all bigger, stray capacitance is obvious, in order to improve response speed, must add driving circuit (Buffer).This routine driving circuit adopts the power supply of forward boosting charge pump in addition, and can guarantee like this provides the current potential that is higher than input voltage VIN for the grid of NMOS efferent duct, thereby guarantees the ultra low differential pressure and the big driving force of this linear voltage regulator.

Reference circuit is that the positive terminal for error amplifier provides reference potential, to guarantee suitable output voltage.Adopt band-gap reference circuit in this example, the reference voltage with good temperature characteristics and power supply characteristic can be provided.

The voltage signal VIN of forward boosted charge pump circuit acceptance line voltage stabilizer outside, through boost operations, output voltage is N (N＞1) VIN doubly, be N*VIN, and be driving circuit (Buffer) (3) power supply, thereby promote NMOS driving tube grid current potential, can fine solution adopt NMOS to cause the high problem of linear voltage regulator pressure drop, and can promote driving force.

The utlity model has lot of advantages.Than the linear voltage regulator that drives of existing P MOS and the linear voltage regulator that drives of NMOS separately, introduce NMOS driving tube and charge pump booster circuit simultaneously, can have the strong driving force of NMOS simultaneously concurrently than PMOS, and low two advantages of pressure drop of linear voltage regulator, thereby be particularly suitable for the approaching occasion of input voltage and output voltage, and can provide stronger driving force again, significantly promote efficient.Therefore the utility model can be saved chip area under the prerequisite that guarantees above two kinds of performances, saves cost, and has very strong exploitativeness.

Above embodiment is only for the usefulness that the utility model is described, but not to restriction of the present utility model, person skilled in the relevant technique, under the situation that does not break away from spirit and scope of the present utility model, can also make various conversion or modification, therefore all technical schemes that are equal to also should belong within the category of the present utility model, should be limited by each claim, and include within the scope of claim.

Claims (6)

1. the linear voltage regulator of a ultra low differential pressure and big driving force, based on by driving circuit (3), the feedback network of electric resistance partial pressure (4), error amplifier (2), reference circuit (1), the circuit that load (5) is formed is characterized in that also comprising NMOS efferent duct (7) and forward boosted charge pump circuit (8), wherein:

NMOS efferent duct (7) is configured to accept the voltage signal of driving circuit (3) output, and provides corresponding electric current to load (5);

Forward boosted charge pump circuit (8) is configured to accept the voltage signal VIN of linear voltage regulator outside, and is driving circuit (3) power supply.

2. the linear voltage regulator of ultra low differential pressure according to claim 1 and big driving force, it is characterized in that, described NMOS efferent duct (7) is configured to the output terminal that grid connects driving circuit (3), the voltage signal VIN of drain connection voltage stabilizer outside, source electrode connects the common VOUT output terminal of feedback network (4) of load (5) and electric resistance partial pressure, and substrate links to each other with source electrode.

3. the linear voltage regulator of ultra low differential pressure according to claim 1 and big driving force, it is characterized in that, described forward boosted charge pump circuit (8), be configured to accept the voltage signal VIN of linear voltage regulator outside, and carry out boost operations, output voltage is N (N＞1) VIN doubly, i.e. N*VIN.

4. the linear voltage regulator of ultra low differential pressure according to claim 1 and big driving force is characterized in that, the output voltage of forward boosted charge pump circuit (8) is driving circuit (3) power supply.

5. the linear voltage regulator of ultra low differential pressure according to claim 1 and big driving force, it is characterized in that, driving circuit (3) is configured to receive the control signal from error amplifier (2) by forward boosted charge pump circuit (8) power supply, and the control signal of output NMOS efferent duct (7).

6. the linear voltage regulator of ultra low differential pressure according to claim 1 and big driving force is characterized in that, driving circuit (3) is configured to by forward boosted charge pump circuit (8) power supply, and its output voltage is used for the grid of driving N MOS efferent duct (7).

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