SG11201901196RA - Wafer-level package with enhanced performance - Google Patents

Wafer-level package with enhanced performance

Info

Publication number
SG11201901196RA
SG11201901196RA SG11201901196RA SG11201901196RA SG11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA SG 11201901196R A SG11201901196R A SG 11201901196RA
Authority
SG
Singapore
Prior art keywords
international
redistribution
thinned die
mold compound
multilayer
Prior art date
Application number
SG11201901196RA
Inventor
Jan Vandemeer
Jonathan Hammond
Julio Costa
Original Assignee
Qorvo Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qorvo Us Inc filed Critical Qorvo Us Inc
Publication of SG11201901196RA publication Critical patent/SG11201901196RA/en

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    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00777—Preserve existing structures from alteration, e.g. temporary protection during manufacturing
    • B81C1/00785—Avoid chemical alteration, e.g. contamination, oxidation or unwanted etching
    • B81C1/00801—Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
    • B81B7/0025—Protection against chemical alteration
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
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    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
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    • B81B2207/11—Structural features, others than packages, for protecting a device against environmental influences
    • B81B2207/115—Protective layers applied directly to the device before packaging
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  • Micromachines (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -C.-- -.` 1#11111110111010101111101 1010 01111 OM 0111110111011101110111011# Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .../ WO 2018/031999 Al 15 February 2018 (15.02.2018) WIP0 I PCT (51) International Patent Classification: (72) Inventors: HO1L 23/31 (2006.01) H01L 21/60 (2006.01) erfield Lane, HO1L 21/56 (2006.01) HAMMOND, (21) International Application Number: Oak Ridge, PCT/US2017/046779 6601 Ashton (US). (22) International Filing Date: (74) Agent: WITHROW, 14 August 2017 (14.08.2017) va, P.L.L.C., (25) Filing Language: English olina 27511 (26) Publication Language: English (81) Designated kind of national (30) Priority Data: AO, AT, AU, 62/374,447 12 August 2016 (12.08.2016) US CA, CH, CL, (71) Applicant: QORVO US, INC. [US/US]; 7628 Thorndike DZ, EC, EE, Road, Greensboro, North Carolina 27409 (US). HR, HU, ID, IL, IN, KR, KW, MG, MK, North Carolina 27310 (US). COSTA, Julio, C.; Park Drive, Oak Ridge, North Carolina 27310 VANDEMEER, Kernersville, Jonathan, Jan, Edward; 279 Weath- North Carolina 27284 (US). Hale; 5808 Autumn Gate Drive, Benjamin, S.; Withrow & Terrano- Pinedale Springs Way, Cary, North Car- (unless otherwise indicated, for every available): AE, AG, AL, AM, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, ES, FI, GB, GD, GE, GH, GM, GT, HN, IR, IS, JO, JP, KE, KG, KH, KN, KP, LC, LK, LR, LS, LU, LY, MA, MD, ME, MX, MY, MZ, NA, NG, NI, NO, NZ, protection 106 (US). States AZ, CN, EG, KZ, LA, MN, MW, (54) Title: WAFER — -LEVEL PACKAGE WITH ENHANCED PERFORMANCE 2 38 42 redistribution layer (24) the first device between the redistribution within the the top surface = = _ = — = = = 24 : 6 . „ = = . . ' . = 18 : (18), from to package and mold compound and over the first thinned die. the first thinned die. (57) 01 structure M redistribution interconnects and --.... structure W . 7 7: / t , . ,,, , . . 6 L y c l +.,,,,, , AV • 0 6 ••. . , -- 4 l ' 40 ,,,, ;/07. 7 . '-', /-:1-. % J = 46 44 The present disclosure relates to a wafer-level package that includes a first thinned die (12), a a first mold compound glass materials. contacts (44) around the first thinned die, and extends A (20), and The multilayer redistribution on a bottom surface the first device layer are solder-free. The first mold compound resides over the 44 46 44 46 FIG. i a second mold compound (22). The first thinned die includes a first device structure includes redistribution interconnects that of the multilayer redistribution beyond a top surface of the first thinned die to define The second mold compound fills the opening and is in contact 44 46 44 multilayer connect multilayer an opening with = = = ,-1 C'N formed 01 ,1 layer 0 GC first 1-1 C of N structure. Herein, the connections C [Continued on next page] WO 2018/031999 Al MIDEDIMOMOIDEIREEMODHOMMEHOHOMEin OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3)) — with amended claims and statement (Art. 19(1))
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