CN113594295A - Preparation method of solar cell with double-sided passivation structure - Google Patents
Preparation method of solar cell with double-sided passivation structure Download PDFInfo
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- CN113594295A CN113594295A CN202110836421.8A CN202110836421A CN113594295A CN 113594295 A CN113594295 A CN 113594295A CN 202110836421 A CN202110836421 A CN 202110836421A CN 113594295 A CN113594295 A CN 113594295A
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- 238000002161 passivation Methods 0.000 title claims abstract description 94
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 57
- 239000010703 silicon Substances 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 238000011065 in-situ storage Methods 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 230000005641 tunneling Effects 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 238000000992 sputter etching Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 239000002131 composite material Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 87
- 238000010586 diagram Methods 0.000 description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000005922 Phosphane Substances 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910000085 borane Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000064 phosphane Inorganic materials 0.000 description 1
- 238000013082 photovoltaic technology Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a preparation method of a solar cell with a double-sided passivation structure, which is characterized by comprising the following steps of: s100, selecting a silicon wafer as a silicon substrate of the battery, and performing texturing or polishing treatment on the front surface and the back surface of the silicon substrate; s200, manufacturing a first silicon oxide passivation layer on the front surface and the back surface of the silicon substrate, and forming a polysilicon layer on the first silicon oxide passivation layer; s300, carrying out N-type in-situ doping treatment on the polycrystalline silicon layer to generate an N-type doped polycrystalline silicon passivation layer; and S400, forming an oxidation protection layer on the N-type doped polycrystalline silicon passivation layer. The invention provides a preparation method for manufacturing a solar cell forming structure, which can well form various layered structures on a silicon substrate, tunnel and passivate the contacted composite polycrystalline silicon passivation layer on the front side and the back side, and the prepared silicon bottom cell has high open circuit voltage, is particularly suitable for preparing a multi-junction laminated solar cell and has higher photoelectric conversion efficiency.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a solar cell with a double-sided passivation structure.
Background
Photovoltaic energy has been developed rapidly in recent years as one of the most important renewable energy sources. Solar cells are the most important part of photovoltaic energy systems, and improving the photoelectric conversion efficiency of the solar cells is the most important way to reduce the cost of photovoltaic energy.
At present, industrialized crystalline silicon photovoltaic cells are gradually close to the bottleneck, the efficiency improvement is small, and due to the higher limit efficiency of the laminated photovoltaic cells, the most favorable theoretical technical support is provided for reducing the power consumption cost of photovoltaic energy.
The perovskite material has the characteristics of low cost, adjustable band gap and the like, and the perovskite-crystalline silicon laminated solar cell combined with the silicon bottom cell can improve the efficiency limit of the silicon solar cell to more than 40 percent, so that the perovskite-crystalline silicon laminated solar cell is considered as the most promising next-generation photovoltaic technology in the photovoltaic industry.
In the existing crystalline silicon perovskite laminated solar cell, due to the limitation of the preparation process, the front surface of the bottom cell generally adopts an emitter which is polished and not passivated, so that the laminated voltage is low, and the integral photoelectric conversion efficiency is influenced. Based on the defects, a silicon bottom cell structure with double-sided tunneling passivation contact suitable for a multi-junction laminated solar cell needs to be redesigned, and a manufacturing process method is designed according to the structural characteristics of the silicon bottom cell structure.
Disclosure of Invention
In view of the above circumstances, the present invention provides a method for preparing a solar cell with a double-sided passivation structure, which comprises the following steps:
a preparation method of a solar cell with a double-sided passivation structure comprises the following steps:
s100, selecting a silicon wafer as a silicon substrate of the battery, and performing texturing or polishing treatment on the front surface and the back surface of the silicon substrate;
s200, manufacturing a first silicon oxide passivation layer on the front surface and the back surface of the silicon substrate, and forming a polysilicon layer on the first silicon oxide passivation layer;
s300, carrying out N-type in-situ doping treatment on the polycrystalline silicon layer to generate an N-type doped polycrystalline silicon passivation layer;
s400, forming an oxidation protection layer on the N-type doped polycrystalline silicon passivation layer;
s500, removing the oxidation protection layer, the N-type doped polycrystalline silicon passivation layer and the first silicon oxide passivation layer on one side of the back surface of the silicon substrate by an etching method until the silicon substrate forms a tunneling structure;
s600, removing the oxidation protection layer on one side of the front surface of the silicon substrate by an etching method until the N-type doped polycrystalline silicon passivation layer is formed to form a tunneling structure;
s700, manufacturing a second silicon dioxide passivation layer and a polysilicon passivation layer on one side of the front surface and one side of the back surface of the silicon substrate;
s800, carrying out P-type in-situ doping on the second polysilicon passivation layers formed on the two sides of the silicon substrate in the previous step to generate a P-type doped polysilicon passivation layer;
s900, manufacturing an antireflection layer on the P-type doped polycrystalline silicon passivation layer on the back side of the silicon substrate;
and S1000, manufacturing a metal bottom electrode layer on the antireflection layer obtained in the last step.
Further, in the step S200, the first silicon oxide passivation layer and the polysilicon layer, and the method for forming the oxidation protection layer in the step S400 adopt one or more of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, and a sputtering method.
Further, in the step S300, the process of generating the N-type doped polysilicon passivation layer includes a diffusion method.
Further, in the step S500, the etching method is one or both of ion etching and/or wet etching.
Further, in the step S600, the etching method is BOE/HF wet etching.
Further, in step S700, one or more of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, and a sputtering method is used to form the second silicon dioxide passivation layer and the polysilicon passivation layer.
Further, in the step S800, a method of performing P-type in-situ doping is a diffusion method.
Further, in the step S900, the manufacturing method of the anti-reflection layer includes one or both of atomic deposition or plasma enhanced chemical vapor deposition.
Further, in the step S900, the manufacturing method of the anti-reflection layer includes one or both of atomic deposition or plasma enhanced chemical vapor deposition.
Further, in the step S100, a manufacturing method of the metal bottom electrode layer includes one or more of evaporation, screen printing and electroplating.
Has the advantages that: the method can well form various layered structures on a silicon substrate, tunnel and passivate the contacted composite polycrystalline silicon passivation layer on the front side and the back side, the effect of the double-sided passivation structure of the silicon substrate layer can improve the open-circuit voltage of the silicon battery, the composite doped polycrystalline silicon passivation layer on the upper surface can be used as the middle tunneling layer of the laminated battery, and the prepared silicon bottom battery has high open-circuit voltage, is particularly suitable for preparing a multi-junction laminated solar battery and has higher photoelectric conversion efficiency.
Drawings
Fig. 1 is a schematic structural diagram formed after step S200 according to the present invention.
Fig. 2 is a schematic structural diagram formed after step S300 according to the present invention.
Fig. 3 is a schematic diagram of the structure formed after step S400 according to the present invention.
Fig. 4 is a schematic structural diagram formed after step S500 of the present invention.
Fig. 5 is a schematic structural diagram formed after step S600 of the present invention.
Fig. 6 is a schematic structural diagram formed after step S700 of the present invention.
Fig. 7 is a schematic structural diagram formed after step S800 according to the present invention.
Fig. 8 is a schematic structural diagram formed after step S1000 according to the present invention.
Detailed Description
The invention is further described in the following detailed description with reference to the drawings and examples as preferred embodiments:
referring to fig. 1 to 8, a method for manufacturing a solar cell with a double-sided passivation structure includes the following steps:
s100, selecting a silicon wafer as the silicon substrate 100 of the battery, and performing texturing or polishing treatment on the front surface and the back surface of the silicon substrate 100, wherein the silicon wafer is P-type silicon or N-type silicon;
s200, forming a first silicon oxide passivation layer 200 on the front and back surfaces of the silicon substrate 100, and forming a polysilicon layer 300 on the first silicon oxide passivation layer 200, wherein in the specific operation, the first silicon oxide passivation layer 200 and the polysilicon layer 300 are formed by using one or more of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, and a sputtering method, as shown in fig. 1;
s300, carrying out N-type in-situ doping treatment on the polycrystalline silicon layer to generate an N-type doped polycrystalline silicon passivation layer 400, wherein during specific operation, the process for generating the N-type doped polycrystalline silicon passivation layer 400 comprises a diffusion method, and the formed structure is shown in FIG. 2;
s400, forming an oxidation protection layer 500 on the N-type doped polycrystalline silicon passivation layer 400, wherein during specific operation, the oxidation protection layer 500 is formed by adopting one or more of a low-pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method and a sputtering method, and the formed structure is shown in FIG. 3;
s500, removing the oxidation protection layer 500, the N-type doped polysilicon passivation layer 400, and the first silicon oxide passivation layer 200 on the back side of the silicon substrate 100 by an etching method until the silicon substrate 100 forms a tunneling structure, wherein in the specific operation, the etching method is one or two of ion etching and/or wet etching, and the formed structure is as shown in fig. 4;
s600, removing the oxidation protection layer 500 on the front side of the silicon substrate 100 by an etching method until the N-type doped polysilicon passivation layer 400 forms a tunneling structure, wherein during a specific operation, the etching method is BOE/HF wet etching, and the formed structure is as shown in fig. 5;
s700, manufacturing a second silicon dioxide passivation layer 200 'and a polysilicon passivation layer 400' on the front side and the back side of the silicon substrate 100, and in specific operation, manufacturing the second silicon dioxide passivation layer 200 'and the polysilicon passivation layer 400' by adopting one or more of a low-pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method and a sputtering method, wherein the formed structure is shown in FIG. 6;
s800, carrying out P-type in-situ doping on the polysilicon passivation layer 400' formed on the two sides of the silicon substrate 100 in the previous step to generate a P-type doped polysilicon passivation layer 600, wherein during specific operation, the P-type in-situ doping method is a diffusion method, and the formed structure is as shown in FIG. 7;
s900, manufacturing an antireflection layer 700 on the P-type doped polycrystalline silicon passivation layer on the back side of the silicon substrate 100, wherein in the specific operation, the manufacturing method of the antireflection layer comprises one or two of atomic deposition or plasma enhanced chemical vapor deposition;
and S1000, forming a metal bottom electrode layer 800 on the antireflection layer obtained in the previous step, wherein in a specific operation, the forming method of the metal bottom electrode layer 800 comprises one or more of evaporation, screen printing and electroplating, and the formed structure is as shown in FIG. 8.
In addition to the above steps, in specific implementations, Cz tensile is used to prepare silicon substrate 100 having a resistivity of 1-5 ohm. The both-side polishing process of the silicon substrate 100 is performed by an alkaline solution. The first silicon oxide passivation layer 200 formed in step S200 has a thickness of 2nm, and the polysilicon layer 300 has a thickness of 30nm and is in the form of a thin film. In step S300, the polysilicon layer 300 is doped in-situ by phosphane to form an N-doped polysilicon passivation layer 400 with a doping concentration of 1.5 × 1020cm−3. The oxidation protective layer 500 is formed to a thickness of 80 nm. In step S500, the oxidation protection layer 500, the N-type doped polysilicon passivation layer 400 and the first silicon oxide passivation layer 200 on the back surface of the silicon wafer may be removed by Reactive-Ion Etching (RIE) to form a light-trapping backside texture surface. In step S600, the oxidation protection layer 500 is removed by HF/BOE solution. After the two etching processes are completed, the etched concave-convex surface is formed, and a first silicon oxide passivation layer 200 'with the thickness of 2nm and a polycrystalline silicon passivation layer 400' with the thickness of 70nm can be deposited on the front and back surfaces of the silicon wafer in an apposition mode through a low-pressure vapor deposition method. In step S800, the P-type doped polysilicon passivation layer 600 may be formed by performing in-situ doping on the front and back polysilicon films with borane, wherein the doping concentration is 3 × 1020cm−3。
Example two
As shown in fig. 8, in order to form a cell structure through the above method embodiment, the cell structure is a layered structure and includes a silicon substrate 100, the silicon substrate 100 is made of P-type silicon or N-type silicon, the upper surface and the lower surface of the silicon substrate 100 are textured or polished surfaces, the upper surface of the silicon substrate layer 100 is provided with an upper passivation layer playing a role in passivation, the lower surface is provided with a lower passivation layer playing a role in passivation, the lower surface of the lower passivation layer is provided with an anti-reflection layer, and the lower surface of the anti-reflection layer 700 is provided with a metal bottom electrode layer 800;
the upper passivation layer 200 sequentially comprises a first silicon oxide passivation layer 200, an N-type doped polysilicon passivation layer 400, a second silicon oxide passivation layer 200' and a P-type doped polysilicon passivation layer 600 from bottom to top;
the lower passivation layer sequentially comprises a second silicon dioxide passivation layer 200' and a P-type doped polysilicon passivation layer 600 from top to bottom.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (10)
1. A preparation method of a solar cell with a double-sided passivation structure is characterized by comprising the following steps:
s100, selecting a silicon wafer as a silicon substrate of the battery, and performing texturing or polishing treatment on the front surface and the back surface of the silicon substrate;
s200, manufacturing a first silicon oxide passivation layer on the front surface and the back surface of the silicon substrate, and forming a polysilicon layer on the first silicon oxide passivation layer;
s300, carrying out N-type in-situ doping treatment on the polycrystalline silicon layer to generate an N-type doped polycrystalline silicon passivation layer;
s400, forming an oxidation protection layer on the N-type doped polycrystalline silicon passivation layer;
s500, removing the oxidation protection layer, the N-type doped polycrystalline silicon passivation layer and the first silicon oxide passivation layer on one side of the back surface of the silicon substrate by an etching method until the silicon substrate forms a tunneling structure;
s600, removing the oxidation protection layer on one side of the front surface of the silicon substrate by an etching method until the N-type doped polycrystalline silicon passivation layer is formed to form a tunneling structure;
s700, manufacturing a second silicon dioxide passivation layer and a polysilicon passivation layer on one side of the front surface and one side of the back surface of the silicon substrate;
s800, carrying out P-type in-situ doping on the second polysilicon passivation layers formed on the two sides of the silicon substrate in the previous step to generate a P-type doped polysilicon passivation layer;
s900, manufacturing an antireflection layer on the P-type doped polycrystalline silicon passivation layer on the back side of the silicon substrate;
and S1000, manufacturing a metal bottom electrode layer on the antireflection layer obtained in the last step.
2. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S200, the first silicon oxide passivation layer and the polysilicon layer, and the method for forming the oxidation protection layer in the step S400 adopt one or more of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, and a sputtering method.
3. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S300, the process of generating the N-type doped polysilicon passivation layer includes a diffusion method.
4. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S500, the etching method is one or both of ion etching and/or wet etching.
5. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S600, the etching method is BOE/HF wet etching.
6. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in step S700, one or more of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, and a sputtering method are used to form the second silicon dioxide passivation layer and the polysilicon passivation layer.
7. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in step S800, the method for performing P-type in-situ doping is a diffusion method.
8. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S900, the antireflection layer is formed by one or both of atomic deposition and plasma enhanced chemical vapor deposition.
9. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S900, the antireflection layer is formed by one or both of atomic deposition and plasma enhanced chemical vapor deposition.
10. The method of manufacturing a solar cell with a double-sided passivation structure of claim 1, wherein: in the step S100, the metal bottom electrode layer is formed by one or more of evaporation, screen printing and electroplating.
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| WO2023087879A1 (en) * | 2021-11-19 | 2023-05-25 | 常州时创能源股份有限公司 | Double-faced passivated contact cell and preparation method therefor |
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