CN112951927A - Preparation method of solar cell - Google Patents
Preparation method of solar cell Download PDFInfo
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- CN112951927A CN112951927A CN201911253664.8A CN201911253664A CN112951927A CN 112951927 A CN112951927 A CN 112951927A CN 201911253664 A CN201911253664 A CN 201911253664A CN 112951927 A CN112951927 A CN 112951927A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 145
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- 230000005641 tunneling Effects 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000002161 passivation Methods 0.000 claims abstract description 27
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 253
- 229920005591 polysilicon Polymers 0.000 claims description 78
- 238000009792 diffusion process Methods 0.000 claims description 62
- 239000011241 protective layer Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000004140 cleaning Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000005388 borosilicate glass Substances 0.000 claims description 8
- 238000005245 sintering Methods 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 41
- 239000010408 film Substances 0.000 description 24
- 238000005215 recombination Methods 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silver aluminum Chemical compound 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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Abstract
The application provides a preparation method of a solar cell, which comprises the steps of preparing a tunneling layer on one side surface of a silicon wafer, sequentially preparing a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer on the surface of the tunneling layer, wherein the doping concentration of the first doped polycrystalline silicon layer is smaller than that of the second doped polycrystalline silicon layer, and obtaining the doped polycrystalline silicon layer through subsequent annealing. According to the method and the device, the preparation process of the doped polycrystalline silicon layer is optimized, the first doped polycrystalline silicon layer with lower doping concentration is prepared at the position close to the tunneling layer, the second doped polycrystalline silicon layer with higher doping concentration is prepared in a stacking mode, and the influence on the passivation effect of the tunneling layer can be reduced and the performance of the battery can be improved in the process of forming the doped polycrystalline silicon layer through subsequent high-temperature annealing.
Description
Technical Field
The application relates to the technical field of solar cell production, in particular to a preparation method of a solar cell.
Background
Crystalline silicon solar cells currently occupy the important position in the photovoltaic market, and the improvement of cell efficiency is the joint pursuit of the photovoltaic industry and the market. At present, with the continuous improvement of the quality of silicon wafers, the recombination loss of the surface of the battery becomes a key factor for restricting the improvement of the efficiency of the battery, so that the surface passivation technology is very important. In the PERC cell with the rapid increase of the yield in recent years, the passivation film is additionally arranged on the back surface of the cell, so that the recombination of surface carriers is reduced, and the cell conversion efficiency is improved. In order to further reduce the back recombination rate and improve the passivation effect, on the basis of the N-type PERT battery technology, a TOPCon (tunneling oxide passivation contact) battery is developed by Germany Frorff research institute. The ultrathin tunneling oxide layer and the doped polycrystalline silicon film are prepared on the back surface of the battery, a passivation contact structure is formed together, surface recombination and metal recombination on the back surface can be greatly reduced, and therefore the open-circuit voltage Voc and the conversion efficiency of the battery are greatly improved.
At present, the industrialization technology of TOPCon battery has been developed greatly, the mass production efficiency has reached 23%, and the TOPCon battery still has a further space for improvement, and is an important direction for the development of crystalline silicon solar cells. With the increase of the doping concentration of the polycrystalline silicon layer, the filling factor is slightly improved, but in the high-doping concentration polycrystalline silicon layer, the phenomenon that a doping element (usually phosphorus) in the polycrystalline silicon layer penetrates through the tunneling layer is obvious in the high-temperature annealing process, the phosphorus concentration in the silicon substrate close to the tunneling layer is increased, the passivation effect is influenced, and the performance of the battery is further influenced.
In view of the above, there is a need for a new method for manufacturing a solar cell.
Disclosure of Invention
The present application aims to provide a method for manufacturing a solar cell, which improves the performance of the solar cell and improves the conversion efficiency by optimizing the manufacturing process.
In order to achieve the above object, the present application provides a method for manufacturing a solar cell, which mainly includes: preparing a tunneling layer on the surface of one side of the silicon wafer;
sequentially preparing a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer on the surface of the tunneling layer, wherein the doping concentration of the first doped polycrystalline silicon layer is less than that of the second doped polycrystalline silicon layer;
and annealing to obtain the doped polysilicon layer.
As a further improvement of the present application, the preparation process of the doped polysilicon layer comprises depositing a protective layer on the second doped polysilicon layer;
and diffusing, namely forming a diffusion layer on the surface of the other side of the silicon wafer, and annealing the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer in the diffusion process to obtain the doped polycrystalline silicon layer.
As a further improvement of the application, the protective layer is a silicon nitride layer or a silicon oxide layer or a composite layer formed by the silicon nitride layer and the silicon oxide layer, and the thickness of the protective layer is set to be 80-200 nm.
As a further improvement of the application, the thickness of the diffusion layer is 0.4-0.8 μm, and the sheet resistance of the diffusion layer is 80-120 ohm/sq.
As a further improvement of the present application, after the preparation of the protective layer is completed, the other side surface of the silicon wafer is cleaned; then diffusion is carried out.
As a further improvement of the present application, after the "cleaning the other side surface of the silicon wafer", performing single-side texturing on the other side surface of the silicon wafer; then diffusion is carried out.
As a further improvement of the application, the silicon wafer is an N-type silicon wafer, and the tunneling layer, the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are all arranged on the back of the silicon wafer.
As a further improvement of the application, the preparation method further comprises the steps of cleaning and removing the borosilicate glass on the surface of the diffusion layer after the diffusion is finished, and then preparing Al on the surface of the diffusion layer2O3A passivation layer and an anti-reflection layer; or after the diffusion is finished, retaining the borosilicate glass on the surface of the diffusion layer, and preparing an antireflection layer on the surface of the borosilicate glass.
As a further improvement of the present application, after the diffusion is completed, the protective layer on the surface of the doped polysilicon layer is removed;
depositing and preparing a back passivation layer on the surface of the doped polycrystalline silicon layer;
and printing and sintering to obtain a first electrode and a second electrode which are respectively positioned on two sides of the silicon wafer, wherein the first electrode is contacted with the diffusion layer, and the second electrode is contacted with the doped polycrystalline silicon layer.
As a further improvement of the present application, after the diffusion is completed, cleaning and retaining a portion of the protective layer as a back passivation layer;
and printing and sintering to obtain a first electrode and a second electrode which are respectively positioned on two sides of the silicon wafer, wherein the first electrode is contacted with the diffusion layer, and the second electrode is contacted with the doped polycrystalline silicon layer.
As a further improvement of the present application, the preparation method further includes preparing a third doped polysilicon layer between the first doped polysilicon layer and the second doped polysilicon layer, wherein the doping concentration of the third doped polysilicon layer is greater than that of the first doped polysilicon layer, and the doping concentration of the third doped polysilicon layer is less than that of the second doped polysilicon layer.
As a further improvement of the application, the doping concentration of the first doped polycrystalline silicon layer is 5E 18-1E 19cm-3(ii) a The doping concentration of the third doped polysilicon layer is 1E 19-5E 19cm-3(ii) a The doping concentration of the second doped polysilicon layer is 5E 19-5E 20cm-3。
As a further improvement of the application, the thickness of the doped polysilicon layer is set to be 80-300 nm, and the doping concentration of the doped polysilicon layer is 1E 20-2E 20cm-3。
As a further improvement of the application, the tunneling layer is a silicon oxide film or a silicon oxynitride film or a composite film formed by mutually laminating the silicon oxide film and the silicon oxynitride film, and the thickness of the tunneling layer is set to be 1.5-3 nm.
As a further improvement of the present application, the tunneling layer, the first doped polysilicon layer and the second doped polysilicon layer are sequentially prepared on both side surfaces of the silicon wafer;
depositing and preparing a protective layer on the second doped polycrystalline silicon layer on one side of the silicon wafer;
and diffusing, namely reversely doping the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on the other side of the silicon wafer to obtain a diffusion layer, and annealing the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on one side deviating from the diffusion layer to form a doped polycrystalline silicon layer in the diffusion process.
The beneficial effect of this application is: by adopting the preparation method of the solar cell, the first doped polycrystalline silicon layer with lower doping concentration and the second doped polycrystalline silicon layer with higher doping concentration are sequentially prepared on the surface of the tunneling layer, and the doped polycrystalline silicon layer with consistent doping concentration is formed in the subsequent high-temperature annealing process; in the high-temperature annealing process, the first doped polycrystalline silicon layer close to the tunneling layer has low influence on the passivation effect of the tunneling layer due to low doping concentration, and the performance of the battery is improved.
Drawings
FIG. 1 is a schematic structural view of a solar cell fabricated using the fabrication method of the present application;
FIG. 2 is a schematic main flow chart of a method for manufacturing a solar cell according to the present application;
fig. 3 is a schematic structural diagram of a solar cell manufacturing method according to the present application when depositing a protective layer on a second doped polysilicon layer to prepare a protective layer.
100-solar cell; 10-a silicon wafer; 11-a diffusion layer; 20-a tunneling layer; 30-doping a polysilicon layer; 31-a first doped polysilicon layer; 32-a second doped polysilicon layer; 33-a third doped polysilicon layer; 41-a first electrode; 42-a second electrode; 51-front side passivation layer; 52-an antireflective layer; 60-back passivation layer.
Detailed Description
The present application will be described in detail below with reference to embodiments shown in the drawings. The present invention is not limited to the above embodiments, and structural, methodological, or functional changes made by one of ordinary skill in the art according to the present embodiments are included in the scope of the present invention.
Referring to fig. 1, a structural schematic diagram of a solar cell 100 manufactured by the manufacturing method of the present application is shown, where the solar cell 100 includes a silicon wafer 10, a tunneling layer 20 and a doped polysilicon layer 30 sequentially stacked on a surface of one side of the silicon wafer 10, a diffusion layer 11 is formed on a surface of the other side of the silicon wafer 10 by diffusion, and the diffusion layer 11 and the doped polysilicon layer 30 are further respectively provided with corresponding film layer structures. The solar cell 100 further includes a first electrode 41 and a second electrode 42 respectively disposed on two sides of the silicon wafer 10, wherein the first electrode 41 is in contact with the diffusion layer 11, and the second electrode 42 is in contact with the doped polysilicon layer 30.
In this embodiment, the silicon wafer 10 is an N-type silicon wafer, and the resistivity of the silicon wafer 10 is usually set to 0.5-6 Ω · cm. The tunneling layer 20 and the doped polysilicon layer 30 are sequentially stacked on the back surface of the silicon wafer 10, and the doped polysilicon layer 30 is doped with phosphorus. The film structure specifically includes a front passivation layer 51 and an anti-reflection layer 52 disposed on the diffusion layer 11, and a back passivation layer 60 disposed on the doped polysilicon layer 30. The first electrode 41, i.e., the front electrode, passes through the front passivation layer 51 and the anti-reflection layer 52 to make ohmic contact with the diffusion layer 11; the second electrode 42, i.e., the back electrode, passes through the back passivation layer 60 and makes ohmic contact with the doped polysilicon layer 30.
With reference to fig. 2 and fig. 3, the preparation method of the present application mainly includes:
providing a silicon wafer 10, and cleaning and texturing the surface of the silicon wafer 10;
preparing a tunneling layer 20 on the surface of one side of the silicon wafer 10, wherein the thickness of the tunneling layer 20 is set to be 1.5-3 nm;
sequentially preparing a first doped polysilicon layer 31 and a second doped polysilicon layer 32 on the surface of the tunneling layer 20, wherein the doping concentration of the first doped polysilicon layer 31 is less than that of the second doped polysilicon layer 32;
depositing a protective layer 70 on the second doped polysilicon layer 32;
performing diffusion, performing boron diffusion on the other side surface of the silicon wafer 10 to form a diffusion layer 11, and annealing the first doped polysilicon layer 31 and the second doped polysilicon layer 32 in the diffusion process to obtain a doped polysilicon layer 30 with uniform doping concentration;
cleaning and removing the BSG on the surface of the diffusion layer, and then sequentially depositing and preparing a front passivation layer 51 and an antireflection layer 52;
cleaning to remove the protective layer 70 on the back surface of the silicon wafer 10, and depositing to prepare a back passivation layer 60;
screen printing and sintering to obtain the first electrode 41 and the second electrode 42.
Specifically, the silicon wafer 10 is a monocrystalline silicon wafer, and a uniformly distributed 1-3 μm pyramid-shaped texture surface structure is obtained by performing alkali solution texturing. The tunneling layer 20 is a silicon oxide film or a silicon oxynitride film or a composite film formed by laminating a silicon oxide film and a silicon oxynitride film, where the tunneling layer 20 is SiO2Thin films, obtainable by wet chemical (HNO)3/O3/H2SO4+H2O2) Or by thermal oxidation (LPCVD) on the back side of the wafer 10.
The whole thickness of the doped polysilicon layer 30 is set to 80-300 nm, and the doping concentration of the doped polysilicon layer 30 is 1E 20-2E 20cm-3. A third doped polysilicon layer 33 is further prepared between the first doped polysilicon layer 31 and the second doped polysilicon layer 32, the doping concentration of the third doped polysilicon layer 33 is greater than that of the first doped polysilicon layer 31, and the doping concentration of the third doped polysilicon layer 33 is less than that of the second doped polysilicon layer 32. The first doped polysilicon layer 31, the second doped polysilicon layer 32 and the third doped polysilicon layer 33 are all prepared by in-situ doping, so as to prepare a polysilicon film layer with sequentially increasing doping concentrations. The thicknesses of the first, second and third doped polysilicon layers 31, 32 and 33 may be the same or different, and the doping concentration of the first doped polysilicon layer is 5E 18-1E 19cm-3(ii) a The doping concentration of the third doped polysilicon layer is 1E 19-5E 19cm-3(ii) a The doping concentration of the second doped polysilicon layer is 5E 19-5E 20cm-3。
The protective layer 70 is a silicon nitride layer or a silicon oxide layer or a composite layer of a silicon nitride layer and a silicon oxide layer, the protective layer 70 can be made by a PECVD method, and the thickness of the protective layer 70 is set to be 80-200 nm. The thickness of the diffusion layer 11, namely the junction depth, is set to be about 0.4-0.8 μm, and the sheet resistance of the diffusion layer is 80-120 ohm/sq. The preparation method further comprises the step of cleaning the front surface before diffusion, for example, HF with the concentration set to be 5% -15% can be adopted, and a single-side chain type cleaning device is matched to remove the redundant silicon nitride layer and/or silicon oxide layer on the front surface of the silicon wafer 10. After the front side cleaning is completed, single-side alkaline texturing is performed on the front side of the silicon wafer 10 to obtain a given textured structure, so that the quality and the surface antireflection performance of the diffusion layer 11 are ensured.
Here, the front passivation layer 51 is provided as Al2O3Film layer of Al2O3The film layer is suitable for passivating the surface of the P-type diffusion layer 11 and can be prepared by depositing through an ALD process, and the deposition temperature is 180-280 ℃. The antireflection layer 52 is formed of at least one film layer of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like. For improving the film performance and the antireflection effect of the antireflection layer 52 and considering the burn-through performance of the antireflection layer 52, the antireflection layer 52 can be arranged to be a laminated or gradually-changed film structure through the adjustment of technological parameters such as gas flow, reaction time and temperature.
In particular, in other embodiments of the present application, to reduce the overall manufacturing process of the solar cell 100 and improve the product yield, the manufacturing method includes, after the diffusion is completed, retaining borosilicate glass on the surface of the diffusion layer 11 as the front passivation layer 51, and directly depositing an antireflection layer 52 on the surface of the borosilicate glass.
The back passivation layer 60 is provided as a silicon nitride and/or silicon oxide film layer. For the purpose of saving the process, the protective layer 70 may be partially cleaned, in other words, a portion of the protective layer 70 is remained as the back passivation layer 60.
The first electrode 41 and the second electrode 42 are obtained by printing and sintering corresponding slurry respectively, and the peak temperature of the sintering process is 750-800 ℃. Generally, the first electrode 41 can be printed by silver paste, silver aluminum paste or aluminum paste; the second electrode 42 is configured as a silver electrode.
In another embodiment of the present application, the steps that are different from the previous embodiment are:
sequentially preparing the tunneling layer 20, the first doped polysilicon layer 31 and the second doped polysilicon layer 32 on the surfaces of the two sides of the silicon wafer 10;
depositing and preparing a protective layer 70 on the second doped polysilicon layer 32 on one side of the silicon wafer 10;
and performing diffusion, namely performing reverse doping on the first doped polysilicon layer 31 and the second doped polysilicon layer 32 on the other side of the silicon wafer 10 to obtain a diffusion layer 11, and annealing the first doped polysilicon layer 31 and the second doped polysilicon layer 32 on one side departing from the diffusion layer 11 to form a doped polysilicon layer 30 in the diffusion process.
Here, the silicon wafer 10 is also an N-type silicon wafer, and the protective layer 70 is disposed on the second doped polysilicon layer 32 on the back side of the silicon wafer 10. The first doped polysilicon layer 31 and the second doped polysilicon layer 32 on the front surface of the silicon wafer 10 form an emitter of the cell through reverse doping; the first doped polysilicon layer 31 and the second doped polysilicon layer 32 on the back of the silicon wafer 10 are annealed in the diffusion process to form a doped polysilicon layer 30 with uniform doping concentration.
In summary, in the preparation method of the present application, the first doped polysilicon layer 31 with a lower doping concentration and the second doped polysilicon layer 32 with a higher doping concentration are sequentially prepared on the surface of the tunneling layer 20, and the doped polysilicon layer 30 with a consistent doping concentration is formed in the subsequent high temperature annealing process. In the high-temperature annealing process, the first doped polysilicon layer 31 close to the tunneling layer 20 has a low doping concentration, so that the influence on the passivation effect of the tunneling layer 20 is small, the battery performance can be improved, the diffusion process is arranged at the rear, and the high-temperature condition of diffusion is used as the high-temperature annealing process of the first doped polysilicon layer 31 and the second doped polysilicon layer 32, so that the whole process is more reasonable.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.
Claims (15)
1. A method for manufacturing a solar cell, comprising:
preparing a tunneling layer on the surface of one side of the silicon wafer;
sequentially preparing a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer on the surface of the tunneling layer, wherein the doping concentration of the first doped polycrystalline silicon layer is less than that of the second doped polycrystalline silicon layer;
and annealing to obtain the doped polysilicon layer.
2. The method of claim 1, wherein:
depositing and preparing a protective layer on the second doped polycrystalline silicon layer;
and diffusing, namely forming a diffusion layer on the surface of the other side of the silicon wafer, and annealing the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer in the diffusion process to obtain the doped polycrystalline silicon layer.
3. The method of claim 2, wherein: the protective layer is a silicon nitride layer or a silicon oxide layer or a composite layer formed by the silicon nitride layer and the silicon oxide layer, and the thickness of the protective layer is 80-200 nm.
4. The method of claim 2, wherein: the thickness of the diffusion layer is 0.4-0.8 μm, and the sheet resistance of the diffusion layer is 80-120 ohm/sq.
5. The method of claim 2, wherein: after the protective layer is prepared, cleaning the other side surface of the silicon wafer; then diffusion is carried out.
6. The method of claim 5, wherein: after the surface on the other side of the silicon wafer is cleaned, single-side texturing is carried out on the surface on the other side of the silicon wafer; then diffusion is carried out.
7. The method of claim 2, wherein: the silicon chip is an N-type silicon chip, and the tunneling layer, the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are all arranged on the back of the silicon chip.
8. The method of claim 7, wherein: the preparation method also comprises the steps of cleaning and removing the borosilicate glass on the surface of the diffusion layer after the diffusion is finished, and then preparing Al on the surface of the diffusion layer2O3A passivation layer and an anti-reflection layer; or after the diffusion is finished, retaining the borosilicate glass on the surface of the diffusion layer, and preparing an antireflection layer on the surface of the borosilicate glass.
9. The method of claim 7, wherein: after the diffusion is finished, removing the protective layer on the surface of the doped polycrystalline silicon layer;
depositing and preparing a back passivation layer on the surface of the doped polycrystalline silicon layer;
and printing and sintering to obtain a first electrode and a second electrode which are respectively positioned on two sides of the silicon wafer, wherein the first electrode is contacted with the diffusion layer, and the second electrode is contacted with the doped polycrystalline silicon layer.
10. The method of claim 7, wherein: after the diffusion is finished, cleaning and reserving a part of the protective layer as a back passivation layer;
and printing and sintering to obtain a first electrode and a second electrode which are respectively positioned on two sides of the silicon wafer, wherein the first electrode is contacted with the diffusion layer, and the second electrode is contacted with the doped polycrystalline silicon layer.
11. The method of claim 1, wherein: the preparation method also comprises the step of preparing a third doped polycrystalline silicon layer between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer, wherein the doping concentration of the third doped polycrystalline silicon layer is greater than that of the first doped polycrystalline silicon layer, and the doping concentration of the third doped polycrystalline silicon layer is less than that of the second doped polycrystalline silicon layer.
12. The method of claim 11, wherein: the doping concentration of the first doped polysilicon layer is 5E 18-1E 19cm-3(ii) a The doping concentration of the third doped polysilicon layer is 1E 19-5E 19cm-3(ii) a The doping concentration of the second doped polysilicon layer is 5E 19-5E 20cm-3。
13. The method of claim 1, wherein: the thickness of the doped polycrystalline silicon layer is set to be 80-300 nm, and the doping concentration of the doped polycrystalline silicon layer is 1E 20-2E 20cm-3。
14. The method of claim 1, wherein: the tunneling layer is a silicon oxide film or a silicon oxynitride film or a composite film formed by mutually laminating the silicon oxide film and the silicon oxynitride film, and the thickness of the tunneling layer is set to be 1.5-3 nm.
15. The method of claim 1, wherein:
sequentially preparing the tunneling layer, the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on the surfaces of the two sides of the silicon wafer;
depositing and preparing a protective layer on the second doped polycrystalline silicon layer on one side of the silicon wafer;
and diffusing, namely reversely doping the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on the other side of the silicon wafer to obtain a diffusion layer, and annealing the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on one side deviating from the diffusion layer to form a doped polycrystalline silicon layer in the diffusion process.
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| CN113644161A (en) * | 2021-07-22 | 2021-11-12 | 江苏润阳悦达光伏科技有限公司 | Method for passivating borosilicate glass of solar cell |
| CN114038928A (en) * | 2021-11-25 | 2022-02-11 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof and photovoltaic module |
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| US20230079799A1 (en) * | 2021-09-16 | 2023-03-16 | Jinko Solar (Haining) Co., Ltd. | Solar cell, manufacturing method thereof, and photovoltaic module |
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| CN113644161A (en) * | 2021-07-22 | 2021-11-12 | 江苏润阳悦达光伏科技有限公司 | Method for passivating borosilicate glass of solar cell |
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Application publication date: 20210611 |