CN111739982B - Preparation method of selective emitter and solar cell - Google Patents
Preparation method of selective emitter and solar cell Download PDFInfo
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- CN111739982B CN111739982B CN202010624005.7A CN202010624005A CN111739982B CN 111739982 B CN111739982 B CN 111739982B CN 202010624005 A CN202010624005 A CN 202010624005A CN 111739982 B CN111739982 B CN 111739982B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
- H01L31/022458—Electrode arrangements specially adapted for back-contact solar cells for emitter wrap-through [EWT] type solar cells, e.g. interdigitated emitter-base back-contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application provides a preparation method of a selective emitter, which comprises the following steps: forming a doping layer on the surface of the silicon substrate; forming a mask on the surface of the doped layer; selectively removing part of the mask to expose part of the doping layer and form a non-mask protection region and a mask protection region; carrying out high-temperature oxidation treatment on the doping layer including the mask so as to separate out part of doping elements in the non-mask protection region to the oxidation layer and form doping regions with different doping concentrations in the doping layer; and removing the mask and the oxide layer on the surface of the silicon substrate to obtain the selective emitter. The light doping of the high sheet resistance region in the selective emitter structure is realized by adopting an oxidation segregation mode, a doping layer (a boron-rich layer or a phosphorus-rich layer) on the surface can be effectively removed, the recombination loss caused by unactivated doping atoms is reduced, and the open-circuit voltage and the conversion efficiency of the solar cell are further improved.
Description
Technical Field
The present disclosure relates to the field of solar cells, and more particularly, to a method for manufacturing a selective emitter and a solar cell.
Background
In a Selective Emitter (SE) structure of a solar cell, a contact region (electrode ohmic contact region) between a metal electrode and a silicon substrate on a doping layer (also referred to as a diffusion layer) is heavily doped, and a non-metal contact region between the metal electrodes is lightly doped. The structure can effectively reduce the contact resistance and metal recombination of the metal area and improve the open-circuit voltage. Meanwhile, auger recombination of a non-metal contact region, namely a lightly doped region, is reduced, and short-wave quantum efficiency is effectively improved, so that short-circuit current of the light-doped region is improved. Therefore, it is desirable to develop a process for fabricating a selective emitter structure to improve the conversion efficiency of a solar cell.
Disclosure of Invention
The invention provides a preparation method of a selective emitter, which is used for preparing the selective emitter based on an oxidation segregation mode so as to improve the conversion efficiency of a solar cell.
In order to achieve the above purpose, the present application provides the following technical solutions:
according to an aspect of the present application, there is provided a method for preparing a selective emitter, including the steps of:
s1: providing a silicon substrate, and forming a doping layer on the surface of the silicon substrate, wherein the doping layer comprises doping elements and has a first doping concentration;
s2: forming a mask on the surface of the doped layer;
s3: removing a portion of the material from the mask to expose the doped layer to form at least one first region; the area where the mask is not removed is at least one second area which is used as a protective layer of the doped layer;
s4: carrying out high-temperature oxidation treatment on the doped layer comprising the mask so as to form an oxide layer at least in the at least one first region; wherein part of the doping elements of the at least one first region are precipitated out to the oxide layer, the first region has a second doping concentration, and the second doping concentration is smaller than the first doping concentration; and
s5: and removing the mask and the oxide layer to obtain the selective emitter.
Preferably, in step S4, the oxidant used in the high-temperature oxidation process includes oxygen and/or H 2 O。
Preferably, in step S4, the high temperature oxidation treatment is performed at a temperature of 500 to 1200 ℃.
Preferably, in step S4, the thickness of the oxide layer obtained after the high-temperature oxidation treatment is 40 to 300nm.
Optionally, in step S4, annealing the surface of the silicon substrate after performing the high temperature oxidation treatment.
Optionally, the mask layer comprises one or more of silicon oxide, silicon nitride, silicon carbide or an organic thin film.
Optionally, the thickness of the mask layer is greater than or equal to 20nm.
Optionally, the sheet resistance of the first region (non-mask protection region) of the doped layer after the oxidation treatment is in the range of 20-130ohm/sq, the sheet resistance of the second region (mask protection region) is in the range of 80-400ohm/sq, and the sheet resistance of the first region is greater than that of the second region.
According to another aspect of the present application, there is provided a solar cell comprising a selective emitter on a silicon substrate, wherein the selective emitter may be prepared by the above method. The solar cell may further include at least one passivation layer on the surface of the silicon substrate and an electrode forming an ohmic contact with the selective emitter for collecting current.
The selective emitter is formed on the surface of the silicon substrate in an oxidation and segregation mode, the process is simpler, the sheet resistance of the selective emitter light doping region and the sheet resistance of the selective emitter heavy doping region can be respectively controlled by adjusting the doping process, the mask thickness and the oxidation process, and the matching performance with the subsequent passivation and the metallization is very high. Doping elements are separated out in an oxidation mode, so that a doping layer (a boron-rich layer or a phosphorus-rich layer) on a lightly doped surface can be effectively removed, recombination loss caused by unactivated doping atoms is reduced, the open-circuit voltage and the conversion efficiency of the solar cell are further improved, the surface of a silicon wafer is not etched by laser or a chemical method, surface damage is avoided, and the effect improvement effect of the selective emitter is not adversely affected.
Drawings
FIG. 1 is a flow chart illustrating selective emitter fabrication according to an embodiment of the present application;
FIGS. 2A-2E are schematic diagrams of selective emitter fabrication according to embodiments of the present application; and
fig. 3 is a graph of doping profiles after an oxidation treatment and after an oxidation treatment plus an annealing treatment according to embodiments of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone.
It should be understood that the directional terms "upper", "lower", etc. used in the description of the embodiments of the present application are used in a directional sense as illustrated in the accompanying drawings, and should not be construed as limiting the embodiments of the present application. Further, it will be understood that when an element is referred to as being "on" or "under" another element, it can be directly on or under the other element or be indirectly on or under the other element via an intermediate element. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
All the technical features mentioned herein, as well as preferred features, may be combined with each other to form new solutions, if not mentioned specifically. Unless otherwise defined or indicated, the terms of art and science used herein have the same meaning as is familiar to those skilled in the art.
In the present invention, unless otherwise indicated, the numerical range "a-b" represents a shorthand representation of any combination of real numbers between a and b, including a and b where a and b are both real numbers. For example, the numerical range "800-900" represents all real numbers between "800-900" that have all been listed herein, and "800-900" is simply an abbreviated representation of the combination of these numbers.
A "range" disclosed herein can be in the form of one or more lower limits and one or more upper limits, respectively, in terms of lower limits and upper limits.
In a Selective Emitter (SE) structure of a solar cell, a contact region (electrode ohmic contact region) between a metal electrode and a silicon substrate is heavily doped on a doping layer (also referred to as a diffusion layer), and a non-metal contact region between the metal electrodes is lightly doped. The structure can effectively reduce the contact resistance and metal recombination of the metal area and improve the open-circuit voltage. Meanwhile, auger recombination of a non-metal contact region, namely a lightly doped region, is reduced, and short-wave quantum efficiency is effectively improved, so that short-circuit current of the light-doped region is improved.
For the preparation of the solar cell SE structure, the following can be used: 1) The selective emitter is realized by a laser doping mode, but the doping concentration difference of a light doping area and a heavy doping area is limited, so that the improvement range of the cell efficiency is limited, the laser area is easy to damage, and the improvement of the cell efficiency is influenced; 2) A selective emitter is formed in a reverse etching mode, so that a pyramid structure on the surface of the battery after texturing can be damaged, the antireflection effect is reduced, and the improvement of the battery efficiency is influenced; 3) The selective emitter is formed by the two-step diffusion method, the process is complex, the number of atoms of the doping layer is increased due to the two-step diffusion, the recombination is enhanced, and the improvement of the efficiency of the battery is influenced.
Therefore, in order to overcome the defects of the prior art, embodiments of the present application provide a method for manufacturing a selective emitter, where a doped layer is first formed on a surface of a silicon substrate, where the doped layer is used to provide a heavily doped region in a selective emitter structure, and then a lightly doped high sheet resistance region in the selective emitter structure is realized in an oxidation segregation manner, so that the heavily doped layer on the surface can be effectively removed, recombination loss caused by unactivated doped atoms is reduced, and open-circuit voltage and conversion efficiency of a solar cell are further improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1 to fig. 2E, fig. 1 is a flow chart illustrating the preparation of a selective emitter according to an embodiment of the present disclosure, and fig. 2A to fig. 2E are schematic diagrams illustrating the preparation of a selective emitter according to an embodiment of the present disclosure.
S1: providing a silicon substrate 1, and forming a doping layer 2 on the surface of the silicon substrate 1, wherein the doping layer 2 comprises doping elements and has a first doping concentration. In some embodiments, the doped layer 2 may be formed as part of the silicon substrate 1.
Alternatively, the silicon substrate may include, but is not limited to, single crystal silicon, polycrystalline silicon, and/or single crystal-like, among others. For example, the silicon substrate 1 is a single crystal silicon substrate having a resistivity of 0.5 to 3.5 Ω · cm and a thickness of 150 to 270 μm.
In some embodiments, the silicon substrate may be a P-type substrate or an N-type substrate. When the silicon substrate is a P-type substrate, the doped layer is an N-type doped layer, so that a PN junction structure is formed. When the silicon substrate is an N-type substrate, the doped layer is a P-type doped layer, so that a PN junction structure is formed.
The doped layer may be formed by high temperature diffusion (also referred to as thermal diffusion), slurry doping, or ion implantation. In one embodiment, a high temperature diffusion process is used to form a doped layer having a thickness of 0.3-2.0 μm on a silicon wafer surface.
For example, the P-type substrate may be doped with phosphorus, specifically, the substrate is placed in a tubular diffusion furnace, a phosphorus oxychloride liquid source is used as a diffusion source (or doping source), the temperature of the constant temperature region is maintained at about 810 ℃, phosphorus diffusion is performed on the substrate for a certain diffusion time (for example, 40 min), and the doping junction depth is 0.2 to 1.0 μm, thereby forming a phosphorus heavily doped layer with a first doping concentration.
For another example, the N-type substrate may be doped with boron, and specifically, the substrate may be placed in a tubular diffusion furnace, a liquid boron tribromide source is used as a diffusion source (or doping source), the temperature of the constant temperature region is maintained at about 850 ℃, boron is diffused into the substrate for a certain diffusion time (e.g., 40 min), and the doping junction depth is 0.2 to 1.0 μm, thereby forming a boron heavily doped layer having the first doping concentration.
It is noted that the doped layer formed is a heavily doped layer, i.e. the first concentration has a relatively high concentration, in order to provide a heavily doped region in the selective emitter structure.
In some embodiments, the silicon substrate may be pre-treated. For example, a pyramidal surface structure may be formed by texturing the silicon substrate to achieve texturing of the surface of the silicon substrate. Alternatively, the substrate is etched with an alkaline solution (such as a sodium hydroxide or potassium hydroxide solution) for a period of time to form the pyramidal features.
The shape of the surface of the silicon substrate is not limited, and may be a pyramid shape, a polished surface, a black silicon surface, a damage-removed surface, or the like. For example, if selective electrodes are used on the front side of the substrate, the surface of the silicon substrate is typically a pyramidal or black silicon surface for reducing reflection of incident light. If selective electrodes are used on the back side of the substrate, the surface of the silicon substrate is typically a de-damaged or polished surface.
S2: a mask 3 is formed on the surface of the doped layer.
The formed mask may be used to provide a protective layer for certain regions of the doped layer so that the regions covered by the mask are not oxidized in a subsequent oxidation process.
Optionally, the mask comprises one or more of silicon oxide, silicon nitride, silicon carbide or an organic thin film. In some embodiments, the mask has a thickness greater than or equal to 20nm. The mask may be formed on the surface of the doped layer by chemical vapor deposition, spin coating, printing, or thermal oxidation, which are commonly used in the art, and will not be described herein.
S3: a portion of the material is removed from the mask 3 exposing the doped layer to form at least one first region 24, wherein the region of the mask not removed is at least one second region (25). The remaining mask is used to provide a protective layer for the at least one second region.
In some embodiments, the mask 3 may be selectively removed by physical or chemical means. For example, the physical method may include an ultrasonic cleaning method. The chemical process may include a hydrofluoric acid (HF) etching process. Specifically, the mask 3 on the surface of the doped layer is selectively removed by adopting HF with the concentration of 2-10wt%, and the etching time is in the range of 2-30min.
S4: carrying out high-temperature oxidation treatment on the doping layer comprising the mask so as to form an oxidation layer in the at least one first region; and part of doping elements of the at least one first region are precipitated to the oxide layer, the at least one first region has a second doping concentration, and the second doping concentration is smaller than the first doping concentration.
In this step, the high temperature oxidation process may be performed on the doped layer including the mask by using a dry oxygen or wet oxygen process at a temperature of 500 to 1200 ℃.
As shown in FIG. 2D, when the high temperature oxidation is performed, the oxidizing agent (oxygen and/or water vapor) used undergoes an oxidation reaction with the silicon in the doped layer to form silicon oxide (SiO) x ) A layer 22. Since the melting temperature of the silicon oxide is higher than that of the doped layer, the silicon oxide layer 22 forms a mixed phase of a silicon oxide solid phase and a doped layer liquid phase 21 during cooling, and the concentration of the doping element (phosphorus or boron) in the solid phase and the liquid phase is differentiated, thereby causing the doping element to migrate toward the silicon oxide solid phase. In this process, however, since the at least one second region 25 of the doped layer covered by the mask is protected, the oxidizing agent cannot reach this region, so that the at least one second region 25 is not oxidized and the concentration of the doping element in the second region 25 is not reduced or is reduced only to a small extent.
The doped layer is subjected to a high temperature oxidation treatment, and due to the principle of oxidative segregation, part of the doping elements in the oxidized first region 24 are precipitated to the oxidized layer, resulting in a reduced doping concentration, while the concentration of the doping elements in the second region 25 of the doped layer protected by the mask is not reduced or is reduced to a small extent. Thus, the doped layer subjected to the high temperature oxidation process produces a lightly doped region (i.e., first region 24) having the second doping concentration and a heavily doped region (i.e., first region 25) having the first doping concentration. The sheet resistance of the lightly doped region is reduced relative to that before high-temperature oxidation, while the sheet resistance of the heavily doped region is kept unchanged or only slightly increased relative to that before high-temperature oxidation treatment. Thus, the lightly doped region and the heavily doped region form a selective emitter.
For high temperature oxidation processes, when the oxidant is oxygen, it is referred to as dry oxygen oxidation. When the oxidant is water, the wet oxygen is oxidized. In one embodiment, the high temperature oxidation is carried out using a wet oxygen oxidation process. The wet oxidation can form a thicker oxide layer at a lower temperature and in a shorter time, and more doping element boron can be precipitated in a shorter time. In the case of high-temperature oxidation, the oxidation temperature is preferably in the range of 600 to 900 ℃. Too low a temperature results in too slow a rate of oxide formation and takes a long time. And the excessive oxidation temperature brings unnecessary energy consumption.
The thickness of the oxide layer obtained after the surface of the doped layer is subjected to oxidation treatment is preferably in the range of 40 to 300nm. When the thickness of the oxide layer is less than 40nm, the doping elements precipitated into the oxide layer are too small to form an effective lightly doped region and a heavily doped region. When the thickness of the oxide layer is greater than 300nm, the time for forming the oxide layer is too long, and unnecessary power consumption is increased. Since the thickness of the oxide film is related to the temperature and the length of time of the high-temperature oxidation, the thickness of the oxide film can be adjusted by the oxidation temperature and time.
After the surface of the doped layer is oxidized, the surface of the silicon substrate can be annealed. After the high-temperature oxidation treatment is carried out on the doping layer, particularly for the boron doping layer, a concave doping curve can be formed on the surface after the high-temperature oxidation treatment, the shape of the doping curve can be modified through annealing, and the better passivation effect of the silicon surface can be realized. As shown in fig. 3, the curve after oxidation is shown by a dotted line. As can be seen from the dotted line, the ordinate and the doping concentration decrease with the change in the silicon depth. After annealing treatment, the doping curve becomes more stable, and the doping is kept basically unchanged in a longer silicon depth. This means that the concentration of the doped layer can be made uniform as a whole by the annealing treatment, and the performance is improved.
S5: the mask 3 and the oxide layer 22 are removed to obtain the selective emitter.
The selective emitter comprises a doped layer of at least one first region 24 that is lightly doped and at least one second region 25 that is heavily doped, as shown in fig. 2E. Optionally, the sheet resistance of the first region is in a range of 20-130ohm/sq, and the sheet resistance of the second region is in a range of 80-400ohm/sq.
To form the selective emitter, the sheet resistance of the first region is greater than the sheet resistance of the second region. The sheet resistance of the first region and the sheet resistance of the second region can be adjusted by forming different lightly doped layers according to doping elements and the method described above.
The selective emitter is formed on the surface of the silicon substrate in an oxidation and segregation mode, the process is simpler, the sheet resistance of the selective emitter light doping region and the sheet resistance of the selective emitter heavy doping region can be respectively controlled by adjusting the doping process, the mask thickness and the oxidation process, and the matching performance with the subsequent passivation and the metallization is very high. The doping elements are precipitated in an oxidation mode, so that a doping-rich layer (a boron-rich layer or a phosphorus-rich layer) on the lightly doped surface can be effectively removed, the recombination loss caused by unactivated doping atoms is reduced, and the open-circuit voltage and the conversion efficiency of the solar cell are further improved. The method does not use laser or chemical method to etch the surface of the silicon chip, does not cause surface damage, and does not have negative influence on the effect improvement effect of the selective emitter.
The present application further provides a solar cell comprising a silicon substrate and a selective emitter structure formed on a surface thereof (e.g., a base front side). The selective emitter structure has a heavily doped region with a first doping concentration and a lightly doped region with a second doping concentration, wherein the first doping concentration is greater than the second doping concentration. The solar cell further comprises at least one passivation layer deposited on the surface of the substrate. The passivation layer includes, but is not limited to, silicon nitride, silicon oxynitride, aluminum oxide. The solar cell further comprises an electrode forming an ohmic contact with the selective emitter for collecting current converted by the solar cell.
In some embodiments, the solar cell may be formed by:
forming a selective emitter structure on the surface of the silicon substrate by using the selective emitter preparation method described in fig. 1, which is not described herein again;
etching the surface of the substrate to remove phosphorosilicate glass or borosilicate glass formed in the doping process;
forming a back passivation layer on the back surface of the substrate;
forming a front passivation layer and/or an antireflection layer on the front surface of the substrate, wherein the antireflection layer can adopt a film layer which is the same as or similar to the passivation layer;
methods of passivation include, but are not limited to, plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), and Physical Vapor Deposition (PVD).
Forming electrodes on the front surface and/or the back surface by a screen printing process and sintering;
in some embodiments, a back electrode is formed on the back side of the substrate, and the back electrode may penetrate and/or partially penetrate the passivation layer to form an ohmic contact with the substrate. For example, a screen printing technique may be used to print a conductive paste on the back surface of the substrate, and the conductive paste is baked and sintered to form a gate line-shaped back electrode. The conductive paste of the back electrode can be a conductive silver paste with penetrability, and can penetrate through the passivation layer after being sintered so as to be electrically connected with the substrate.
In some embodiments, a front electrode is formed on the front side of the substrate, and the front electrode may form an ohmic contact with a heavily doped region in the selective emitter on the substrate through and/or partially through the antireflective layer and/or passivation layer. Alternatively, the front electrode may be a gate line structure. For example, a conductive paste may be printed on the front surface of the substrate by a screen printing technique, and dried to form a grid-shaped front electrode. The conductive paste of the front electrode can be a conductive silver paste with penetrability, and the conductive silver paste can penetrate through the anti-reflection layer and/or the passivation layer after being sintered so as to be electrically connected with the substrate through the heavily doped region.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It is noted that a portion of this patent application contains material which is subject to copyright protection. The copyright owner reserves the copyright rights whatsoever, except for making copies of the patent files or recorded patent document contents of the patent office.
Claims (9)
1. A method of making a selective emitter, comprising:
providing a silicon substrate, and forming a doping layer on the surface of the silicon substrate, wherein the doping layer comprises doping elements and has a first doping concentration;
forming a mask on the surface of the doped layer;
removing a portion of the material from the mask to expose the doped layer to form at least one first region; the area where the mask is not removed is at least one second area;
carrying out high-temperature oxidation treatment on the doped layer comprising the mask to form an oxide layer in the at least one first region; wherein a part of the doping elements in the at least one first region are precipitated out to the oxide layer, the at least one second region of the doping layer covered by the mask is protected, the oxide layer is not formed in the at least one second region, the at least one first region has a second doping concentration, and the second doping concentration is less than the first doping concentration; the thickness of the oxide layer obtained after the high-temperature oxidation treatment is 40-300nm; and
and removing the mask and the oxide layer to obtain the selective emitter.
2. The method according to claim 1, wherein the oxidizing agent used in the high-temperature oxidation treatment comprises oxygen and/or H 2 O。
3. The production method according to claim 1, wherein the high-temperature oxidation treatment is performed at a temperature of 500 to 1200 ℃.
4. The production method according to claim 1, wherein annealing treatment is performed on the surface of the silicon substrate after the high-temperature oxidation treatment is performed.
5. The method of claim 1, wherein the mask comprises one or more of silicon oxide, silicon nitride, silicon carbide, or an organic thin film.
6. The method of claim 1, wherein the mask has a thickness greater than or equal to 20nm.
7. The method of claim 1, wherein the sheet resistance of the at least one first region is in a range of 20-130ohm/sq, the sheet resistance of the at least one second region is in a range of 80-400ohm/sq, and the sheet resistance of the at least one first region is greater than the sheet resistance of the at least one second region.
8. A solar cell, characterized in that it comprises at least: a silicon substrate and a selective emitter on the silicon substrate, wherein the selective emitter is prepared by the method of any one of claims 1-7.
9. The solar cell of claim 8, further comprising:
at least one passivation layer positioned on the surface of the silicon substrate; and
and an electrode forming an ohmic contact with the selective emitter, the electrode being for collecting current.
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| CN112885724A (en) * | 2021-01-15 | 2021-06-01 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN113363334A (en) * | 2021-06-01 | 2021-09-07 | 常州时创能源股份有限公司 | Preparation method of boron-doped selective emitter |
| CN113903817A (en) * | 2021-09-07 | 2022-01-07 | 湖南红太阳光电科技有限公司 | Preparation method of selective emitter of crystalline silicon solar cell |
| CN113990985A (en) * | 2021-11-02 | 2022-01-28 | 南京日托光伏新能源有限公司 | Preparation method of ingot single crystal and MWT battery structure |
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| WO2012096311A1 (en) * | 2011-01-13 | 2012-07-19 | 日立化成工業株式会社 | p-TYPE DIFFUSION LAYER FORMATION COMPOSITION, METHOD FOR PRODUCING SILICON SUBSTRATE HAVING p-TYPE DIFFUSION LAYER, METHOD FOR PRODUCING SOLAR CELL ELEMENT, AND SOLAR CELL |
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