CN111599895A - Preparation method of crystalline silicon solar passivated contact cell - Google Patents
Preparation method of crystalline silicon solar passivated contact cell Download PDFInfo
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- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 43
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 230000005641 tunneling Effects 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 230000003667 anti-reflective effect Effects 0.000 claims description 6
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- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 4
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
A preparation method of a crystalline silicon solar passivated contact cell belongs to the field of solar cells. The preparation method comprises the following steps: manufacturing a tunneling layer on the back of the N-type crystalline silicon to obtain a first structure body; manufacturing an n + doped polycrystalline silicon passivation layer on the back surface of the tunneling layer, and then etching the edge and the front surface to obtain a second structural body; carrying out P + doping on the front surface of the second structure body to manufacture a P-type layer, and then carrying out edge and back etching to obtain a third structure body; manufacturing a passivation film on the front surface of the third structure body to obtain a fourth structure body; respectively manufacturing antireflection films on the front surface and the back surface of the fourth structural body to obtain a fifth structural body; electrodes are formed on the front and back surfaces of the fifth structure body, respectively. The battery has simple manufacturing process and high photoelectric efficiency.
Description
Technical Field
The application relates to the field of solar cells, in particular to a preparation method of a crystalline silicon solar passivated contact cell.
Background
In recent years, as an environment-friendly energy technology, the development of crystalline silicon solar power generation is rapid, and various novel crystalline silicon technologies emerge endlessly.
At present, Passivated Emitter and Rear Cell (PERC) solar cells are mainly used in the market. The photoelectric conversion efficiency of the PERC solar cells in mainstream production can exceed 22%. However, the conversion efficiency of the PERC solar cell is more limited to be improved. Therefore, a technique called passivation contact has been developed, which can be used to further improve the photoelectric conversion efficiency of the cell. Passivation contact technology is highly compatible with existing PERC technology and is therefore becoming increasingly popular with the market and various research institutes.
However, in the practice of the prior art passivation contact technology, the solar cell is prone to failure.
Disclosure of Invention
In view of the above-mentioned shortcomings, the present application provides a method for preparing a crystalline silicon solar passivated contact cell to partially or fully ameliorate, or even solve, the problems of the related art.
The application is realized as follows:
in a first aspect, examples of the present application provide a method of making a crystalline silicon solar passivated contact cell. It includes: manufacturing a tunneling layer on the back of the N-type crystalline silicon to obtain a first structure body; manufacturing an n + doped polycrystalline silicon passivation layer on the back surface of the tunneling layer, and then etching the edge and the front surface to obtain a second structural body; carrying out P + doping on the front surface of the second structure body to manufacture a P-type layer, and then carrying out edge and back etching to obtain a third structure body; manufacturing a passivation film on the front surface of the third structure body to obtain a fourth structure body; respectively manufacturing antireflection films on the front surface and the back surface of the fourth structural body to obtain a fifth structural body; electrodes are formed on the front and back surfaces of the fifth structure body, respectively.
With reference to the first aspect, in a first possible implementation manner of the first aspect of the present application, the material of the tunneling layer is silicon dioxide.
With reference to the first aspect, in a second possible implementation manner of the first aspect of the present application, the tunneling layer is fabricated by thermal oxidation, ozone, wet oxidation, or atomic layer deposition.
With reference to the first aspect or the first or second embodiment of the first aspect, in a third possible implementation of the first aspect of the present application, the tunneling layer has a thickness of 0.5 nm to 3 nm.
With reference to the first aspect, in a fourth possible implementation manner of the first aspect of the present application, the fabricating the n + doped polysilicon passivation layer includes fabricating a polysilicon film and n + doping, where the polysilicon film is implemented by low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and the n + doping is implemented by low pressure ion implantation or thermal diffusion; alternatively, p + doping is performed by low pressure ion implantation or thermal diffusion.
With reference to the first aspect or the four embodiments of the first aspect, in a fifth possible implementation of the first aspect of the present application, the thickness of the n + -doped polysilicon passivation layer is 20 nanometers to 300 nanometers.
In a sixth possible implementation form of the first aspect of the present application in combination with the first aspect, the surface sheet resistance of the P-type layer is 80 ohm/□ to 300 ohm/□.
With reference to the first aspect, in a seventh possible implementation manner of the first aspect of the present application, the material of the passivation film is aluminum oxide, and/or the material of the antireflective film is silicon nitride.
With reference to the first aspect, in an eighth possible implementation manner of the first aspect of the present application, the edge and front etching and the edge and back etching are performed by chemical wet etching or dry etching, respectively and independently.
In a second aspect, examples of the present application provide a method of making a crystalline silicon solar passivated contact cell. The battery includes: a substrate and upper and lower electrodes respectively positioned on top and bottom surfaces of the substrate; the substrate comprises N-type crystalline silicon and a front surface structure and a back surface structure which are respectively positioned on the front surface and the back surface of the N-type crystalline silicon; the front structure comprises a P + doped P-type layer, an aluminum oxide passivation film and a silicon nitride antireflection film which are sequentially laminated; the back structure comprises a silicon dioxide tunneling layer, an n + doped polysilicon passivation layer and a silicon nitride anti-reflection film which are sequentially laminated.
The preparation method comprises the following steps: before the P + doped P-type layer is manufactured, a silicon dioxide tunneling layer and an n + doped polysilicon passivation layer are manufactured in sequence.
In the implementation process, in the preparation method of the crystalline silicon solar passivated contact cell provided by the embodiment of the application, doped polycrystalline silicon is plated on the back side of the passivated contact cell, and then boron diffusion is performed on the front side of the passivated contact cell. The process can effectively avoid the problem of electroplating and can also improve the photoelectric conversion efficiency of the solar cell.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is a schematic structural diagram of a crystalline silicon solar passivated contact cell prepared by the method in the application example;
fig. 2 shows a flow diagram of a known process for fabricating the crystalline silicon solar passivated contact cell of fig. 1;
fig. 3 shows another process flow diagram for fabricating the crystalline silicon solar passivated contact cell of fig. 1 in an example of the application.
Icon: 100-solar cell; 101-a lower electrode; 102-silicon nitride antireflective film; 103-a polysilicon passivation layer; 104-a silicon dioxide tunneling layer; 105-N type crystalline silicon; 106-doped P-type layer; 107-aluminum oxide passivation film; 108-silicon nitride antireflective film; 109-an upper electrode; 201-a substrate; 202-PN junction; 203-front side structure; 204-backside structure.
Detailed Description
Embodiments of the present application will be described in detail below with reference to examples, but those skilled in the art will appreciate that the following examples are only illustrative of the present application and should not be construed as limiting the scope of the present application. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
The following specifically describes a method for manufacturing a crystalline silicon solar passivated contact cell according to the embodiment of the application:
a crystalline silicon solar passivated contact cell is a solar cell that uses silicon material, is based on PN junctions, and incorporates passivated contact technology. Generally, N-type crystalline silicon is used as a substrate, and doping is performed on the front surface of the substrate to form a PN junction, and then corresponding subsequent operations are performed to fabricate various functional layers on the front surface and the back surface. For example, wherein the implementation is as a passivated contact scheme after forming the PN junction, a relatively thin oxide film is fabricated, which acts as a tunneling layer. And a polysilicon layer matched with the tunneling layer and used as a passivation layer. The tunneling layer and the passivation layer cooperate to hinder the recombination of the minority carriers and at the same time allow the separation of the majority carriers. By such a configuration, the photoelectric conversion efficiency can be improved to some extent. However, current batteries of this type tend to exhibit low efficiency (lower than expected by design) during use, relatively short service life, and even failure.
In order to facilitate understanding of the method for manufacturing a crystalline silicon solar passivated contact cell proposed in the present application, in an example, the inventor provides a crystalline silicon solar passivated contact cell (hereinafter referred to as a solar cell 100) fabricated in an experiment and a process thereof.
The solar cell 100 is constructed as shown in fig. 1 with an N-type crystalline silicon 105 as the substrate and a PN junction 202 formed by a front P + doped P-type layer 106.
In general, the solar cell 100 includes a base 201 and upper and lower electrodes 109 and 101 on top and bottom surfaces thereof.
Wherein the substrate comprises N-type crystalline silicon 105 and front side structures 203 and back side structures 204 on the front side and back side, respectively.
The front surface structure 203 includes a P + doped P-type layer 106, an aluminum oxide passivation film 107, and a silicon nitride antireflective film 108 stacked in this order. The back structure 204 comprises a silicon dioxide tunneling layer 104, an n + doped polysilicon passivation layer 103, and a silicon nitride anti-reflective film 102 stacked in sequence.
The process flow of the solar cell 100 is shown in fig. 2, and includes the following steps.
S10, cleaning and texturing
Firstly, cleaning and texturing a substrate. For example, by using an acid solution (e.g., HF and HNO)3The mixed acid) and alkaline solution (such as sodium hydroxide or potassium hydroxide solution) are used for cleaning and texturing the substrate so as to remove metal ions and cutting damage layers on the surface of the substrate silicon wafer and form wormhole-shaped textured surface or pyramid-shaped textured surface. Alternatively, electrochemical texturing, reactive ion etching texturing, laser texturing, mask texturing, and the like may also be used.
Impurities and defects (such as residues) on the surface of the silicon wafer can be removed through cleaning, and the surface can be in a rough state through texturing, so that a light trapping structure is formed, and the incidence rate of light can be improved.
In the texturing process, the front surface of the substrate forms a rough surface structure through the textured surface, so that a P-type layer of the front surface, an aluminum oxide passivation film of the front surface and a silicon nitride anti-reflection film of the front surface which are manufactured on the front surface subsequently have similar textured structures, such as the pyramid-shaped textured surface.
Step S11. front boron diffusion
The substrate is subjected to boron element diffusion by means of thermal diffusion or ion implantation, so that a phosphorus-doped P-type surface (P + doped P-type layer) is formed to form a PN junction.
Step S12, back cleaning
And cleaning the back surface of the PN junction, namely the surface of one side of the substrate silicon wafer far away from the N-type surface.
Step S13, plating SiO on the back surface2And doped polysilicon
Forming SiO on the cleaned back surface by thermal oxidation, ozone, wet oxidation or Atomic Layer Deposition (ALD)2And forming a silicon dioxide tunneling layer. Then, a polysilicon film is formed on the bottom surface (surface away from the substrate) of the silicon dioxide tunneling layer by Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), and then is doped with phosphorus by ion implantation or thermal diffusion to form an n + doped polysilicon passivation layer.
S14, etching the edge and the front
Since the phosphorus doping of the polysilicon on the back surface is performed in step S13, a phosphorus doped structure is also formed on the side surface (edge) and the front surface of the substrate, and thus, in order to avoid the phosphorus doping of the side surface, the doped layer is removed by chemical wet or dry etching. Thus leaving only the phosphorus doping at the bottom.
Step S15, front side plating with Al2O3
After etching, depositing aluminum oxide on the front surface by thermal oxidation, ozone or wet oxidation or atomic layer deposition and the like to form an aluminum oxide passivation film.
Step S16, front/back SiNx
And respectively manufacturing silicon nitride films on the aluminum oxide passivation film and the n + doped polysilicon passivation layer by a plasma enhanced chemical vapor deposition method to form the silicon nitride antireflection film.
Step S17, printing and sintering of front/back electrodes
Through the steps, the substrate of the crystalline silicon solar cell adopting the passivation contact technology is manufactured, the grid finger-shaped metal material is manufactured in a screen printing mode, and then the upper electrode and the lower electrode are formed through sintering. The cell obtained according to this example can achieve a Voc performance of 697.0mV, a Jsc performance of 40.3A, an FF performance of 81.4%, and an Eff performance of 22.86%.
Tests show that the crystalline silicon solar passivated contact cell manufactured through the steps has the problem of easy failure. After studying the reason, the inventor finds that: since the diffusion coefficient of phosphorus is larger than that of boron, in the phosphorus doping process (step S13), the doping of phosphorus on the front surface destroys the P-type thin layer (i.e., P + doped P-type layer) in the PN junction formed in the previous process (steps S10 and S11), and accordingly, PN is also destroyed, thereby causing the solar cell to have low efficiency and even fail.
In view of the above problems, the inventors tried to coat a protective film such as SiNx, SiC, etc. on the emitter of the front side (in the PN junction, the base silicon wafer is the base, and the doped layer thereon having the polarity opposite to that of the base is the emitter). Due to the presence of the protective film, the protective film can prevent doping of the emitter when doping of the back surface is performed. Therefore, after the back N + doped polysilicon is plated, the front protective film is washed away. The process can effectively avoid the damage of phosphorus wraparound plating to the PN junction of the front surface, but the additional plating and cleaning procedures are required to be added, the manufacturing cost of the solar cell is increased, and the application and the development of the passivation contact cell technology are not facilitated.
In view of the above, the present application provides a novel technical solution to improve or even solve the above problems. The novel technical solution can realize another solution different from the above-mentioned technique while applying a passivation Contact technique (Tunnel oxide passivated Contact, TOPCon in the example). The method can not only apply a passivation contact technology in the crystalline silicon solar cell, but also avoid the problem of phosphorus electroplating in the process, thereby avoiding the damage to the PN junction on the front surface and avoiding the introduction of more process steps. Namely, the manufacturing of the crystalline silicon solar passivated contact cell is realized by a relatively simpler preparation process, and the photoelectric conversion efficiency is improved.
Overall, the solution exemplified in the present application, for the first time, employs in the passivation of contact cells: the doped polysilicon is plated on the back surface, and then the battery is prepared in a mode of boron diffusion on the front surface, so that the traditional process technical route is completely overturned. In the process, since the back phosphorus-doped polysilicon is prepared firstly (at the moment, a PN junction is not formed on the front surface), even if phosphorus is plated around the front surface in the doping process, the PN junction cannot be damaged. In addition, because the diffusion coefficient of boron is much smaller than that of phosphorus, the n + doped polysilicon on the back surface is not damaged in the front boron diffusion process.
The preparation method of the crystalline silicon solar passivated contact cell in the embodiment of the application can be seen in figure 3.
S300, cleaning and texturing; step S301, plating SiO on the back surface2And doping the polysilicon; s302, etching the edge and the front; s303, front boron diffusion; s304, etching the edge and the back; step S305. front side Al plating2O3(ii) a S306, front/back SiNx; step S307, printing and sintering of front/back electrodes. The above steps may be performed by an existing semiconductor process, such as the specific process methods corresponding to the above mentioned steps in the process route shown in fig. 2, such as thermal oxidation, low pressure chemical vapor deposition, ion implantation, and so on.
The SiO formed in the step S3012And doped polysilicon (n + doped, i.e., n-type heavy doping) together form a tunnel oxide passivation contact. The tunneling oxide is silicon dioxide, which may be referred to as tunneling layer, passivation tunneling layer, or passivation oxide layer. Because the thickness of the silicon dioxide layer is thin, minority carriers can be prevented from passing through, while majority carriers can pass through by tunneling. Silicon dioxide can significantly suppress recombination at the back surface (recombination at the metal/lower electrode contact region) and thus has an excellent passivation effect.
In conjunction with fig. 2 and 3, it can be seen that the improved solution proposed by the present application (the solution of fig. 3) is substantially comparable, without a significant increase, in the overall process steps compared to the known solution implemented by the inventors (the solution of fig. 2). The main difference between the two is the process step defined by the dashed box in fig. 3.
Alternatively, the preparation methods exemplified in the present application can also be illustrated by the following descriptions:
manufacturing the back surface of the cleaned and textured N-type crystalline silicon (plating SiO on the back surface)2) And a tunneling layer, obtaining a first structure body. The tunneling layer has a thickness of 0.5 nm to 3 nm.
And manufacturing an n + doped polycrystalline silicon passivation layer (doped polycrystalline silicon) on the back surface of the tunneling layer, and then etching the edge and the front surface to obtain a second structural body. The thickness of the n + doped polysilicon passivation layer is significantly greater than the thickness of the tunneling layer (20nm-300 nm).
And (3) carrying out P + doping manufacture (front boron diffusion) on the front surface of the second structural body to form a P-type layer to form a PN junction, and then carrying out edge and back etching to obtain a third structural body. After the front boron diffusion, the surface sheet resistance of the formed P-type layer is 80 ohm/□ to 300 ohm/□, namely the diffusion sheet resistance.
On the front side of the third structure (front side plated with Al)2O3) Passivating film to obtain a fourth junctionA structure body.
And respectively manufacturing (SiNx plating) antireflection films on the front surface and the back surface of the fourth structural body to obtain a fifth structural body. Electrodes are formed (printed and sintered) on the front and back surfaces of the fifth structure, respectively.
The cell obtained according to this example can achieve a Voc performance of 710.2mV, a Jsc performance of 40.2A, an FF performance of 81.6% and an Eff performance of 23.30%.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A preparation method of a crystalline silicon solar passivated contact cell is characterized by comprising the following steps:
manufacturing a tunneling layer on the back of the N-type crystalline silicon to obtain a first structure body;
manufacturing an n + doped polycrystalline silicon passivation layer on the back surface of the tunneling layer, and then etching the edge and the front surface to obtain a second structural body;
carrying out P + doping on the front surface of the second structure body to manufacture a P-type layer, and then carrying out edge and back etching to obtain a third structure body;
manufacturing a passivation film on the front surface of the third structure body to obtain a fourth structure body;
respectively manufacturing antireflection films on the front surface and the back surface of the fourth structural body to obtain a fifth structural body;
and forming electrodes on the front surface and the back surface of the fifth structure body, respectively.
2. The method for preparing a crystalline silicon solar passivated contact cell according to claim 1 wherein the material of the tunneling layer is silicon dioxide.
3. The method of claim 1, wherein the tunneling layer is fabricated by thermal oxidation, ozone, wet oxidation, or atomic layer deposition.
4. The method for preparing a crystalline silicon solar passivated contact cell according to any of the claims 1 to 3, characterized in that the thickness of the tunneling layer is 0.5 to 3 nanometers.
5. The method for preparing a crystalline silicon solar passivated contact cell according to claim 1 wherein fabricating the n + doped polysilicon passivation layer comprises fabricating a polysilicon film and n + doping, and the polysilicon film is performed by low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and the n + doping is performed by low pressure ion implantation or thermal diffusion;
alternatively, the p + doping is performed by low pressure ion implantation or thermal diffusion.
6. The method for preparing a crystalline silicon solar passivated contact cell according to claim 1 or 5 wherein the thickness of the n + doped polysilicon passivation layer is 20 to 300 nanometers.
7. The method for preparing the crystalline silicon solar passivated contact cell of claim 1 wherein the surface sheet resistance of the P-type layer is 80 ohm/□ to 300 ohm/□.
8. The method for preparing a crystalline silicon solar passivated contact cell according to claim 1, characterized in that the material of the passivation film is aluminum oxide and/or the material of the antireflective film is silicon nitride.
9. The method for preparing a crystalline silicon solar passivated contact cell according to claim 1 wherein the edge and front side etching, the edge and back side etching are performed independently by chemical wet etching or dry etching respectively.
10. A method of making a crystalline silicon solar passivated contact cell, the cell comprising: a substrate and upper and lower electrodes respectively positioned on top and bottom surfaces of the substrate; the substrate comprises N-type crystalline silicon and a front surface structure and a back surface structure which are respectively positioned on the front surface and the back surface of the N-type crystalline silicon; the front structure comprises a P + doped P-type layer, an aluminum oxide passivation film and a silicon nitride antireflection film which are sequentially laminated; the back structure comprises a silicon dioxide tunneling layer, an n + doped polysilicon passivation layer and a silicon nitride antireflection film which are sequentially laminated, and is characterized in that the preparation method comprises the following steps:
before the P + doped P-type layer is manufactured, the silicon dioxide tunneling layer and the n + doped polysilicon passivation layer are manufactured in sequence.
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Application publication date: 20200828 |