CN113544827A - 一种芯片的封装方法及封装结构 - Google Patents
一种芯片的封装方法及封装结构 Download PDFInfo
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- CN113544827A CN113544827A CN202180001992.8A CN202180001992A CN113544827A CN 113544827 A CN113544827 A CN 113544827A CN 202180001992 A CN202180001992 A CN 202180001992A CN 113544827 A CN113544827 A CN 113544827A
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Abstract
本公开内容提供一种芯片的封装方法及封装结构,所述芯片的封装方法,包括:将至少两个芯片经由粘附层贴合在一衬底的一侧上,其中,所述芯片的元件面朝向所述衬底,所述衬底中设置有衬底布线结构和/或芯片;对设置在所述衬底的一侧上的至少两个芯片进行减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度;对经减薄处理的芯片塑封以形成塑封布置层,在所述衬底上沿塑封方向堆叠至少两层所述塑封布置层;在经减薄处理的芯片上打孔,形成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层的第一互连孔。实现芯片减薄后能够进行更高密度和更多叠层的3D互连,并且降低对打孔设备的要求,有利于器件性能的提升。
Description
技术领域
本公开内容涉及微电子封装领域,具体涉及芯片封装,尤其涉及一种芯片的封装方法及封装结构。
背景技术
随着接近摩尔定律的物理极限,集成电路领域将面临新的改革,这要求芯片尺寸越来越小,性能越来越高。目前,三维封装是满足各项标准符合制造要求的有效方法,三维封装是通过互连孔技术来实现上下层的互连。然而目前通过三维封装实现的多层堆叠的半导体结构由于每层的厚度限制等因素,导致封装的芯片散热效果并不理想,并因此不能满足更多叠层的架构需求。
发明内容
为了解决本领域已知存在的技术问题,本公开旨在提供一种芯片的封装方法及封装结构。例如能够实现在衬底贴上芯片后,选择性仅对各芯片的厚度进行减薄,而不对其他结构造成影响,进而实现了芯片更好的散热性能,减薄后能够进行更高密度和更多叠层的3D互连,并且降低对打孔设备的要求,有利于器件性能的提升。
在下文中将给出关于本公开内容的简要概述,以便提供关于本公开内容某些方面的基本理解。应当理解,此概述并不是关于本公开内容的穷举性概述。它并不是意图确定本公开内容的关键或重要部分,也不是意图限定本公开内容的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
根据本公开内容,提供了一种芯片的封装方法,包括:将至少两个芯片经由粘附层贴合在一衬底的一侧上,其中,所述芯片的元件面朝向所述衬底,所述衬底中设置有衬底布线结构和/或芯片;对设置在所述衬底的一侧上的至少两个芯片进行减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度;对经减薄处理的芯片塑封以形成塑封布置层,在所述衬底上沿塑封方向堆叠至少两层所述塑封布置层;在经减薄处理的芯片上打孔,形成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层的第一互连孔。
可选地,所述至少两层所述塑封布置层中的相邻的两层所述塑封布置层之间、沿塑封方向依次形成有封装布线层、粘附层或者依次形成有绝缘层、封装布线层和粘附层。
可选地,所述衬底中设置有芯片,包括:将至少两个芯片设置在所述衬底中的不同位置处且在所述衬底的厚度方向上的相同或不同的高度处。
可选地,所述在经减薄处理的芯片上打孔,形成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层的第一互连孔,包括:从与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片或所述衬底布线结构的第一互连孔。
可选地,还包括:从所述绝缘层的表面打孔,形成贯通所述绝缘层延伸至所述塑封布置层以连接所述塑封布置层中的芯片的第二互连孔。
可选地,还包括:从不与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述不与所述衬底相邻的塑封布置层和所述粘附层以连接至所述封装布线层的第三互连孔。
可选地,还包括:从不与所述衬底相邻的塑封布置层的表面打孔,形成依次贯通所述不与所述衬底相邻的塑封布置层、所述粘附层、所述封装布线层、与所述衬底相邻的塑封布置层延伸至所述衬底以连接所述衬底中的芯片的第四互连孔。
可选地,所述第一互连孔、所述第二互连孔、所述第三互连孔和所述第四互连孔中的每一个的孔径均小于所述芯片的宽度。
可选地,所述芯片的厚度是相同或不同的。
可选地,所述芯片被减薄之前的厚度包括在0至150μm之间。
可选地,所述芯片被减薄之后的厚度包括在0至20μm之间。
可选地,所述塑封布置层的厚度大于所述经减薄处理的芯片的厚度。
可选地,所述刻蚀芯片包括利用酸性液体、碱性液体、或等离子气体对芯片进行刻蚀。
可选地,所述减薄处理包括减薄和抛光处理。
可选地,所述衬底布线结构为在硅、玻璃、有机载版、或金属与绝缘的复合材料上的图案。
可选地,所述衬底为由硅、氧化硅、玻璃、氮化硅、复合材料、或塑封树脂材料制成的面板或晶圆。
可选地,所述粘附层由半固化干膜、液体、或者金属制成。
可选地,制成所述塑封布置层的材料包括以下之一:绝缘物质、聚酰亚胺、苯并环丁烯、派瑞林、工业化液晶聚合物、环氧树脂、硅氧化、硅氮化物、铝氧化物。
根据本公开内容,还提供了一种芯片的封装结构,包括:一衬底,所述衬底中设置有衬底布线结构和/或芯片;至少两层塑封布置层,配置成在所述衬底的一侧上沿塑封方向堆叠,其中,所述塑封布置层中的每一层包括至少两个芯片,所述塑封布置层中的芯片的元件面朝向所述衬底,所述塑封布置层中的芯片配置成经由粘附层贴合在所述衬底的一侧上后被实施减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度;第一互连孔,配置成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层。
可选地,所述至少两层所述塑封布置层中的相邻的两层所述塑封布置层之间、沿所述塑封方向依次形成有封装布线层、粘附层或者依次形成有绝缘层、封装布线层和粘附层。
可选地,还包括:至少两个芯片设置在所述衬底中的不同位置处且在所述衬底的厚度方向上的相同或不同的高度处。
可选地,所述第一互连孔,还配置成从与所述衬底相邻的塑封布置层的表面起,贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片。
可选地,还包括:第二互连孔,配置成从所述绝缘层的表面起,贯通所述绝缘层延伸至所述塑封布置层以连接所述塑封布置层中的芯片。
可选地,还包括:第三互连孔,配置成从不与所述衬底相邻的塑封布置层的表面起,形成贯通所述不与所述衬底相邻的塑封布置层和所述粘附层以连接至所述封装布线层。
可选地,还包括:第四互连孔,配置成从不与所述衬底相邻的塑封布置层的表面起,依次贯通所述不与所述衬底相邻的塑封布置层、所述粘附层、所述封装布线层、与所述衬底相邻的塑封布置层延伸至所述衬底以连接所述衬底中的芯片。
可选地,所述第一互连孔、所述第二互连孔、所述第三互连孔和所述第四互连孔中的每一个的孔径均小于所述芯片的宽度。
可选地,所述芯片的厚度是相同或不同的。
可选地,所述芯片被减薄之前的厚度包括在0至150μm之间。
可选地,所述芯片被减薄之后的厚度包括在0至20μm之间。
可选地,所述塑封布置层的厚度大于所述经减薄处理的芯片的厚度。
可选地,所述刻蚀芯片包括利用酸性液体、碱性液体、或等离子气体对芯片进行刻蚀。
可选地,所述减薄处理包括减薄和抛光处理。
可选地,所述衬底布线结构为在硅、玻璃、有机载版、或金属与绝缘的复合材料上的图案。
可选地,所述衬底为由硅、氧化硅、玻璃、氮化硅、复合材料、或塑封树脂材料制成的面板或晶圆。
可选地,所述粘附层由半固化干膜、液体、或者金属制成。
可选地,制成所述塑封布置层的材料包括以下之一:绝缘物质、聚酰亚胺、苯并环丁烯、派瑞林、工业化液晶聚合物、环氧树脂、硅氧化、硅氮化物、铝氧化物。
本公开内容的方案至少能有助于实现如下效果之一:选择性芯片表面减薄,避免了利用键合设备工艺,提高了与其他工艺的兼容性;更好的芯片散热性能,更高密度和更多叠层的连线架构,减少光刻、掩膜等工艺步骤,降低打孔深度从而减低对打孔设备的要求等。
附图说明
下面参照附图说明本公开内容的具体内容,这将有助于更加容易地理解本公开内容的以上和其他目的、特点和优点。附图只是为了示出本公开内容的原理。在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中:
图1示出了根据本公开实施方式的芯片的封装方法的流程示意图;
图2-23示出了根据本公开实施方式的芯片的示意性剖视图;
图24示出了根据本公开实施方式的芯片的示意性剖视图。
具体实施方式
在下文中将结合附图对本公开内容的示例性公开内容进行描述。为了清楚和简明起见,在说明书中并未描述实现本公开内容的所有特征。然而,应该了解,在开发任何实现本公开内容的过程中可以做出很多特定于本公开内容的决定,以便实现开发人员的具体目标,并且这些决定可能会随着本公开内容的不同而有所改变。
在此,还需要说明的是,为了避免因不必要的细节而模糊了本公开内容,在附图中仅仅示出了与根据本公开内容的方案密切相关的器件结构,而省略了与本公开内容关系不大的其他细节。
应理解的是,本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。本公开内容中,在可行的情况下,不同实施方案之间的特征可替换或借用、以及在一个实施方案中可省略一个或多个特征。
在以下具体实施方案中可参照附图,附图形成了本公开内容的一部分并例示了示例性实施方案。此外,应理解的是,在不脱离所请求保护的主题的范围的情况下,可以利用其它实施方案并可以做出结构和/或逻辑改变。还应当指出,方向和参照(例如,上、下、顶部、底部、等等)仅用于帮助对附图中的特征的描述,并非在限制性意义上仅采用以下具体实施方案。
如在本公开内容的说明书和所附权利要求书中所使用的,除非上下文另外明确指示,单数形式“一”、“一个”和“所述”也包括复数形式。还将理解的是,如本文中所使用的术语“和/或”指代并包括相关联的列出的项中的一个或多个的任何和所有可能的组合。
参照图1来描述根据本公开实施方式的芯片的封装方法,图1示出了根据本公开实施方式的芯片的封装方法的流程示意图。
如图1所示,在本公开实施方式中,所述芯片的封装方法,包括:
步骤101,将至少两个芯片由粘附层贴合在一衬底的一侧上,其中,所述芯片的元件面朝向所述衬底,所述衬底中设置有衬底布线结构和/或芯片。
本公开实施方式中,封装衬底的材料可以根据实际需求进行选取,并不限制衬底的具体材质。可选地,所述衬底可以由硅、氧化硅、玻璃、氮化硅、复合材料、塑封树脂等材料制成的面板或晶圆,其厚度可以为0~500μm。可选地,所述衬底可以是不包含任何用于电路连接的裸片;可选地,所述衬底中可以包含至少一个或多个用于电路连接的芯片;可选地,所述衬底布线结构可以是在硅、玻璃、有机载版、或金属与绝缘的复合材料上的图案;
可选地,粘附层可以是半固化干膜,液体、或者金属,当贴合完成以后可以通过进一步的固化、扩散、和/或焊接等操作来增强芯片与衬底之间的结合。
步骤102,对设置在所述衬底的一侧上的至少两个芯片进行减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度。
这里刻蚀芯片以减小芯片的厚度可以是在将芯片贴合/粘附在衬底上后,将整个器件一起进行浸泡湿刻以实现刻蚀减薄,或者优选地,采用选择性刻蚀方法:选择性地仅刻蚀芯片以减小芯片的厚度而不对其他结构造成影响。可选地,刻蚀芯片包括用酸性液体、碱性液体、等离子等气体对芯片进行刻蚀。可以理解的是基于本公开实施方式的减薄处理,可以使得芯片厚度变薄,进而使得本公开实施方式的整个芯片的封装结构的厚度减小,以能够实现本公开的芯片的多层堆叠结构。又由于芯片的减薄而降低了打孔深度,从而对打孔设备诸如TSV打孔设备的要求降低,进而降低了芯片封装的工业成本以及提高了生产效率。可选地,减薄处理包括减薄和抛光等处理。
步骤103,对经减薄处理的芯片塑封以形成塑封布置层,在所述衬底上沿塑封方向堆叠至少两层所述塑封布置层。
这里形成塑封布置层可以是将经减薄处理的至少两个芯片在所述衬底的表面上塑封以形成注塑封装成型的塑封布置层。可选地,塑封布置层的厚度大于经减薄处理的芯片的厚度。可选地,制成所述塑封布置层的材料可以包括:绝缘物质、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene,BCB)、派瑞林(parylene)、工业化液晶聚合物(liquid crystal polymer,LCP)、环氧树脂、硅氧化、硅氮化物、铝氧化物等。
这里堆叠至少两层所述塑封布置层可以是在衬底的一侧上形成一层塑封布置层,再在该层塑封布置层的表面上继续形成第二层塑封布置层,第二层塑封布置层的形成方式类似于第一层塑封布置层:可以将至少两个芯片设置在形成在第一层塑封布置层上的一粘附层上,对设置在所述粘附层上的至少两个芯片进行减薄处理,然后对经减薄处理的至少两个芯片在所述粘附层上塑封以形成该第二层塑封布置层,进而实现了两层塑封布置层的堆叠,以此类推可以在衬底上堆叠更多层塑封布置层。
步骤104,在经减薄处理的芯片上打孔,形成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层的第一互连孔。
这里在经减薄处理的芯片上打孔可以是在对经减薄处理后的芯片进行塑封后进行,由于塑封布置层的厚度要大于经减薄处理后的芯片,因此打孔可以先从塑封布置层的表面开始向芯片打孔,进而贯穿芯片以延伸到衬底中的布线结构、或衬底中的芯片、或该塑封布置层或其他塑封布置层中,形成第一互连孔,因芯片的厚度被减薄进而能够容易地钻出所需互连孔。
可选地,所述至少两层所述塑封布置层中的相邻的两层所述塑封布置层之间、沿所述堆叠的方向依次形成有封装布线层、粘附层或者依次形成有绝缘层、封装布线层和粘附层。
通常来说,粘附层需要由绝缘材料制成,而粘附层是绝缘的情况下无需形成绝缘层,这里的绝缘层可以是在粘附层不绝缘的情况下设置的。这里粘附层的作用与前述使得最靠近衬底的一层塑封布置层中的芯片作用类似,可以是用于在其上形成塑封布置层、使得塑封布置层中的芯片粘附于其上。
可选地,还包括:将至少两个芯片设置在所述衬底中的不同位置处且在所述衬底的厚度方向上的相同或不同的高度处。换句话说,不同的芯片可以设置在衬底中的不同空间位置处。可选地,不同的芯片可以根据相对于衬底的上层的塑封布置层中的芯片进行对位。
可选地,还包括:从与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片的第一互连孔。
可选地,还包括:从所述绝缘层的表面打孔,形成贯通所述绝缘层延伸至所述塑封布置层以连接所述塑封布置层中的芯片的第二互连孔。
可选地,还包括:从不与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述不与所述衬底相邻的塑封布置层和所述粘附层以连接至所述封装布线层的第三互连孔。
可选地,还包括:从不与所述衬底相邻的塑封布置层的表面打孔,形成依次贯通所述不与所述衬底相邻的塑封布置层、所述粘附层、所述封装布线层、与所述衬底相邻的塑封布置层延伸至所述衬底以连接所述衬底中的芯片的第四互连孔。
可选地,所述第一互连孔、所述第二互连孔、所述第三互连孔和所述第四互连孔中的每一个的孔径均小于所述芯片的宽度。
可选地,所述芯片的厚度是相同或不同的。
可选地,所述芯片被减薄之前的厚度包括在0至150μm之间。
可选地,所述芯片被减薄之后的厚度包括在0至20μm之间。这里,在将芯片粘附在粘附层/衬底上后,可以选择性地专门对芯片的厚度减薄到0至20μm之间,以达到技术性优势。
可选地,所述粘附层可以由抗酸和/或抗碱材料制成。可选地,所述粘附层可以被镀上保护层以抗刻蚀。
可选地,所述减薄处理包括湿法减薄。
本公开实施方式所提供的芯片的封装方法,由于芯片经减薄处理从而能够实现多层堆叠结构,使得整个芯片的厚度被降低因而具有更好的散热性能,其封装方式也更加简化,减少了键合设备(bonding equipment)以及化学机械研磨(chemical mechanicalpolish,CMP)的使用,降低了打孔深度从而减低对打孔设备的要求。
为了更好的理解本公开实施方式提供的芯片的封装方法,下面将根据本公开实施方式的具有两层塑封布置层的芯片的封装方法为例,结合图2至图23,详细阐述根据本实施方式的芯片的封装流程:
步骤S1,在衬底上贴上芯片。
如图2所示,衬底100可以是硅、氧化硅、玻璃、氮化硅、复合材料、塑封树脂或其它材料,其厚度为0~500μm;101可以为不导电的第一粘附层,覆盖在衬底上;图中包括芯片1、芯片2、芯片3,这里例示了3个芯片,也可以是其他任何数量,芯片1、芯片2、芯片3可以是带器件的芯片或裸的芯片。
步骤S2,蚀刻减薄芯片。
如图3所示,相比于图2所示的芯片,其厚度被减薄,具体地,可以选用选择性蚀刻方式,只蚀刻芯片1、芯片2、芯片3,而不蚀刻第一粘附层101,可以通过控制蚀刻速率来实现预定的蚀刻厚度,可以通过控制第一粘附层和芯片表面刻蚀的选择比来控制蚀刻。也可以用化学气相沉积(chemical vapor deposition,CVD),原子层沉积(atomic layerdeposition,ALD)等方式蚀刻前镀层保护膜(图3未示出)来对侧壁和粘附层进行保护。
步骤S3,注塑封装成型以及平整化。
如图4所示,在粘附层上形成第一塑封布置层102,该第一塑封布置层102将芯片包裹在其中,经过固化后磨平,但不侵蚀到芯片中,形成如图5所示的封装结构。
步骤S4,在塑封面和芯片上进行刻孔。
如图6所示,示例出在芯片2、芯片3以及塑封面上进行刻孔,刻孔可以采用激光刻蚀法或者深反离子刻蚀法,芯片2、芯片3的厚度小于200μm,在102层上形成图案光刻胶层(图中未示出),然后进行深度刻蚀,打孔深度可以穿过第一塑封布置层102、第一粘附层101到达衬底100,以连接衬底100中的芯片,如图6所示出的打出的四个孔111对应如上所述的第一互连孔。
从与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片的第一互连孔。
步骤S5,在孔的内部壁上沉积绝缘体(未在附图中示出)。
步骤S6,孔的内部壁上沉积绝缘体镀种子层后填充导电材料并磨平表面。
如图7所示,连接衬底100中的器件,最后去除光刻胶层。
步骤S7,在第一塑封布置层102的表面上沉积一层绝缘层103。
如图8所示,可通过旋转涂布的方式覆盖进行,也可进行真空覆膜。
步骤S8,在塑封面和芯片上进行刻孔。
如图9所示,在绝缘层103上以及对芯片1和芯片2刻孔,形成贯通绝缘层103延伸至第一塑封布置层102以连接塑封布置层102中的芯片的第二互连孔112。
步骤S9,孔的内部壁上沉积绝缘体镀种子层后填充导电材料并磨平表面,如图10所示。
步骤S10,在绝缘层103的表面上沉积一层第一封装布线层104,在该104层上刻蚀第一RDL线槽121,如图11、12所示。
步骤S11,在第一RDL线槽121内填充导电材料,如图13所示。
步骤S12,在第一封装布线层104的表面附上第二粘附层105,第二粘附层105可以由绝缘材料制成,如图14所示。
步骤S13,在第二粘附层105上粘附芯片4、芯片5、芯片6,如图15所示。
步骤S14,蚀刻减薄芯片4、芯片5、芯片6,如图16所示。
步骤S15,注塑封装成型,形成第二塑封布置层106如图17所示。
步骤S16,平整化,如图18所示。
步骤S17,打孔113、114。
如图19所示,形成贯通第二塑封布置层106和第二粘附层105以延伸至第一封装布线层104中的第一RDL线槽121的第三互连孔113,以及形成依次贯通第二塑封布置层106、第二粘附层105、第一封装布线层104、绝缘层103、第一塑封布置层102、第一粘附层101延伸至衬底100以连接衬底100中的芯片的21114。
步骤S18,填孔,如图20所示,具体可以参照前述填孔操作进行实施。
步骤S19,如图21所示,在表面上沉积一层第二封装布线层107。
步骤S20,如图22所示,刻蚀第二RDL线槽122,填充导电材料。
步骤S21,在第二封装布线层107的表面附上一层第三粘附层108,第三粘附层108可以由绝缘材料制成,如图23所示。
步骤S22,在第三粘附层108上粘合芯片7、芯片8、芯片9,如图23所示。
可选地,按步骤S1~S22沿衬底100的厚度方向上持续往上叠层,形成根据本实施方式的芯片的封装结构。
参照图24来描述根据本公开实施方式的芯片,图24例示了根据本公开实施方式的具有两层塑封布置层的芯片的示意性剖视图。
本公开实施例公开的芯片包括一衬底,所述衬底中设置有衬底布线结构和/或芯片;至少两层塑封布置层,配置成在所述衬底的一侧上沿塑封方向堆叠,其中,所述塑封布置层中的每一层包括至少两个芯片,所述塑封布置层中的芯片的元件面朝向所述衬底,所述塑封布置层中的芯片配置成经由粘附层贴合在所述衬底的一侧上后被实施减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度;第一互连孔,配置成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层。
以如图24例示的具有两层塑封布置层的芯片为例,芯片包括至少两层塑封布置层:第一塑封布置层102、第二塑封布置层106,在衬底100的一侧上沿厚度方向堆叠,第一塑封布置层102或第二塑封布置层106中包括至少2个芯片,其中,所述至少2个芯片配置成在被设置在衬底100的一侧或第一粘附层101/第二粘附层105/第三粘附层108上后被实施减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度。
可选地,所述至少2个芯片配置成在被设置在所述衬底的一侧,包括:所述至少2个芯片粘附在形成于所述陈埭的一侧的一粘附层上。以如图24为例,至少2个芯片配置成在被设置在衬底100的一侧,包括:所述至少2个芯片粘附在形成于衬底100的一侧的第一粘附层101上。
可选地,所述至少两层所述塑封布置层中的相邻的两层所述塑封布置层之间、沿所述堆叠的方向依次形成有封装布线层、粘附层或者依次形成有绝缘层、封装布线层和粘附层。通常来说,粘附层需要由绝缘材料制成,而粘附层是绝缘的情况下无需设置绝缘层,这里的绝缘层可以是在粘附层不绝缘的情况下设置的。这里粘附层的作用与前述使得最靠近衬底的一层塑封布置层中的芯片作用类似,可以是用于在其上形成塑封布置层、使得塑封布置层中的芯片粘附于其上。
以图24为例,第一塑封布置层102与第二塑封布置层106之间、沿堆叠的方向依次形成有绝缘层103、第一封装布线层、第二粘附层105。
可选地,本公开实施方式的芯片还包括:至少2个芯片设置在所述衬底中的不同位置处且在所述衬底的厚度方向上的相同或不同的高度处。
可选地,本公开实施方式的芯片还包括:
第一互连孔,配置成从与所述衬底相邻的塑封布置层的表面起,贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片。以图24为例,第一互连孔111,配置成从与衬底100相邻的第一塑封布置层102的表面起,贯通与衬底100相邻的第一塑封布置层102和第一粘附层101延伸至衬底100以连接衬底100中的芯片。
可选地,本公开实施方式的芯片还包括:
第二互连孔,配置成从所述绝缘层的表面起,贯通所述绝缘层延伸至所述塑封布置层以连接所述塑封布置层中的芯片。以图24为例,第二互连孔112,配置成从绝缘层103的表面起,贯通绝缘层103延伸至第一塑封布置层102以连接塑封布置层102中的芯片。
可选地,本公开实施方式的芯片还包括:
第三互连孔,配置成从不与所述衬底相邻的塑封布置层的表面起,形成贯通所述不与所述衬底相邻的塑封布置层和所述粘附层以连接至所述封装布线层。以图24为例,第三互连孔113,配置成从第二塑封布置层106的表面起,形成贯通第二塑封布置层106和第二粘附层105以连接至所述第一封装布线层104。
可选地,本公开实施方式的芯片还包括:
第四互连孔,配置成从不与所述衬底相邻的塑封布置层的表面起,依次贯通所述不与所述衬底相邻的塑封布置层、所述粘附层、所述封装布线层、与所述衬底相邻的塑封布置层延伸至所述衬底以连接所述衬底中的芯片。以图24为例,配置成从第二塑封布置层106的表面起,依次贯通第二塑封布置层106、第二粘附层105、第一封装布线层104、第一塑封布置层102延伸至衬底100以连接衬底100中的芯片。
可选地,所述第一互连孔、所述第二互连孔、所述第三互连孔和所述第四互连孔中的每一个的孔径均小于所述芯片的宽度。
可选地,所述芯片的厚度是相同或不同的。
可选地,所述芯片被减薄之前的厚度包括在0至150μm之间。
可选地,所述芯片被减薄之后的厚度包括在0至20μm之间。
可选地,所述粘附层由绝缘材料制成。
可选地,所述绝缘层上刻蚀有重布线层槽(RDL slot),其中,所述重布线层槽中填充有导电材料。
可选地,所述第一互连孔、所述第二互连孔、所述第三互连孔和/或所述第四互连孔中填充有导电材料。
可选地,所述塑封布置层的厚度大于所述经减薄处理的芯片的厚度。
可选地,所述刻蚀芯片包括利用酸性液体、碱性液体、或等离子气体对芯片进行刻蚀。
可选地,所述减薄处理包括减薄和抛光处理。
可选地,所述衬底布线结构为在硅、玻璃、有机载版、或金属与绝缘的复合材料上的图案。
可选地,所述衬底为由硅、氧化硅、玻璃、氮化硅、复合材料、或塑封树脂材料制成的面板或晶圆。
可选地,所述粘附层由半固化干膜、液体、或者金属制成。
可选地,制成所述塑封布置层的材料包括以下之一:绝缘物质、聚酰亚胺、苯并环丁烯、派瑞林、工业化液晶聚合物、环氧树脂、硅氧化、硅氮化物、铝氧化物。
需要说明的是,图24仅示意性地例示出具有两层塑封布置层的芯片的封装结构,实际应用中,本公开实施方式可以具有更多层堆叠结构,其具体构造可以是以图24所示的两层塑封布置层的封装结构为基础进行更多层堆叠而形成,其具体地封装方法可以参照上文中描述的芯片的封装方法来理解。
本公开实施方式所提供的芯片,由于包含了经减薄处理的芯片从而能够实现多层堆叠结构,使得整个芯片的厚度被降低因而具有更好的散热性能,其封装方式也更加简化,减少了键合设备(bonding equipment),化学机械研磨(CMP)的使用,降低了打孔深度从而减低对打孔设备的要求。
以上结合具体的实施方案对本公开内容进行了描述,但本领域技术人员应该清楚,这些描述都是示例性的,并不是对本公开内容的保护范围的限制。本领域技术人员可以根据本公开内容的精神和原理对本公开内容做出各种变型和修改,这些变型和修改也在本公开内容的范围内。
工业实用性
本公开实施方式提供了芯片封装结构和封装方法,由于本公开实施方式中的芯片经减薄处理从而能够实现多层堆叠结构。本公开实施方式提供的芯片的封装方法可以解决已知的化学机械方法磨平、多层的金属导线布线会越来越难的问题。实现的芯片减薄可以提高与其他工艺的兼容性,使得整个芯片的厚度被降低因而具有更好的散热性能;降低了打孔深度从而减低对打孔工艺的要求,让其封装方式也更加快速从而提高了产能;可以解决硅互连孔技术的大量技术难点:产能低、制程温度高、可实现的互连孔密度低、易碎裂、影响硅特性、成本过高、不能弯折等难点。芯片的减薄对扇出和3D集成封装有很大益处,可以保证***的可弯折性和高性能,并提升整个***的可靠性。
Claims (36)
1.一种芯片的封装方法,包括:
将至少两个芯片经由粘附层贴合在一衬底的一侧上,其中,所述芯片的元件面朝向所述衬底,所述衬底中设置有衬底布线结构和/或芯片;
对设置在所述衬底的一侧上的至少两个芯片进行减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度;
对经减薄处理的芯片塑封以形成塑封布置层,在所述衬底上沿塑封方向堆叠至少两层所述塑封布置层;
在经减薄处理的芯片上打孔,形成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层的第一互连孔。
2.根据权利要求1所述的芯片的封装方法,其特征在于,所述至少两层所述塑封布置层中的相邻的两层所述塑封布置层之间、沿塑封方向依次形成有封装布线层、粘附层或者依次形成有绝缘层、封装布线层和粘附层。
3.根据权利要求1或2所述的芯片的封装方法,其特征在于,所述衬底中设置有芯片,包括:
将至少两个芯片设置在所述衬底中的不同位置处且在所述衬底的厚度方向上的相同或不同的高度处。
4.根据权利要求2或3所述的芯片的封装方法,其特征在于,所述在经减薄处理的芯片上打孔,形成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层的第一互连孔,包括:
从与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片或所述衬底布线结构的第一互连孔。
5.根据权利要求2至4任一项所述的芯片的封装方法,其特征在于,还包括:
从所述绝缘层的表面打孔,形成贯通所述绝缘层延伸至所述塑封布置层以连接所述塑封布置层中的芯片的第二互连孔。
6.根据权利要求2至5任一项所述的芯片的封装方法,其特征在于,还包括:
从不与所述衬底相邻的塑封布置层的表面打孔,形成贯通所述不与所述衬底相邻的塑封布置层和所述粘附层以连接至所述封装布线层的第三互连孔。
7.根据权利要求2至6任一项所述的芯片的封装方法,其特征在于,还包括:
从不与所述衬底相邻的塑封布置层的表面打孔,形成依次贯通所述不与所述衬底相邻的塑封布置层、所述粘附层、所述封装布线层、与所述衬底相邻的塑封布置层延伸至所述衬底以连接所述衬底中的芯片的第四互连孔。
8.根据权利要求7所述的芯片的封装方法,其特征在于,所述第一互连孔、所述第二互连孔、所述第三互连孔和所述第四互连孔中的每一个的孔径均小于所述芯片的宽度。
9.根据权利要求1至8任一项所述的芯片的封装方法,其特征在于,所述芯片的厚度是相同或不同的。
10.根据权利要求1至9任一项所述的芯片的封装方法,其特征在于,所述芯片被减薄之前的厚度包括在0至150μm之间。
11.根据权利要求1至10任一项所述的芯片的封装方法,其特征在于,所述芯片被减薄之后的厚度包括在0至20μm之间。
12.根据权利要求1至11任一项所述的芯片的封装方法,其特征在于,所述塑封布置层的厚度大于所述经减薄处理的芯片的厚度。
13.根据权利要求1至12任一项所述的芯片的封装方法,其特征在于,所述刻蚀芯片包括利用酸性液体、碱性液体、或等离子气体对芯片进行刻蚀。
14.根据权利要求1至13任一项所述的芯片的封装方法,其特征在于,所述减薄处理包括减薄和抛光处理。
15.根据权利要求1至14任一项所述的芯片的封装方法,其特征在于,所述衬底布线结构为在硅、玻璃、有机载版、或金属与绝缘的复合材料上的图案。
16.根据权利要求1至15任一项所述的芯片的封装方法,其特征在于,所述衬底为由硅、氧化硅、玻璃、氮化硅、复合材料、或塑封树脂材料制成的面板或晶圆。
17.根据权利要求1至16任一项所述的芯片的封装方法,其特征在于,所述粘附层由半固化干膜、液体、或者金属制成。
18.根据权利要求1至17任一项所述的芯片的封装方法,其特征在于,制成所述塑封布置层的材料包括以下之一:绝缘物质、聚酰亚胺、苯并环丁烯、派瑞林、工业化液晶聚合物、环氧树脂、硅氧化、硅氮化物、铝氧化物。
19.一种芯片的封装结构,包括:
一衬底,所述衬底中设置有衬底布线结构和/或芯片;
至少两层塑封布置层,配置成在所述衬底的一侧上沿塑封方向堆叠,其中,所述塑封布置层中的每一层包括至少两个芯片,所述塑封布置层中的芯片的元件面朝向所述衬底,所述塑封布置层中的芯片配置成经由粘附层贴合在所述衬底的一侧上后被实施减薄处理,所述减薄处理包括仅刻蚀芯片以减小芯片的厚度;
第一互连孔,配置成连接所述经减薄处理的芯片与所述衬底布线结构、所述衬底中的芯片、或所述塑封布置层。
20.根据权利要求19所述的芯片的封装结构,其特征在于,所述至少两层所述塑封布置层中的相邻的两层所述塑封布置层之间、沿所述塑封方向依次形成有封装布线层、粘附层或者依次形成有绝缘层、封装布线层和粘附层。
21.根据权利要求19或20所述的芯片的封装结构,其特征在于,还包括:至少两个芯片设置在所述衬底中的不同位置处且在所述衬底的厚度方向上的相同或不同的高度处。
22.根据权利要求20或21所述的芯片的封装结构,其特征在于,所述第一互连孔,还配置成从与所述衬底相邻的塑封布置层的表面起,贯通所述与所述衬底相邻的塑封布置层和所述粘附层延伸至所述衬底以连接所述衬底中的芯片。
23.根据权利要求20至22任一项所述的芯片的封装结构,其特征在于,还包括:
第二互连孔,配置成从所述绝缘层的表面起,贯通所述绝缘层延伸至所述塑封布置层以连接所述塑封布置层中的芯片。
24.根据权利要求20至23任一项所述的芯片的封装结构,其特征在于,还包括:
第三互连孔,配置成从不与所述衬底相邻的塑封布置层的表面起,形成贯通所述不与所述衬底相邻的塑封布置层和所述粘附层以连接至所述封装布线层。
25.根据权利要求20至24任一项所述的芯片的封装结构,其特征在于,还包括:
第四互连孔,配置成从不与所述衬底相邻的塑封布置层的表面起,依次贯通所述不与所述衬底相邻的塑封布置层、所述粘附层、所述封装布线层、与所述衬底相邻的塑封布置层延伸至所述衬底以连接所述衬底中的芯片。
26.根据权利要求25所述的芯片的封装结构,其特征在于,所述第一互连孔、所述第二互连孔、所述第三互连孔和所述第四互连孔中的每一个的孔径均小于所述芯片的宽度。
27.根据权利要求至19至26任一项所述的芯片的封装结构,其特征在于,所述芯片的厚度是相同或不同的。
28.根据权利要求19至27中任一项所述的芯片的封装结构,其特征在于,所述芯片被减薄之前的厚度包括在0至150μm之间。
29.根据权利要求19至28中任一项所述的芯片的封装结构,其特征在于,所述芯片被减薄之后的厚度包括在0至20μm之间。
30.根据权利要求19至29任一项所述的芯片的封装结构,其特征在于,所述塑封布置层的厚度大于所述经减薄处理的芯片的厚度。
31.根据权利要求19至30任一项所述的芯片的封装结构,其特征在于,所述刻蚀芯片包括利用酸性液体、碱性液体、或等离子气体对芯片进行刻蚀。
32.根据权利要求19至31任一项所述的芯片的封装结构,其特征在于,所述减薄处理包括减薄和抛光处理。
33.根据权利要求19至32任一项所述的芯片的封装结构,其特征在于,所述衬底布线结构为在硅、玻璃、有机载版、或金属与绝缘的复合材料上的图案。
34.根据权利要求19至33任一项所述的芯片的封装结构,其特征在于,所述衬底为由硅、氧化硅、玻璃、氮化硅、复合材料、或塑封树脂材料制成的面板或晶圆。
35.根据权利要求19至34任一项所述的芯片的封装结构,其特征在于,所述粘附层由半固化干膜、液体、或者金属制成。
36.根据权利要求19至35任一项所述的芯片的封装结构,其特征在于,制成所述塑封布置层的材料包括以下之一:绝缘物质、聚酰亚胺、苯并环丁烯、派瑞林、工业化液晶聚合物、环氧树脂、硅氧化、硅氮化物、铝氧化物。
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