TWI467674B - 微電子封裝組件及其製造方法 - Google Patents

微電子封裝組件及其製造方法 Download PDF

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Publication number
TWI467674B
TWI467674B TW100122822A TW100122822A TWI467674B TW I467674 B TWI467674 B TW I467674B TW 100122822 A TW100122822 A TW 100122822A TW 100122822 A TW100122822 A TW 100122822A TW I467674 B TWI467674 B TW I467674B
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Taiwan
Prior art keywords
die
package assembly
microelectronic package
substrate
conductive
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TW100122822A
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English (en)
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TW201216389A (en
Inventor
Ravi K Nalla
Mathew J Manusharow
Drew W Delaney
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Intel Corp
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Publication of TW201216389A publication Critical patent/TW201216389A/zh
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

微電子封裝組件及其製造方法
本發明之所揭示的實施例一般有關於微電子封裝組件，且更特別的是有關於無凸塊式增層封裝組件。
無凸塊式增層(BBUL)為用於微電子裝置的封裝技術，其中，此封裝組件包括被嵌入於基板中的至少一個晶粒(也稱為「晶片」)，此基板具有形成於此基板之上的一個或多個增層。在增層與晶粒接合墊之間的電氣連接可使用標準微介層(microvia)形成製程而被製成。BBUL封裝組件能夠使電氣迴路電感小，且使低介電常數(低-k)晶粒材料上的熱機械應力降低。其也允許高引線數、多個電子與光學組件(諸如，邏輯、記憶體、射頻(RF)、及微機電系統(MEMS)等等)的現成整合、以及固有的可調性(scalability)。BBUL封裝組件之現有的製程流程涉及將此基板建構於以銅箔覆蓋的暫時核心/或體上，在此封裝組件與此核心/載體分離之後，此銅箔被蝕除。
【發明內容和實施方式】
為了舉例說明的簡化及清楚起見，圖式繪示一般方式的結構，且熟知的特性及技術之說明及細節會予以省略，以避免不必混淆本發明之所述的實施例之討論。此外，圖式中的要素不必然按比例繪製。例如，圖式中的某些要素之尺寸可相對於其他要素而被誇大，以協助改善本發明的實施例之瞭解。不同圖式中之相同的參考標號代表相同的要素，而類似的參考標號可，但不必然，代表類似的要素。
說明書中及申請專利範圍中之術語「第一」、「第二」、「第三」、「第四」、等等(若有的話)被使用來區別類似元件，且不必然用於描述特定循序或按時間排列的順序。要瞭解的是，如此所使用的術語可依據適當的情況而交換，使得在此所述之本發明的實施例係例如可以除了在此所繪示或其他所述之外的順序而操作。同樣地，若方法在此被敘述為包含一系列的步驟，則如同在此所提出之此類步驟的順序不必然是可實施此類步驟的唯一順序，且所陳述的步驟之某些或許可被省略，及/或在此所未敘述的某些其他步驟或許可被加入此方法。再者，術語「包含」、「包括」、「具有」、及其任何變型係意謂涵蓋不排他性的包括，使得包含一系列之元件的程序、方法、物件、或設備不必然受限於那些元件，而是可包括此種程序、方法、物件、或設備之未明確列出或固有的其他元件。
說明書中及申請專利範圍中之術語「左」、「右」、「前」、「後」、「上」、「下」、「之上」、「之下」、等等(若有的話)被使用於說明的目的，且不必然用於描述固定的相對位置，除非其他特別或藉由上下文所表示。要瞭解的是，如此所使用的術語可依據適當的情況而交換，使得在此所述之本發明的實施例係例如可以除了在此所繪示或其他所述的方位之外的其他方位而操作。如在此所使用的術語「被耦接」係界定為以電氣或非電氣的方式而直接或間接地被連接。如為彼此「相鄰」之在此所述的物件可為彼此實體相接觸、彼此緊鄰、或在與彼此相同的一般地區或區域中，視使用此詞句的上下文而定。在此之「在一個實施例中」之此詞句的出現不必然全部關於相同實施例。
在本發明的一個實施例中，微電子封裝組件包含基板；晶粒(其在此也可被稱為晶片)，被嵌入於此基板內-此晶粒具有前側及相對的後側，且另具有至少一個矽穿孔於其中；複數個增層，與此晶粒的此前側相鄰，且被堆積於此晶粒的此前側之上；以及電源平面，與此晶粒的此後側相鄰且實體相接觸。在另一個實施例中，此微電子封裝組件包含基板；第一晶粒和第二晶粒，兩者皆被嵌入於此基板中，兩者皆具有前側及相對的後側，且兩者皆具有至少一個矽穿孔於其中；複數個增層，與此第一晶粒和此第二晶粒的此等前側相鄰，且被堆積於此第一晶粒和此第二晶粒的此等前側之上；以及導電結構，與此第一晶粒和此第二晶粒的此等後側相鄰且實體相接觸。
由於下面的討論將解釋清楚，所以本發明的實施例能夠使晶粒的主動側上之電源凸塊(或其他種類的凸塊)之數量降低，因而促進晶粒尺寸的降低。再者，本發明的實施例能夠可被稱為晶粒向下電源開啟(DDPU)系統，除了其他優點以外，其提供較佳的第二階互連部(SLI)返回路徑最佳化、使用於輸入/輸出(I/O)元件的訊號對接地增加成為可行、以及消除I/O與電源之間的惱人折衷。本發明之相同或其他的實施例能夠使封裝組件中的多個晶粒之間的可達成I/O密度增加。
現在參考圖式，圖1A為依據本發明的實施例之微電子封裝組件100的平面圖，而圖1B為依據本發明的實施例之微電子封裝組件100的剖面圖。圖1B為沿著圖1A中的線B-B所獲得到的。如圖1A及1B中所繪示，微電子封裝組件100包含基板110，及被嵌入於基板110內的晶粒120。晶粒120具有前側121(亦即，設置電晶體(未顯示出)於其上之側)，及相對的後側122。晶粒120另具有矽穿孔(TSV)123(其一直延伸至後側122，且被曝露在後側122)於其中。基板110包含複數個增層130(其中之一為介電層139)，複數個增層130與晶粒120的前側121相鄰，且被堆積於晶粒120的前側121之上(及周圍)。
微電子封裝組件100另包含與晶粒120的後側122相鄰且實體相接觸之電源平面140。電源平面140的厚度可由微電子封裝組件100的電源輸送需求來予以指定。因為所需的凸塊之某些凸塊可替代成被形成於先前未使用或浪費空間的位置(後側122)中之電源平面140內，所以電源平面140的存在能夠使前側121上的電源凸塊(或I/O凸塊或可能的假凸塊)之數量降低，以及使晶粒120的尺寸對應的降低。換言之，藉由使某些電源或其他的凸塊移動至後側122，在電源與I/O能力不妥協之下，本發明的實施例能夠使晶粒佔用空間(footprint)降低。再者，本發明的實施例允許電源電路能夠自此晶粒的底部或頂部(或兩者)進入此晶粒，而先前的所有電源必須自底部進入(即使是電源進入至封裝組件的頂部，這仍是正確的；亦即，頂側封裝組件電源將必須自此晶粒的底側而傳送至此晶粒，且進入此晶粒。本發明的實施例消除此需求，而卻能夠使兩側的功能部件成為可行，其中，之前的功能部件僅為單側的。
如同所提及者，本發明的實施例能夠使DDPU系統成為可行，其中，電源自與設置主動裝置之處的相對側進入晶粒。如同也被提及者，DDPU系統藉由設置更多個凸塊(甚至在較小的佔用空間中)，而享有諸如改善的SLI返回路徑最佳化，及增加的I/O訊號對接地比之優點。
電源平面140位於後側122處之TSV 123的曝露位置之頂部之上，其意謂在電源平面140與TSV 123之間(及自此至晶粒120的其他部分)，可實施連接，而不需後側122處的任何連接凸塊。在一個實施例中，電源平面140包含銅、與現有的配備相容的材料、及技術製程。在所繪示的實施例中，微電子封裝組件100另包含位於電源平面140之上的保護層150，以便保護此電源平面免於機械或環境的損壞(諸如，氧化)等等。(為了容許圖示更為清楚，保護層150未被顯示於圖1A中。)做為一例，保護層150可為由於為了降低腐蝕及類似所實施的化學處理而形成之氧化鋁等層。做為另一例，保護層150可為由聚合物材料、纖維強化塑膠、等等所製成的雙料射出成型(overmold)。
雖然未被顯示於圖1A及1B中，但是在某些實施例中，電源平面140可作為一個或多個被動組件(例如，電容器、電感器等)的附接點。在這些(或其他)未繪示實施例的某些實施例中，電源平面140可具有包圍晶粒120的某些或全部之凹部於其中。此凹入組態能夠降低微電子封裝組件100的整體厚度(時常也稱為Z高度)，使得除了其他優點以外，其將是與具有較小的外觀尺寸之裝置及產品相容。
圖1A繪示晶粒120的周邊124。圖1B僅顯示周邊124的兩個端點125，且僅顯示此周邊之經過基板110的延伸部分之外邊界126。此延伸部分(或佔用空間)界定晶粒區域127，其橫向寬度係顯示於圖1B中。可看出增層130含有在晶粒區域127外的複數個介層131，及在晶粒區域127內的複數個介層132。在所繪示的實施例中，介層131使電源平面140與基板110彼此電氣連接，而介層132使晶粒120與基板110彼此電氣連接。
因為在晶粒區域127外的介層131正穿透較厚的介電層，所以介層131需要較大的鑽孔尺寸；換言之，介層131為較長。在此方面，上述的此凹入組態之額外的優點為其將降低POP介層(介層131)的外觀比，於是使那些介層更容易且更便宜製造。因為介層132只必須到達晶粒120，而不必一直到達載體140，所以介層132為較短。因此，與介層131相較，介層132可使用較小的雷射。做為一例，這些介層可使用半加成製程(SAP)技術、雷射投影圖案化(LPP)技術、或任何其他適當的介層形成技術而被產生。
圖2A為依據本發明的實施例之微電子封裝組件200的平面圖，而圖2B為依據本發明的實施例之微電子封裝組件200的剖面圖。圖2B為沿著圖2A中的線B-B所獲得到的。如圖2A及2B中所繪示，微電子封裝組件200包含基板210，其具有被嵌入於其中的晶粒220及晶粒260。晶粒220具有前側221(亦即，設置電晶體(未顯示出)於其上之側)，及相對的後側222。晶粒220另具有TSV 223(其一直延伸至後側222，且被曝露在後側222)於其中。同樣地，晶粒260具有前側261(也設置電晶體(未顯示出)於其上之側)，及相對的後側262。晶粒260另具有TSV 263(其一直延伸至後側262，且被曝露在後側262)於其中。基板210包含複數個增層230(其中之一為介電層239)，複數個增層230與晶粒220和260的前側221和261相鄰，且被堆積於晶粒220和260的前側221和261之上(及周圍)。
微電子封裝組件200另包含與晶粒220的後側222及晶粒260的後側262相鄰且實體相接觸之導電結構240。在所繪示的實施例中，導電結構240包含使晶粒220的後側222和晶粒260的後側262彼此電氣連接之互連部241(例如，I/O晶粒內連接部)。導電結構240另包含可被使用於晶粒堆疊的晶粒連接墊242(包括晶粒連接墊242的角色之依據本發明的實施例之晶粒堆疊將於下面進一步予以討論)。
在一個實施例中，導電結構240包含銅。在相同或另一個實施例中，微電子封裝組件200另包含在導電結構240之上的保護層250，以便保護此導電結構免於機械或環境的損壞等等。(為了容許圖示更為清楚，保護層250並未被顯示於圖2A中。)做為一例，保護層250可為與圖1A及1B中所顯示的保護層150類似。
在一個實施例中，導電結構240可具有包圍晶粒220和260的某些或全部之凹部(未顯示出)於其中。在某些實施例中，對於各個晶粒而言，導電結構240可含有分離的凹部。
晶粒220和260(包括其間內的區域)的延伸部分(或佔用空間)界定晶粒區域227，其橫向寬度係顯示於圖2B中。可看出增層230含有在晶粒區域227外的複數個介層231，及在晶粒區域227內的複數個介層232。在所繪示的實施例中，複數個介層231使晶粒連接墊242與基板210彼此電氣運接，而複數個介層232使晶粒220和260與基板210彼此電氣連接。如所顯示，晶粒連接墊242可位於介層232的頂部上，及未使用於I/O連接部之TSV的頂部上。
多晶片封裝組件環境中的晶粒對晶粒互連部為非常昂貴，且難以為了跟上整體裝置尺寸而縮小。這些困難及費用藉由本發明的實施例而被降低或避免，本發明的實施例並非藉由降低線及空間寬度，而是藉由將某些互連部放置於先前未使用的位置：這些晶粒的後側中而增加互連部密度。本發明的實施例於是可被使用來使給定的晶粒尺寸可容納之互連部的數量粗略地加倍。
圖3為依據本發明的實施例之多晶片封裝組件300的剖面圖，多晶片封裝組件300包括具有晶粒220和晶粒260的微電子封裝組件200，以及額外的晶粒310。晶粒310被連接至晶粒連接墊242，於是藉由互連部311而被連接至介層231及基板210。在非繪示的實施例中，可使用打線接合或其他的連接機制，以取代圖3中所顯示的焊錫連接。因為此及其他之封裝組件堆疊在封裝組件上(POP)或封裝組件堆疊在封裝組件中(PIP)組態由於BBUL架構而具有大大降低的高度或厚度，所以其是令人滿意的。此外，本發明的實施例使I/O能夠遠比現有的POP架構(其中，或許兩或三列的凸塊(在其之上，座落額外的封裝組件)為此封裝組件可容納的全部，且在整體封裝組件的外部上之所有的連接部必須在被佈線至此晶粒之前，通過底部封裝組件)更密集。本發明的實施例允許某些或所有的此類連接部被形成於此晶粒後側上，而且也允許其為更密集。完整陣列的連接部是可行的，其中，甚至這些晶粒的後側為至少部分覆蓋連接部。再者，此導電結構本身可當作額外的佈線層。
圖4為繪示依據本發明的實施例之微電子封裝組件的製造方法400之流程圖。做為一例，方法400可導致與圖1A及1B中所顯示的微電子封裝組件100類似，或與圖2A、2B、及3中所顯示的微電子封裝組件200類似之微電子封裝組件的形成。
方法400的步驟410係要設置導電載體。做為一例，此導電載體可為與最先被顯示於圖5中的導電載體510類似。此導電載體可為，例如，附接於可剝去核心的銅箔等等，或者是其他暫時或犧牲的載體結構。此箔的厚度可由此微電子封裝組件的電源輸送需求來予以指定。若想要的話，可使用多層箔，其可能具有可(在後續的步驟中)容納晶粒的凹部。在位於此晶粒之上的箔厚度例如需要與他處的箔厚度不同之情況中，多層箔可提供所需的彈性。如其他範例，就多層被動裝置的產生而言，多層箔也可提供優點，且其可協助改善翹曲。
方法400的步驟420係要設置具有前側、相對的後側、及至少一個矽穿孔於其中的晶粒。做為一例，此晶粒可與圖1A、1B、2A、2B、及3中所顯示之晶粒120、晶粒220、及晶粒260的一個或多個類似，且也可與最先被顯示於圖5中的晶粒520類似。如所繪示，晶粒520具有前側521、後側522、及TSV 523。在某些實施例中，可設置多個晶粒，如由圖5中所顯示的第二(未予標號)晶粒所繪示。(應該瞭解的是，晶粒的數量不受限於只有一個或兩個；更確切而言，視想要的微電子封裝組件所需或適當的，可設置任何數量的晶粒)。
方法400的步驟430係要使此晶粒的此後側附接於此導電載體。這可例如藉由將導電黏著劑或焊錫等等塗佈於TSV墊上(或者，若TSV不具有焊墊，則塗佈於TSV本身的末端上)，且使用熱壓接合等等，以使此晶粒(或多個晶粒)黏著至此箔上來予以達成。做為一例，這些連接部可作為將電源輸送至此晶粒。圖5繪示在晶粒520已被附接於晶粒520的後側522之晶粒520。
方法400的步驟440係要形成複數個增層於此晶粒的此前側之上。此步驟的第一(或早先)部分可為疊置，或以其他方式，形成介電膜於整個板上，因而提供用於增層製程的平衡之水平面。在疊置之前，可實施銅膜的粗糙化，以便幫助此介電膜的黏著。較小介層可被形成在此晶粒區域中，此晶粒區域座落於此晶粒的焊墊(例如，銅墊)上。較大介層可被形成在此晶粒區域外，以使此導電載體(如下所述，在其被功能化之後)連接至此基板上，或連接至可被使用來使額外晶粒或封裝組件堆疊於此微電子封裝組件的頂部上之焊墊。
額外的層然後可被堆積於此介電膜之上。例如，可使用SAP技術，以將座落在這些晶粒墊上的這些介層，及此封裝組件之此基板部分的第一金屬層電鍍。也可使用LPP或其他技術。至此晶粒的I/O連接部及來自此晶粒的I/O連接部可被製成於第一金屬層上或後續的層上，其可使用形成此封裝組件的其餘部分之標準基板SAP(或其他)堆積法來予以形成。當此增層完成時，伴隨此銅箔的此封裝組件可與此暫時核心/載體的其餘部分分離。
做為一例，這些增層、這些較大介層、這些較小介層、及此介電膜可為分別類似於增層630、介層631、介層632、及介電膜639(其全部被顯示於圖6中)。增層630也可為類似於增層130(被顯示於圖1B中)及230(最先被顯示於圖2B中)。介層631也可為類似於介層131(見圖1B)及231(見圖2B及3)，而介層632也可為類似於介層132(見圖1B)及232(見圖2B及3)。介電膜639也可為類似於介電層139(見圖1A及1B)及239(見圖2A、2B、及3)。
方法400的步驟450係要將此導電載體圖案化，以便形成此微電子封裝組件的導電組件。在一個實施例中，此導電組件為電源平面。圖1A及1B顯示起因於此方法400的實施例之性能的微電子封裝組件之範例。
在特定實施例中，步驟450或另一個步驟可包含使此電源平面及此基板電氣連接至電源(例如，電源軌)。做為一例，步驟450可包含將乾膜等等疊置於此銅箔的頂部上，然後實施減去圖案化，以便形成此電源平面。連接部可被製成於此上，以使來自此晶粒外的電源載送介層之電源經由TSV而連接至此晶粒。
在另一個實施例(其中，此微電子封裝組件包含多個晶粒)中，此導電組件為這些晶粒的兩個(或更多個)之間的電氣連接部。圖2A、2B、及3顯示起因於此方法400的實施例之性能的微電子封裝組件之範例。做為一例，步驟450可包含將乾膜等等疊置於此銅箔的頂部上，然後實施減去圖案化，以便形成經過TSV的額外I/O連接部。可被使用來使晶粒或封裝組件堆疊於頂部上的焊墊也皆可被產生於在此晶粒區域外之介層的頂部上，及未使用於I/O連接部之TSV的頂部上。這些焊墊可為類似於最先被顯示於圖2A及2B中的晶粒連接墊242。
雖然本發明已參考特定實施例來予以說明，但是熟習此項技術者將瞭解的是，在不偏離本發明的精神或範圍之下，可實施各種改變。因此，本發明的實施例之揭示係意謂本發明的範圍之例示，而非意謂限制。其係意謂本發明的範圍應該僅受限於後附之申請專利範圍所需的程度。例如，對於一般熟習此項技術者而言，將立即顯然可知在此所揭示之微電子封裝組件及相關的結構與方法可以種種實施例來予以實施，且這些實施例的某些之上述討論不必然代表可行實施例的完整說明。
此外，好處、其他優點、及問題的解決方式已關於特定實施例來予以說明。然而，這些好處、優點、問題的解決方式、以及可致使任何好處、優點、或可出現或變成更明顯的解決方式之任何一個或多個要素並非被解釋為申請專利範圍的任一或全部之緊要、需要、或基本的特性或要素。
此外，若在此所揭示的實施例及/或限制：(1)未明確地被主張於申請專利範圍中；以及(2)依據均等論而為或潛在地為申請專利範圍中之明確的要素及/或限制之等效，則依據貢獻原則，這些實施例及限制並非貢獻給社會大眾。
100．．．微電子封裝組件
110．．．基板
120．．．晶粒
121．．．前側
122．．．後側
123．．．矽穿孔(TSV)
124．．．周邊
125．．．端點
126．．．外邊界
127．．．晶粒區域
130．．．增層
131．．．介層
132．．．介層
139．．．介電層
140．．．電源平面
150．．．保護層
200．．．微電子封裝組件
210．．．基板
220．．．晶粒
221．．．前側
222．．．後側
223．．．矽穿孔
227．．．晶粒區域
230．．．增層
231．．．介層
232．．．介層
239．．．介電層
240．．．導電結構
241．．．互連部
242．．．晶粒連接墊
250．．．保護層
260．．．晶粒
261．．．前側
262．．．後側
263．．．矽穿孔
300．．．多晶片封裝組件
310．．．晶粒
311．．．互連部
510．．．導電載體
520．．．晶粒
521．．．前側
522．．．後側
523．．．矽穿孔
630．．．增層
631．．．介層
632．．．介層
639．．．介電膜
所揭示的實施例將自配合圖式中的附圖之下面的詳細說明之研讀中而更加瞭解，其中：
圖1A及1B分別是依據本發明的實施例之微電子封裝組件的平面圖及剖面圖；
圖2A及2B分別是依據本發明的另一個實施例之微電子封裝組件的平面圖及剖面圖；
圖3係依據本發明的實施例之多晶片封裝組件的剖面圖；
圖4係繪示依據本發明的實施例之微電子封裝組件的製造方法之流程圖；
圖5係依據本發明的實施例之微電子封裝組件在其製造程序的特定點處之部分的剖面圖；以及
圖6係依據本發明的實施例之圖5的此微電子封裝組件在其製造程序的後續點處之部分的剖面圖。
100．．．微電子封裝組件
110．．．基板
120．．．晶粒
124．．．周邊
139．．．介電層
140．．．電源平面

Claims (21)

  1. 一種微電子封裝組件，包含：基板；晶粒，被嵌入於該基板內，該晶粒具有前側及相對的後側，且另具有至少一個矽穿孔於其中；複數個增層，與該晶粒的該前側相鄰，且被堆積於該晶粒的該前側之上；以及電源平面，與該晶粒的該後側相鄰且實體相接觸。
  2. 如申請專利範圍第1項之微電子封裝組件，其中：該電源平面包含銅。
  3. 如申請專利範圍第1項之微電子封裝組件，另包含：被動組件，係附接於該電源平面。
  4. 如申請專利範圍第1項之微電子封裝組件，另包含：保護層，在該電源平面之上。
  5. 如申請專利範圍第1項之微電子封裝組件，其中：該電源平面具有凹部於其中；以及該晶粒係至少部分位於該凹部內。
  6. 如申請專利範圍第1項之微電子封裝組件，其中：該晶粒具有晶粒周邊；該晶粒周邊之經過該等增層的延伸部分界定晶粒區域；以及該等增層含有在該晶粒區域外的第一複數個介層，及在該晶粒區域內的第二複數個介層。
  7. 如申請專利範圍第6項之微電子封裝組件，其中：該第一複數個介層使該電源平面與該基板彼此電氣連接；以及該第二複數個介層使該晶粒與該基板彼此電氣連接。
  8. 一種微電子封裝組件，包含：基板；第一晶粒和第二晶粒，兩者皆被嵌入於該基板中，兩者皆具有前側及相對的後側，且兩者皆具有至少一個矽穿孔於其中；複數個增層，與該第一晶粒和該第二晶粒的該等前側相鄰，且被堆積於該第一晶粒和該第二晶粒的該等前側之上；以及導電結構，與該第一晶粒和該第二晶粒的該等後側相鄰且實體相接觸。
  9. 如申請專利範圍第8項之微電子封裝組件，其中：該導電結構包含：互連部，使該第一晶粒和該第二晶粒的該等後側彼此電連接；以及晶粒連接墊。
  10. 如申請專利範圍第9項之微電子封裝組件，其中：該第一晶粒具有第一晶粒周邊，而該第二晶粒具有第二晶粒周邊；該第一晶粒周邊和該第二晶粒周邊之經過該等增層的延伸部分界定晶粒區域；以及該等增層含有在該晶粒區域外的第一複數個介層，及在該晶粒區域內的第二複數個介層。
  11. 如申請專利範圍第10項之微電子封裝組件，其中：該第一複數個介層使該晶粒連接墊與該基板彼此電氣連接；以及該第二複數個介層使該第一晶粒和該第二晶粒與該基板彼此電氣連接。
  12. 如申請專利範圍第8項之微電子封裝組件，其中：該導電結構包含銅。
  13. 如申請專利範圍第8項之微電子封裝組件，另包含：保護層，在該導電結構之上。
  14. 如申請專利範圍第8項之微電子封裝組件，其中：該導電結構具有凹部於其中；以及該第一晶粒和該第二晶粒係至少部分位於該凹部內。
  15. 一種微電子封裝組件之製造方法，該方法包含：設置導電載體；設置具有前側、相對的後側、及至少一個矽穿孔於其中的晶粒；使該晶粒的該後側附接於該導電載體；形成複數個增層於該晶粒的該前側之上，該等增層與該導電載體形成該微電子封裝組件的基板之部分；以及將該導電載體圖案化，以便形成該微電子封裝組件的導電組件。
  16. 如申請專利範圍第15項之方法，其中：該導電組件為電源平面。
  17. 如申請專利範圍第16項之方法，另包含：使該電源平面電氣連接至電源；以及使該基板電氣連接至該電源。
  18. 如申請專利範圍第15項之方法，其中：該微電子封裝組件另包含第二晶粒；以及該導電組件為介於該晶粒與該第二晶粒之間的電氣連接。
  19. 如申請專利範圍第15項之方法，其中：該導電載體包含銅。
  20. 如申請專利範圍第15項之方法，另包含：形成與該導電組件相鄰的複數個連接墊。
  21. 如申請專利範圍第15項之方法，其中：提供該導電載體包含提供附接於犧牲核心的銅箔；該方法另包含在完成該等增層之後，使該銅箔與該犧牲核心分離；以及將該導電載體圖案化，以便形成該微電子封裝組件的該導電組件包含將該銅箔圖案化。
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