CN112909083B - High-voltage JFET device structure for improving withstand voltage reliability and manufacturing method thereof - Google Patents
High-voltage JFET device structure for improving withstand voltage reliability and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 77
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000137 annealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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Abstract
The invention provides a high-voltage JFET device structure for improving withstand voltage reliability and a manufacturing method thereof, DNW positioned in an active region; a second N+ region located on one side of the DNW inner edge; the first field oxide region is positioned on the surface of the DNW and takes the second N+ region as the center of a circle, and the P well is positioned on the surface in the DNW and takes the second N+ region as the center of a circle and surrounds the first field oxide region; a first P+ region and a first N+ region at the surface of the P well; the first polysilicon gate is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; the upper surface of one side of the first field oxide region, which is close to the second N+ region, is also provided with a second polysilicon gate; the first polysilicon gate and the second polysilicon gate are annular structures surrounding the second N+ region; the first P+ region and the first N+ region are connected to the first metal plate through the through holes above the first P+ region and the first N+ region respectively; the first metal plate extends to a position above the upper surface of the first field oxide region; the first metal plate is of an annular structure taking the second N+ region as a circle center; the annular structure forms a plurality of segmented hollow grooves in an annular direction thereof.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-voltage JFET device structure for improving withstand voltage reliability and a manufacturing method thereof.
Background
In order to improve breakdown voltage BV in an off state, two field plates, namely gate polysilicon and source metal, are needed on field oxygen of a drift region close to a channel side, and the metal field plate also needs to extend out of the gate polysilicon to form a step-type double-field plate. The metal field plate needs to be connected with a grid electrode (Poly) and a channel P Well (PW) of the JFET device to be connected with zero potential. The high voltage JFET device generally adopts a circular structure with a high voltage drain in the middle and a JFET channel PW outside, so that when the source metal field plate is connected to the channel PW, the metal covers the entire gate polysilicon Poly, forming a ring. The gate Poly is generally etched by plasma etching, and the number of residual charges after plasma etching increases as the area of the etched Poly increases. These residual charges are usually removed by a thermal annealing process after metal etching, but if there is a metal cover above Poly, the effect of removing will be affected, especially for such a high voltage JFET device, the gate Poly area is larger, and the metal layer is covered above the gate Poly, which will cause insufficient removal of residual charges during thermal annealing, resulting in increased device leakage and reduced withstand voltage.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a high-voltage JFET device structure with improved withstand voltage reliability and a method for manufacturing the same, which are used for solving the problem that residual charges cannot be sufficiently eliminated after thermal annealing of gate polysilicon due to shielding of a metal plate above the polysilicon gate in the JFET device in the prior art.
To achieve the above and other related objects, the present invention provides a high voltage JFET device structure for improving withstand voltage reliability, comprising at least:
a P-type substrate; an active region on the P-type substrate; DNW located within the active region;
a second N+ region located on one side of the DNW inner edge; the first field oxygen area is positioned at the DNW surface and the upper surface is higher than the DNW upper surface, and takes the second N+ area as a circle center to form an annular structure surrounding the second N+ area; a P-well which is positioned on the surface in the DNW, takes the second N+ region as a center and surrounds the first field oxygen region; a space is arranged between the first field oxide region and the P well;
a first p+ region and a first n+ region located at a surface within the P-well; wherein the first n+ region is closer to the first field oxide region than the first p+ region; the first polysilicon gate is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; a second polysilicon gate is further arranged on the upper surface of one side, close to the second N+ region, of the first field oxide region; the first polysilicon gate and the second polysilicon gate are of annular structures surrounding the second N+ region;
the first P+ region and the first N+ region are respectively connected to the first metal plate through the through holes above the first P+ region and the first N+ region; the first metal plate extends to the position, in the plane of the first metal plate, that the first polysilicon gate is positioned above one end of the upper surface of the first field oxide region; the first metal plate is of an annular structure taking the second N+ region as a circle center; and the annular structure forms a plurality of segmented hollow grooves in the annular direction thereof;
the second N+ region and the second polysilicon gate are connected to the second metal plate through holes respectively located above the second N+ region and the second polysilicon gate.
Preferably, the high voltage JFET device structure further comprises: a second field oxide region located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW; the second field oxide region is located on one side of the P well away from the first polysilicon gate.
Preferably, the first metal plate is a gate of the high voltage JFET device structure.
Preferably, the second metal plate is a drain of the high voltage JFET device structure.
Preferably, the high voltage JFET device structure further comprises a third n+ region located at an inner surface of the DNW, and the third n+ region is located on a side of the second field oxide region remote from the first p+ region.
Preferably, the third n+ region is connected to a third metal plate by a via located thereon, the third metal plate being a source of the high voltage JFET device structure.
Preferably, the high-voltage JFET device structure further comprises a third field oxide region which is located at the junction of the DNW and the P-type substrate and the upper surface of which is higher than the upper surface of the DNW, and the third field oxide region is located on one side of the third N+ region away from the second field oxide region.
Preferably, the high voltage JFET device structure further comprises a second p+ region located at an inner surface of the P-type substrate, and the second p+ region is connected to the fourth metal plate by a via located thereon.
The invention also provides a manufacturing method of the high-voltage JFET device structure for improving the pressure resistance reliability, which at least comprises the following steps:
step one, providing a P-type substrate, and forming DNW on the P-type substrate;
step two, forming a ring-shaped first field oxygen region taking the second N+ region as a circle center between the first N+ region and the second N+ region; forming an annular second field oxide region taking the second N+ region as a center between the third N+ region and the first P+ region;
step three, forming an annular P well in the DNW;
forming a first polysilicon gate which is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; forming a second polysilicon gate on the upper surface of one side of the first field oxide region, which is close to the second N+ region;
forming a second N+ region on the surface in the P well; the annular P well is of an annular structure taking the second N+ region as a circle center; forming a first N+ region and a first P+ region at a surface within the P well; and the first n+ region is closer to the second n+ region than the first p+ region; forming a third n+ region at a surface within the DNW on a side of the first p+ region remote from the first n+ region; forming a second p+ region at a surface inside the P-type substrate outside the DNW, and the second p+ region being located on a side of the third n+ region away from the first p+ region;
step six, covering a dielectric layer; forming through holes on the upper surfaces of the first P+ region, the first N+ region, the second N+ region, the third N+ region and the second polysilicon gate;
forming a metal layer on the dielectric layer, etching the metal layer, and forming a first metal plate in the through hole above the first P+ region and the first N+ region, wherein the first metal plate extends to the position that the first polysilicon gate is positioned above one end of the upper surface of the first field oxide region, and the first metal plate is of an annular structure taking the second N+ region as the center of a circle; the annular structure forms a plurality of segmented hollow grooves in the annular direction; and forming a second metal plate in the through hole above the second N+ region and the second polysilicon gate.
As described above, the high-voltage JFET device structure for improving withstand voltage reliability and the method for manufacturing the same of the present invention have the following advantageous effects: in order to expose more polysilicon areas as much as possible, particularly to expose a gate oxide area below a polysilicon gate, residual charges are released, a metal field plate covered on the polysilicon area is designed into a slotting mode, the whole metal is divided into a plurality of segments by optimizing a metal field plate layout close to a JFET channel side, and the problem of insufficient residual charges elimination after a thermal process caused by metal coverage is solved on the premise of keeping the field plate effect.
Drawings
Fig. 1 is a schematic view showing a vertical cross section of a high-voltage JFET device structure of the present invention with improved withstand voltage reliability;
fig. 2 is a schematic layout diagram of a high-voltage JFET device structure for improving voltage endurance reliability according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a high-voltage JFET device structure for improving withstand voltage reliability, which at least comprises the following components:
a P-type substrate; an active region on the P-type substrate; DNW located within the active region; a second N+ region located on one side of the DNW inner edge; the first field oxygen area is positioned at the DNW surface and the upper surface is higher than the DNW upper surface, and takes the second N+ area as a circle center to form an annular structure surrounding the second N+ area; a P-well which is positioned on the surface in the DNW, takes the second N+ region as a center and surrounds the first field oxygen region; a space is arranged between the first field oxide region and the P well; a first p+ region and a first n+ region located at a surface within the P-well; wherein the first n+ region is closer to the first field oxide region than the first p+ region; the first polysilicon gate is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; a second polysilicon gate is further arranged on the upper surface of one side, close to the second N+ region, of the first field oxide region; the first polysilicon gate and the second polysilicon gate are of annular structures surrounding the second N+ region;
the first P+ region and the first N+ region are respectively connected to the first metal plate through the through holes above the first P+ region and the first N+ region; the first metal plate extends to the position, in the plane of the first metal plate, that the first polysilicon gate is positioned above one end of the upper surface of the first field oxide region; the first metal plate is of an annular structure taking the second N+ region as a circle center; and the annular structure forms a plurality of segmented hollow grooves in the annular direction thereof; the second N+ region and the second polysilicon gate are connected to the second metal plate through holes respectively located above the second N+ region and the second polysilicon gate.
As shown in fig. 1, fig. 1 is a schematic view showing a vertical section of a high-voltage JFET device structure of the present invention for improving withstand voltage reliability, the high-voltage JFET device structure including in this embodiment: a P-type substrate (PSUB); an active area AA on the P-type substrate; DNW (N-type deep well) located within the active region;
the high voltage JFET device structure further comprises: a second N+ region 01 located at one side of the inner edge of the DNW (N-type deep well); a first field oxide region 02 located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW, wherein the first field oxide region 02 takes the second n+ region 01 as a center to form a ring structure surrounding the second n+ region 01; as shown in fig. 2, fig. 2 is a schematic layout diagram of a high-voltage JFET device structure for improving voltage endurance reliability according to the present invention. Drain in FIG. 2 is the Drain formed over the second N+ region 01.
As shown in fig. 1, the high voltage JFET device structure further includes: a P-well (PW) located at the surface inside the DNW (N-type deep well) and surrounding the first field oxide region 02 with the second N+ region 01 as a center; the first field oxide region and the P-well in FIG. 1 have a space therebetween;
the high voltage JFET device structure further includes a first p+ region 03 and a first n+ region 04 at a surface within the P-well (PW); wherein the first n+ region 04 is closer to the first field oxide region 02 than the first p+ region 03;
the high-voltage JFET device structure further comprises a first polysilicon gate 05 which is positioned at the edge of the upper surface of the first N+ region 04 and extends to the upper surface of the first field oxide region 02; a second polysilicon gate 06 is further arranged on the upper surface of the first field oxide region 02, which is close to one side of the second N+ region 01; the first polysilicon gate 05 and the second polysilicon gate 06 are both annular structures surrounding the second n+ region 01; as shown in fig. 2, the first polysilicon gate 05 and the second polysilicon gate 06 are both ring structures surrounding the second n+ region (Drain).
The first p+ region 03 and the first n+ region 04 in fig. 1 are respectively connected to the first metal plate 08 through the respective upper via holes 07; the first metal plate 08 extends to the position that the first polysilicon gate 05 is positioned above one end of the upper surface of the first field oxide region 02 in the plane of the first metal plate; namely, the plane of the first metal plate is a horizontal plane above the substrate as shown in fig. 1, as shown in fig. 2, and the first metal plate 08 is a ring-shaped structure taking the second n+ region 01 (Drain) as a center; and the ring-shaped structure forms a plurality of segmented hollow grooves 09 in the ring-shaped direction thereof, and the part between the two rings formed by the black thick lines in fig. 2 forms the first metal plate 08, and the hollow grooves 09 of four segments are positioned in the first metal plate 08.
As shown in fig. 1, the second n+ region 01 and the second polysilicon gate 06 are connected to the second metal plate 10 through respective through holes 07 located above.
As shown in fig. 1, the high-voltage JFET device structure in this embodiment further includes: a second field oxide region 11 located at the surface of the DNW and having an upper surface higher than the upper surface of the DNW; the second field oxide region 11 is located on a side of the P-well (PW) away from the first polysilicon gate 05.
The first metal plate 08 in this embodiment is the gate (gate) of the high-voltage JFET device structure; the second metal plate 10 is the Drain (Drain) of the high voltage JFET device structure.
As shown in fig. 1, the high-voltage JFET device structure in this embodiment further includes a third n+ region 12 located at the inner surface of the DNW, and the third n+ region 12 is located on a side of the second field oxide region 11 away from the first p+ region 03.
Further, in this embodiment, the third n+ region 12 is connected to the third metal plate 13 through a via located thereon, and the third metal plate 13 is the Source (Source) of the high voltage JFET device structure.
As shown in fig. 1, the high-voltage JFET device structure in this embodiment further includes a third field oxide region 14 located at the boundary between the DNW and the P-type substrate and having an upper surface higher than the upper surface of the DNW, and the third field oxide region 14 is located on a side of the third n+ region 12 away from the second field oxide region 11.
The present invention further provides that the high voltage JFET device structure in this embodiment further comprises a second p+ region 15 located at the inner surface of the P-type substrate, and that the second p+ region 15 is connected to the fourth metal plate 16 by a via located thereon.
The invention also includes: a dielectric layer 17 located below the first and second metal plates.
The invention also provides a manufacturing method of the high-voltage JFET device structure for improving the voltage withstand reliability, referring to fig. 1, the method at least comprises the following steps:
step one, providing a P-type substrate (PSUB), and forming DNW (N-type deep well) on the P-type substrate;
step two, forming a ring-shaped first field oxide region 02 taking the second N+ region 01 as a circle center between the first N+ region 04 and the second N+ region 01; a second field oxide region 11 which takes the second N+ region 01 as a center is formed between the third N+ region 12 and the first P+ region 03;
step three, forming a ring-shaped P Well (PW) in the DNW (N-type deep well);
forming a first polysilicon gate 05 positioned at the edge of the upper surface of the first N+ region 04 and extending to the upper surface of the first field oxide region 02; forming a second polysilicon gate 06 on the upper surface of the first field oxide region 02 near the side of the second n+ region 01;
step five, forming a second N+ region 01 at the surface in the P Well (PW); the annular P Well (PW) is an annular structure taking the second N+ region 01 as a circle center; forming a first n+ region 04 and a first p+ region 03 at a surface within the P-well (PW); and the first n+ region 04 is closer to the second n+ region 01 than the first p+ region 03; forming a third n+ region 12 at a surface within the DNW on a side of the first p+ region 03 remote from the first n+ region 04; forming a second p+ region 15 at a surface inside the P-type substrate outside the DNW, and the second p+ region 15 being located on a side of the third n+ region 12 remote from the first p+ region 03;
step six, covering the dielectric layer 17; forming through holes 07 on the upper surfaces of the first P+ region 03, the first N+ region 04, the second N+ region 01, the third N+ region 12 and the second polysilicon gate 06;
step seven, forming a metal layer on the dielectric layer 17, etching the metal layer, and forming a first metal plate 08 in the through hole above the first p+ region 03 and the first n+ region 01, wherein the first metal plate extends to the position that the first polysilicon gate 05 is located above one end of the upper surface of the first field oxide region 02, as shown in fig. 2, and the first metal plate 08 is in an annular structure taking the second n+ region 01 as the center of a circle; the annular structure forms a plurality of segmented hollow grooves 09 in the annular direction thereof; a second metal plate 10 is formed in the second n+ region 01 and the via hole above the second polysilicon gate 06.
In summary, in order to expose more polysilicon regions as much as possible, especially to expose the gate oxide region below the polysilicon gate, the invention designs the metal field plate covered on the polysilicon gate in a slotted mode, and divides the whole metal into several segments by optimizing the metal field plate layout close to the channel side of the JFET, thereby eliminating the problem of insufficient elimination of residual charge after the thermal process caused by metal coverage on the premise of maintaining the field plate effect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A high voltage JFET device structure for improving withstand voltage reliability, comprising at least:
a P-type substrate; an active region on the P-type substrate; an N-type deep well located in the active region;
the second N+ region is positioned at one side of the inner edge of the N-type deep well; the first field oxygen region is positioned at the surface of the N-type deep well, the upper surface of the first field oxygen region is higher than the upper surface of the N-type deep well, and the first field oxygen region takes the second N+ region as a circle center to form an annular structure surrounding the second N+ region; the P well is positioned on the surface in the N-type deep well, takes the second N+ region as a circle center and surrounds the first field oxygen region; a space is arranged between the first field oxide region and the P well;
a first p+ region and a first n+ region located at a surface within the P-well; wherein the first n+ region is closer to the first field oxide region than the first p+ region; the first polysilicon gate is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; a second polysilicon gate is further arranged on the upper surface of one side, close to the second N+ region, of the first field oxide region; the first polysilicon gate and the second polysilicon gate are of annular structures surrounding the second N+ region;
the first P+ region and the first N+ region are respectively connected to the first metal plate through the through holes above the first P+ region and the first N+ region; the first metal plate extends to the position, in the plane of the first metal plate, that the first polysilicon gate is positioned above one end of the upper surface of the first field oxide region; the first metal plate is of an annular structure taking the second N+ region as a circle center; and the annular structure forms a plurality of segmented hollow grooves in the annular direction thereof;
the second N+ region and the second polysilicon gate are connected to the second metal plate through holes respectively located above the second N+ region and the second polysilicon gate.
2. The high voltage JFET device structure of claim 1, wherein the voltage withstand reliability is improved by: the high voltage JFET device structure further comprises: the second field oxygen region is positioned at the surface of the N-type deep well and the upper surface of the second field oxygen region is higher than the upper surface of the N-type deep well; the second field oxide region is located on one side of the P well away from the first polysilicon gate.
3. The high voltage JFET device structure of claim 1, wherein the voltage withstand reliability is improved by: the first metal plate is a grid electrode of the high-voltage JFET device structure.
4. The high voltage JFET device structure of claim 1, wherein the voltage withstand reliability is improved by: the second metal plate is a drain electrode of the high-voltage JFET device structure.
5. The high voltage JFET device structure of claim 2, wherein the voltage withstand reliability is improved by: the high-voltage JFET device structure further comprises a third N+ region located at the inner surface of the N-type deep well, and the third N+ region is located on one side of the second field oxide region away from the first P+ region.
6. The high voltage JFET device structure of claim 5, wherein the voltage withstand reliability is improved by: the third N+ region is connected to a third metal plate through a through hole located on the third N+ region, and the third metal plate is a source electrode of the high-voltage JFET device structure.
7. The high voltage JFET device structure of claim 5, wherein the voltage withstand reliability is improved by: the high-voltage JFET device structure further comprises a third field oxide region which is positioned at the junction of the N-type deep well and the P-type substrate and the upper surface of which is higher than the upper surface of the N-type deep well, and the third field oxide region is positioned at one side of the third N+ region away from the second field oxide region.
8. The high voltage JFET device structure of claim 1, wherein the voltage withstand reliability is improved by: the high voltage JFET device structure further includes a second p+ region located at an inner surface of the P-type substrate, and the second p+ region is connected to the fourth metal plate by a via located thereon.
9. The method of manufacturing a high voltage JFET device structure of any one of claims 1 to 8, wherein the voltage endurance reliability is improved, characterized by: at least comprises:
step one, providing a P-type substrate, and forming an N-type deep well on the P-type substrate;
step two, forming a ring-shaped first field oxygen region taking the second N+ region as a circle center between the first N+ region and the second N+ region; forming an annular second field oxide region taking the second N+ region as a center between the third N+ region and the first P+ region;
forming an annular P well in the N-type deep well;
forming a first polysilicon gate which is positioned at the edge of the upper surface of the first N+ region and extends to the upper surface of the first field oxide region; forming a second polysilicon gate on the upper surface of one side of the first field oxide region, which is close to the second N+ region;
forming a second N+ region on the surface in the P well; the annular P well is of an annular structure taking the second N+ region as a circle center; forming a first N+ region and a first P+ region at a surface within the P well; and the first n+ region is closer to the second n+ region than the first p+ region; forming a third N+ region at a surface in the N-type deep well on a side of the first P+ region away from the first N+ region; forming a second P+ region at a surface inside the P-type substrate outside the N-type deep well, wherein the second P+ region is positioned on one side of the third N+ region away from the first P+ region;
step six, covering a dielectric layer; forming through holes on the upper surfaces of the first P+ region, the first N+ region, the second N+ region, the third N+ region and the second polysilicon gate;
forming a metal layer on the dielectric layer, etching the metal layer, and forming a first metal plate in the through hole above the first P+ region and the first N+ region, wherein the first metal plate extends to the position that the first polysilicon gate is positioned above one end of the upper surface of the first field oxide region, and the first metal plate is of an annular structure taking the second N+ region as the center of a circle; the annular structure forms a plurality of segmented hollow grooves in the annular direction; and forming a second metal plate in the through hole above the second N+ region and the second polysilicon gate.
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