CN111725300A - Terminal structure of MOSFET device and preparation method and application thereof - Google Patents
Terminal structure of MOSFET device and preparation method and application thereof Download PDFInfo
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- 238000000034 method Methods 0.000 claims description 13
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- 230000005669 field effect Effects 0.000 description 4
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- 150000004706 metal oxides Chemical class 0.000 description 3
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- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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Abstract
The invention relates to a terminal structure of a MOSFET device, a preparation method and application thereof, wherein the terminal structure comprises more than one group of silicon carbide groove rings which are arranged on the periphery of a chip of the MOSFET device and are distributed in sequence from inside to outside; the silicon carbide groove ring is a closed ring; the silicon carbide groove ring at the innermost side is connected with the low potential of the chip; the silicon carbide groove ring on the outermost side is a stop ring, and the potential of the stop ring is connected with a scribing channel of the chip. According to the terminal structure of the MOSFET device, the silicon carbide groove is connected with the low potential of the chip through the inner side, so that the formation of an anti-criminal channel is effectively inhibited, and electric leakage can be inhibited; the silicon carbide groove is connected with the high potential of the scribing channel at the outer side, so that the isolation effect can be enhanced, and a leakage channel can be prevented from being formed between the inner side and the outer side due to the closed annular design, so that the problems of voltage resistance and leakage of the MOSFET device are solved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a terminal structure of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, and a preparation method and application thereof.
Background
A Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is a Field Effect Transistor that can be widely used in analog circuits and digital circuits. Terminal structure of MOSFETSilicon carbide trenches are commonly used. As shown in fig. 1, a conventional process manufacturing method of a silicon carbide Trench (SiC Trench MOS) includes the steps of: forming a lightly doped N-type epitaxial layer 8 on a semiconductor substrate 9, growing a silicon dioxide layer on the epitaxial layer 8, and defining a P-type body region by using a first P-well mask; then growing a silicon dioxide layer with a certain thickness on the surface of the silicon carbide wafer, defining a Trench region by using a second Trench (SiC Trench) photomask, forming a series of trenches on the N-epitaxial layer, growing a gate oxide layer 7 in the trenches through thermal oxidation, depositing polycrystalline silicon on the gate oxide layer 7, and then back-etching the polycrystalline silicon to form a gate electrode 6; then, injecting first P-type impurity ions into the previously defined P-type body region, and diffusing to form a P-type body region 5; using the third block N+Mask, defining N in P well region+A source contact region 4 for implanting and diffusing second N-type impurity ions; depositing an insulating medium layer 3 on the surface of the chip, defining a Contact hole pattern by adopting a fourth Contact hole (Contact) photomask, photoetching a source hole 2, filling barrier layer metal in the hole, and sputtering top layer metal on the surface; and finally, defining a Gate Metal region 1(Gate Metal) and a Source Metal region 1' (Source Metal) by using a fifth Metal layer (Metal) photomask, forming a Gate Metal electrode and a Source Metal electrode by adopting dry etching, and depositing a Metal layer on the surface of the N-type highly doped substrate to form a drain Metal electrode 10. As can be seen from the above manufacturing processes, the existing process mainly includes 5 layers of photolithography masks, including a trench mask (Poly layer), a P-well mask (P-well layer), and N+Mask layer (N)+layer), contact mask layer (contact layer) and Metal mask layer (Metal layer), that is, five photolithography processes are required in the device manufacturing process. The photoetching is to transfer the pattern on the mask plate to the wafer, and each photoetching needs at least eight process steps including gas phase film forming, rotary glue coating, baking, exposure, baking after exposure, development, film hardening and development inspection, and the steps occupy a very large machine and time proportion in wafer manufacturing.
Therefore, how to reduce the lateral leakage of the terminal structure of the MOSFET device and to ensure the breakdown voltage thereof while simplifying the manufacturing process becomes one of the issues that the development of the semiconductor industry is always concerned about and pursued.
Disclosure of Invention
The invention provides a terminal structure of a MOSFET (metal oxide semiconductor field effect transistor) device, which solves the problems of voltage resistance and electric leakage of the MOSFET device by arranging a plurality of layers of closed silicon carbide groove rings on the outer side of a chip.
The invention also provides a preparation method of the terminal structure of the MOSFET device, which simplifies the process, reduces the cost and can solve the problems of low withstand voltage and electric leakage of the traditional three-layer photomask.
The invention also provides an application of the terminal structure of the MOSFET device.
The technical scheme provided by the invention is as follows:
in a first aspect, the invention provides a terminal structure of a MOSFET device, which includes more than one group of silicon carbide trench rings arranged on the periphery of a chip of the MOSFET device and distributed in sequence from inside to outside;
the silicon carbide groove ring is a closed ring;
the silicon carbide groove ring at the innermost side is connected with the low potential of the chip;
the silicon carbide groove ring on the outermost side is a stop ring, and the potential of the stop ring is connected with a scribing channel of the chip.
According to the terminal structure of the MOSFET device, the silicon carbide groove is connected with the low potential of the chip through the inner side, so that the formation of an anti-criminal channel is effectively inhibited, and electric leakage can be inhibited; the silicon carbide grooves are connected with the high potential of the scribing channel on the outer side, the isolation effect can be enhanced, a leakage channel can be prevented from being formed between the inner side and the outer side due to the closed annular design, isolation terminals are formed through a plurality of silicon carbide groove rings, and the traditional P-type injection junction terminals are replaced, so that the problems of voltage resistance and leakage of the MOSFET device are solved.
The terminal structure of the MOSFET device of the present invention may further have the following additional features:
in the specific implementation mode of the invention, the terminal structure of the MOSFET device is obtained by sequentially distributing silicon carbide trench rings on the periphery of a MOSFET device chip from inside to outside, and the innermost silicon carbide trench ring is connected with the low potential of the chip, so that the formation of an inversion channel can be effectively inhibited, and the leakage can be inhibited.
In a specific embodiment of the present invention, the silicon carbide trench rings at the innermost side are arranged in more than one group; the silicon carbide groove rings on the outermost side are arranged into more than one group; the silicon carbide groove rings between the innermost silicon carbide groove ring and the outermost silicon carbide groove ring are arranged into more than one group, and the functions of isolating and extending an electric field can be achieved.
In the embodiment of the invention, the silicon carbide trench ring at the innermost side is arranged at the side close to the gate metal and is connected with the low potential of the chip, so that the formation of the inversion can be effectively inhibited, and the leakage can be inhibited.
In order to ensure that the peripheral high potential is limited near the scribing street and enhance the isolation effect, in the specific embodiment of the invention, the silicon carbide groove ring at the outermost side is arranged at one side close to the scribing street.
In an embodiment of the present invention, the silicon carbide trench ring is a gate silicon carbide trench ring, and the gate silicon carbide trench ring surrounds at least one chip of the gate silicon carbide trench ring, so that the isolation effect can be enhanced.
In a second aspect, the present invention provides a method for manufacturing a terminal structure of a MOSFET device, including the following steps:
connecting a low potential of a MOSFET device chip with the innermost silicon carbide groove ring, then sequentially distributing the silicon carbide groove rings from inside to outside, wherein the outermost silicon carbide groove ring is connected with a scribing channel of the chip;
wherein, the silicon carbide groove ring is a closed ring.
In a specific embodiment of the method of the present invention, the silicon carbide trench rings connected to the low potential of the chip are one or more groups, and the silicon carbide trench rings connected to the scribe line of the chip are one or more groups.
In one embodiment of the method of the present invention, the silicon carbide trench is a gate silicon carbide trench ring, and the gate silicon carbide trench ring surrounds the chip at least one turn.
The preparation method of the terminal structure of the MOSFET device simplifies the process, reduces the cost and can solve the problems of low withstand voltage and electric leakage of the traditional three-layer photomask.
In a third aspect, the invention provides the application of the terminal structure in a MOSFET device.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic structural diagram of a silicon carbide trench of a conventional MOSFET device;
wherein, 1-grid metal region, 1' -source metal region, 2-photoetching source electrode hole, 3-insulating medium layer and 4-N+The structure comprises a source contact region, a 5-P type body region, a 6-gate electrode, a 7-gate oxide layer, an 8-N type epitaxial layer, a 9-semiconductor substrate and a 10-drain metal electrode;
fig. 2 is a schematic structural diagram of a MOSFET device silicon carbide trench according to an embodiment of the invention;
wherein, 21-grid metal region, 21' -source metal region, 22-photoetching source electrode hole, 23-insulating medium layer and 24-N+A source contact region, a 25-P-type body region, a 26-gate electrode, a 27-gate oxide, a 28-N-type epitaxial layer, a 29-semiconductor substrate, a 210-drain metal electrode, 211, 212, 213, 214-silicon carbide trench ring;
fig. 3 is a schematic structural view of a MOSFET device silicon carbide trench according to another embodiment of the invention;
wherein, 31-grid metal region, 31' -source metal region, 32-photoetching source electrode hole, 33-insulating medium layer and 34-N+A source contact region, a 35-P-type body region, a 36-gate electrode, a 37-gate oxide, a 38-N-type epitaxial layer, a 39-semiconductor substrate, a 310-drain metal electrode, 311, 312, 313, 314-silicon carbide trench ring.
Detailed Description
The following detailed description of embodiments of the invention is intended to be illustrative, and not to be construed as limiting the invention.
The invention is described in detail below by means of specific examples:
example 1
As shown in fig. 2, embodiment 1 provides a termination structure of a MOSFET device, which includes a set of four silicon carbide trench rings (211, 212, 213, 214) disposed on the periphery of a chip of the MOSFET device and distributed sequentially from inside to outside.
The silicon carbide trench rings (211, 212, 213, 214) are all closed ring-shaped.
The silicon carbide groove ring (211) at the innermost side is connected with the low potential of the chip, and the silicon carbide groove ring (211) at the innermost side is arranged at the side close to the grid metal (21).
The multiple groups of silicon carbide groove rings (214) on the outermost side are cut-off rings, the electric potentials of the cut-off rings are connected with the scribing channels (23) of the chip, and the silicon carbide groove rings (214) on the outermost side are arranged on one side close to the scribing channels (23).
Two groups of silicon carbide groove rings (212, 213) are also arranged between the innermost silicon carbide groove ring (211) and the outermost silicon carbide groove ring (214).
The method for manufacturing the terminal structure of the MOSFET device of embodiment 1 includes the steps of:
the low potential of the MOSFET device chip is connected with the silicon carbide groove ring (211) at the innermost side, then the silicon carbide groove rings (212, 213 and 214) are distributed from inside to outside in sequence, and the silicon carbide groove ring (214) at the outermost side is connected with the scribing way (23) of the chip.
Wherein the silicon carbide trench ring (211, 212, 213, 214) is a closed ring shape.
Example 2
As shown in fig. 3, embodiment 2 provides a termination structure of a MOSFET device, which includes a set of four silicon carbide trench rings (311, 312, 313, 314) disposed on the periphery of a chip of the MOSFET device and distributed sequentially from inside to outside.
The silicon carbide trench rings (311, 312, 313, 314) are all closed ring-shaped.
The innermost silicon carbide trench ring (311) is connected to a low potential of the chip.
The multiple groups of silicon carbide groove rings (314) on the outermost side are stop rings, the potentials of the stop rings are connected with the scribing channels (33) of the chip, and the silicon carbide groove rings (314) on the outermost side are arranged on one side close to the scribing channels (33).
Two groups of silicon carbide groove rings (312, 313) are also arranged between the innermost silicon carbide groove ring (311) and the outermost silicon carbide groove ring (314).
The method for manufacturing the terminal structure of the MOSFET device of embodiment 2 includes the steps of:
the low potential of the MOSFET device chip is connected with the silicon carbide groove ring (311) at the innermost side, then the silicon carbide groove rings (312, 313 and 314) are distributed from inside to outside in sequence, and the silicon carbide groove ring (314) at the outermost side is connected with a scribing channel (33) of the chip.
Wherein the silicon carbide trench ring (311, 312, 313, 314) is a closed ring shape.
In conclusion, the terminal structure of the MOSFET device disclosed by the invention has the advantages that the silicon carbide groove is connected with the low potential of the chip through the inner side, so that the formation of an anti-criminal channel is effectively inhibited, and the electric leakage can be inhibited; the silicon carbide grooves are connected with the high potential of the scribing channel on the outer side, the isolation effect can be enhanced, a leakage channel can be prevented from being formed between the inner side and the outer side due to the closed annular design, isolation terminals are formed through a plurality of silicon carbide groove rings, and the traditional P-type injection junction terminals are replaced, so that the problems of voltage resistance and leakage of the MOSFET device are solved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. The terminal structure of the MOSFET device is characterized by comprising more than one group of silicon carbide groove rings which are arranged on the periphery of a chip of the MOSFET device and are distributed in sequence from inside to outside;
the silicon carbide groove ring is a closed ring;
the silicon carbide groove ring at the innermost side is connected with the low potential of the chip;
the silicon carbide groove ring on the outermost side is a stop ring, and the potential of the stop ring is connected with a scribing channel of the chip.
2. The terminal structure of the MOSFET device is characterized in that the terminal structure of the MOSFET device is obtained by sequentially distributing silicon carbide groove rings on the periphery of a chip of the MOSFET device from inside to outside, and the innermost silicon carbide groove ring is connected with a low potential of the chip.
3. Termination structure for a MOSFET device according to claim 1 or 2,
the silicon carbide groove rings at the innermost side are arranged into more than one group;
the silicon carbide groove rings on the outermost side are arranged into more than one group;
the silicon carbide groove rings between the innermost silicon carbide groove ring and the outermost silicon carbide groove ring are arranged into more than one group.
4. A termination structure for a MOSFET device according to any of claims 1-3 wherein the innermost silicon carbide trench ring is disposed adjacent the gate metal.
5. The termination structure of a MOSFET device of any of claims 1-3, wherein the outermost silicon carbide trench ring is disposed adjacent to the scribe lane side.
6. The termination structure of a MOSFET device of any of claims 1-3, wherein the silicon carbide trench ring is a gate silicon carbide trench ring and the gate silicon carbide trench ring surrounds the gate silicon carbide trench ring at least one turn around its die.
7. A preparation method of a terminal structure of a MOSFET device is characterized by comprising the following steps:
connecting a low potential of a MOSFET device chip with the innermost silicon carbide groove ring, then sequentially distributing the silicon carbide groove rings from inside to outside, wherein the outermost silicon carbide groove ring is connected with a scribing channel of the chip;
wherein, the silicon carbide groove ring is a closed ring.
8. The method of claim 7, wherein the silicon carbide trench rings connected to the low potential of the chip are in at least one group, and the silicon carbide trench rings connected to the scribe line of the chip are in at least one group.
9. The method of claim 7 or 8, wherein said silicon carbide trench ring is a gate silicon carbide trench ring and said gate silicon carbide trench ring is wrapped around said die at least one time.
10. Use of a termination structure according to any of claims 1-6 in a MOSFET device.
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| CN108172609A (en) * | 2017-12-22 | 2018-06-15 | 北京世纪金光半导体有限公司 | Silicon carbide suspension node MOSFET device with periphery deep trench protection ring and ground loop |
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| CN101853854A (en) * | 2010-03-12 | 2010-10-06 | 无锡新洁能功率半导体有限公司 | Groove power MOS component with improved type terminal structure and manufacturing method thereof |
| US20110241110A1 (en) * | 2010-04-06 | 2011-10-06 | Shengan Xiao | Terminal structure for superjunction device and method of manufacturing the same |
| CN103824883A (en) * | 2012-11-19 | 2014-05-28 | 比亚迪股份有限公司 | Groove MOSFET with terminal voltage-withstanding structure and manufacturing method of groove MOSFET |
| CN108172609A (en) * | 2017-12-22 | 2018-06-15 | 北京世纪金光半导体有限公司 | Silicon carbide suspension node MOSFET device with periphery deep trench protection ring and ground loop |
| CN212695153U (en) * | 2020-07-16 | 2021-03-12 | 深圳市瑞之辰科技有限公司 | Terminal structure of MOSFET device |
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Inventor after: Ai Yulin Inventor after: Qiu Sanjun Inventor before: Qiu Sanjun |