CN111403471A - High-voltage Junction Field Effect Transistor (JFET) device, manufacturing method thereof and layout structure of high-voltage JFET device - Google Patents
High-voltage Junction Field Effect Transistor (JFET) device, manufacturing method thereof and layout structure of high-voltage JFET device Download PDFInfo
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- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 59
- 229920005591 polysilicon Polymers 0.000 claims description 57
- 239000010410 layer Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 42
- 230000008569 process Effects 0.000 claims description 30
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
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Abstract
The application discloses a high-voltage JFET device, a manufacturing method of the high-voltage JFET device and a layout structure of the high-voltage JFET device, and relates to the field of semiconductor manufacturing. The JFET device comprises a substrate, an N-type deep well and a P-type well arranged in the N-type deep well; a first P-type region and a first N-type region are arranged in the P-type well, and the first P-type region and the first N-type region are led out and then are in short circuit to form a grid electrode of the JFET device; a second N-type region is arranged in the N-type deep well, and the second N-type region is led out to form a source electrode of the JFET device; the surface of the N-type deep well is also provided with field oxygen; a current density adjusting region is arranged in the N-type deep well and is positioned between the grid electrode and the source electrode of the JFET device, and the current density adjusting region is formed by transversely pushing and connecting a plurality of N-type deep well sections; the problem that the off-state withstand voltage is changed when the on-state withstand voltage of the existing JFET device is changed is solved; the on-state withstand voltage of the JFET device is improved, and meanwhile the effect of off-state withstand voltage is not influenced.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a high-voltage JFET device, a manufacturing method thereof and a layout structure of the high-voltage JFET device.
Background
In the existing high-voltage BCD process, on the basis of developing high-voltage L DMOS, a parasitic structure, i.e., a Junction Field-Effect Transistor (JFET), is generated on a terminal structure, and the parasitic JFET and the high-voltage L DMOS share the same drain and drift lengths.
For the ultra-high voltage JFET device with the withstand voltage of more than 300V, when the JFET device is in an on state, a drain end bears high voltage, the surface current of a drift region is larger, and the on-state withstand voltage (on-BV) is far lower than the off-state withstand voltage (off-BV). In the related art, the on-state withstand voltage is improved by increasing the size of the drift region to improve the off-state withstand voltage.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a high-voltage JFET device, a manufacturing method thereof and a layout structure of the high-voltage JFET device. The technical scheme is as follows.
In a first aspect, embodiments of the present application provide a high-voltage JFET device, including a substrate, an N-type deep well disposed in the substrate, and a P-type well disposed in the N-type deep well;
a first P-type region and a first N-type region are arranged in the P-type well, and the first P-type region and the first N-type region are led out and then are in short circuit to form a grid electrode of the JFET device;
a second N-type region and a third N-type region are further arranged in the N-type deep well, the second N-type region and the third N-type region are respectively arranged on the outer side of the P-type well, and the second N-type region is led out to form a source electrode of the JFET device;
the surface of the N-type deep well is also provided with field oxygen, and the field oxygen is positioned between the P-type well and the third N-type region;
a current density adjusting region is arranged in the N-type deep well and is positioned between the grid electrode and the source electrode of the JFET device, and the current density adjusting region is formed by transversely pushing and connecting a plurality of N-type deep well sections;
and a second P-type region is also arranged in the substrate and is positioned at the outer side of the N-type deep well.
Optionally, the surface of the P-type well is further provided with a gate oxide layer and a polysilicon layer, and the gate oxide layer and the polysilicon layer on the surface of the P-type well extend to the surface of the field oxide;
a polysilicon field plate is also arranged on the surface of the field oxygen;
an interlayer dielectric layer is arranged on the surface of the substrate;
the first P-type region, the second P-type region, the first N-type region, the second N-type region, the third N-type region, the polycrystalline silicon layer and the polycrystalline silicon field plate are respectively connected with the metal electrode through holes in the interlayer dielectric layer.
Optionally, the width of each N-type deep well segment is 2 to 10 microns.
Optionally, the distance between any two adjacent N-type deep well segments is 2 microns to 10 microns.
In a second aspect, an embodiment of the present application provides a method for manufacturing a high-voltage JEFT device, where the method includes:
providing a substrate, performing ion implantation on a first deep well region and a second deep well region in the substrate, and performing high-temperature well pushing to form an N-type deep well, wherein the first deep well region comprises a plurality of N-type deep well sections;
forming field oxygen in the second deep well region;
forming a P-type well in the second deep well region, the P-type well being adjacent to the field oxide;
forming a first P-type region, a second P-type region, a first N-type region, a second N-type region and a third N-type region through a photoetching process and an ion implantation process, wherein the first P-type region and the first N-type region are positioned in a P-type well, the second N-type region is positioned in an N-type deep well and is far away from field oxygen, and the third N-type region is positioned in the N-type deep well and is adjacent to the field oxygen;
depositing an interlayer dielectric layer;
respectively leading out the first P type area, the second P type area, the first N type area, the second N type area and the third N type area through the through holes in the interlayer dielectric layer;
and forming a metal layer on the surface of the interlayer dielectric layer, respectively connecting the first P-type region, the second P-type region, the first N-type region, the second N-type region and the third N-type region with metal electrodes, forming a grid electrode of the JFET device by short-circuiting the first P-type region and the first N-type region, and forming a source electrode of the JFET device after the second N-type region is led out.
Optionally, before forming the first P-type region, the second P-type region, the first N-type region, the second N-type region, and the third N-type region through a photolithography process and an ion implantation process, the method further includes:
depositing a gate oxide layer and a polysilicon layer;
forming a gate oxide layer and a polysilicon gate on the surface of the P-type well through a photoetching process and an etching process, wherein the polysilicon gate extends to the surface of the field oxide, and a polysilicon field plate is formed on the surface of the field oxide;
the polysilicon gate is a polysilicon gate of an L DMOS device.
Optionally, the width of each N-type deep well segment is 2 to 10 microns.
Optionally, the distance between any two adjacent N-type deep well segments is 2 microns to 10 microns.
Optionally, when the high-temperature trap is performed, the reaction temperature is greater than 1000 ℃, and the reaction time is greater than 100 minutes.
In a third aspect, an embodiment of the present application provides a layout structure of a high-voltage JFET device, including a drain, a source, and a gate;
the grid is arranged on the outer side of the drain in a surrounding mode, and the source is arranged on the outer side of the grid;
the drain electrode, the source electrode and the grid electrode are arranged in the N-type deep well, and the N-type deep well between the grid electrode and the source electrode is arranged in a segmented mode.
Optionally, the field plate further comprises a first polysilicon field plate and a second polysilicon field plate;
the first polysilicon field plate is positioned on the inner side of the second polysilicon field plate, and the first polysilicon field plate is positioned on the outer side of the drain electrode;
the second polysilicon field plate is positioned at the inner side of the grid electrode, and the second polysilicon field plate is partially overlapped with the grid electrode.
Optionally, the N-type deep well under the gate is segmented.
Optionally, the source electrode is circular or square or semicircular or fan-shaped or rectangular.
The technical scheme at least comprises the following advantages:
the N-type deep well is internally provided with a current density adjusting region formed by pushing and connecting a plurality of N-type deep well sections, so that the current trend in an on state is changed, the surface current density of the drift region part is reduced, the current is led into the body, the on-state withstand voltage on-BV of the JFET device is improved, and meanwhile, the off-state withstand voltage off-BV of the JFET device is not influenced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a high-voltage JFET device according to an embodiment of the present disclosure;
figure 2 is a graph of current density for a prior art JFET device;
fig. 3 is a current density graph of a high-voltage JFET device provided by an exemplary embodiment of the present application;
FIG. 4 is a graphical illustration of off withstand voltage off-BV curves for a prior art JFET device and a high voltage JFET device provided by embodiments of the present application;
fig. 5 is a graph schematically illustrating the on-state withstand voltage on-BV curves of the prior JFET device and the high-voltage JFET device provided by the embodiments of the present application;
fig. 6 is a flow chart of a method of fabricating a high voltage JFET device according to embodiments of the present application;
fig. 7 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 8 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 9 is a flow chart of a fabrication process for a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 10 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 11 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 12 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 13 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 14 is a flow chart of a process for fabricating a high voltage JFET device provided by an exemplary embodiment of the present application;
fig. 15 is a schematic diagram of a layout structure of a high-voltage JFET device according to an embodiment of the present application;
fig. 16 is a schematic diagram of a layout structure of another high-voltage JFET device provided by an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a schematic structural diagram of a high-voltage JFET device according to an embodiment of the present disclosure is shown.
The high-voltage JFET device is parasitic on the high-voltage L DMOS device, and the grid electrode of the high-voltage JFET device is formed by the source end and the substrate end of the high-voltage L DMOS device in a parasitic mode, so that the parasitic pinch-off function of the JFET device is achieved.
The high-voltage JFET device comprises a substrate 101, an N-type deep well (DNW)102 arranged in the substrate 101, and a P-type well (PW)103 arranged in the N-type deep well 102.
A first P-type region 104 and a first N-type region 105 are arranged in the P-type well 103, the first P-type region 104 and the first N-type region 105 are led out and then are in short circuit to form a grid electrode of the JFET device, and the first P-type region 104 and the first N-type region 105 are led out and then are in short circuit to form a source electrode of L DMOS.
The N-type deep well 102 is also internally provided with a second N-type region 106 and a third N-type region 107, the second N-type region 106 and the third N-type region 107 are respectively arranged at the outer side of the P-type well 103, the second N-type region 106 forms a source electrode of the JFET device after being led out, and the third N-type region 107 forms a drain electrode of the JFET device after being led out.
A field oxide 108 is further disposed on the surface of the N-type deep well 102, and the field oxide 108 is located between the P-type well 103 and the third N-type region 107.
A current density modulation region 11 is present within the N-type deep well 102 and the current density modulation region 11 is located between the gate and source of the JFET device. As shown in fig. 1, the current density adjustment region 11 is located between the second N-type region 106 of the JFET device and the P-type well 103.
The current density adjusting region 11 is formed by laterally pushing and connecting a plurality of N-type deep well sections.
Optionally, the current density adjusting region is formed by laterally pushing and connecting at least 2N-type deep well segments.
A second P-type region 109 is also disposed in the substrate 101, and the second P-type region 109 is located outside the N-type deep well 102.
The existence of the current density adjusting area enables the N-type deep well to generate transverse concentration gradient change, compared with the existing JFET structure, the concentration of the N-type deep well in the source area is reduced, the trend of current in an on state is changed, the surface current density of a drift area part is reduced, the current is led into a body, the on state withstand voltage on-BV of the JFET device is improved, and meanwhile, the off state withstand voltage off-BV of the JFET device is not influenced.
As shown in fig. 1, the surface of the P-type well 103 is further provided with a gate oxide layer and a polysilicon layer 110, the gate oxide layer and the polysilicon layer 110 on the surface of the P-type well 103 extend to the surface of the field oxide 108, the surface of the field oxide 108 is further provided with a polysilicon field plate 111, and the polysilicon layer 110 is the gate of the L DMOS device.
An interlayer dielectric layer 112 is disposed on the surface of the substrate 101.
The first P-type region 104, the second P-type region 109, the first N-type region 105, the second N-type region 106, the third N-type region 107, the polysilicon layer 110 and the polysilicon field plate 111 are respectively connected with a metal electrode 114 through a through hole 113 in an interlayer dielectric layer 112.
Optionally, the width of each N-type deep well segment is 2 to 10 microns.
Optionally, the distance between any two adjacent N-type deep well segments is 2 microns to 10 microns.
Fig. 2 schematically shows a current density diagram corresponding to an existing JFET device, fig. 3 shows a current density diagram of a high-voltage JFET device provided by an embodiment of the present application, fig. 4 shows a graph schematically illustrating an off-state withstand voltage on-BV of the existing JFET device and the high-voltage JFET device provided by the embodiment of the present application, and fig. 5 shows a graph schematically illustrating an on-state withstand voltage on-BV of the existing JFET device and the high-voltage JFET device provided by the embodiment of the present application; the current density adjusting region formed by pushing and connecting a plurality of N-type deep well sections is arranged in the N-type deep well, the current trend in the on state is changed, the surface current density of the drift region part is reduced, the current is led into the body, the on-state withstand voltage on-BV of the JFET device is improved, and meanwhile, the off-state withstand voltage off-BV of the JFET device is not influenced.
Different concentration gradient distributions can be formed by adjusting the width of the N-type deep well sections and the distance between the N-type deep well sections, so that different withstand voltage requirements are met.
Referring to fig. 6, a flow chart of a method for manufacturing a high-voltage JFET device according to an embodiment of the present application is shown. As shown in fig. 6, the method for manufacturing the high-voltage JFET device at least comprises the following steps:
And defining a first deep well region and a second deep well region on the substrate through a photoetching process.
As shown in fig. 7, the portions above the N-type deep well segments 71 in the first deep well region S1 and above the second deep well region S2 are not covered with the photoresist 72, and the remaining portions are covered with the photoresist 72.
The first deep well region S1 includes a plurality of N-type deep well segments 71, and the number of the N-type deep well segments 71 is determined according to actual conditions; fig. 7 is merely an exemplary illustration, and does not limit the specific number of N-type deep well segments 71.
Ion implantation is performed on the first deep well region S1 and the second deep well region S2, and then high-temperature drive-in is performed, the first deep well region and the second deep well region are connected to form an N-type deep well 102, and a current density adjustment region 11 is formed in the N-type deep well 102, as shown in fig. 8.
Optionally, the first deep well region includes at least 2N-type deep well segments.
In step 602, field oxide is formed in the second deep well region.
As shown in fig. 9, the surface of the second deep well region S2 is formed with field oxygen 108.
A P-type deep well region is defined in the surface of the second deep well region S2 in the substrate 101 by a photolithography process, ion implantation is performed, and activation by thermal annealing is performed, forming a P-type well 103 in the second deep well region S2, as shown in fig. 10.
And 604, forming a first P-type region, a second P-type region, a first N-type region, a second N-type region and a third N-type region through a photoetching process and an ion implantation process, wherein the first P-type region and the first N-type region are positioned in the P-type well, the second N-type region is positioned in the N-type deep well and is far away from the field oxide, and the third N-type region is positioned in the N-type deep well and is adjacent to the field oxide.
As shown in fig. 11, a first P-type region 104, a second P-type region 109, a first N-type region 105, a second N-type region 106, and a third N-type region 107 are formed on a substrate 101.
As shown in fig. 12, an interlevel dielectric layer 112 is deposited on the surface of the substrate 101.
And 606, respectively leading out the first P type area, the second P type area, the first N type area, the second N type area and the third N type area through the through holes in the interlayer dielectric layer.
A through hole 113 is etched in the interlayer dielectric layer 112, and the first P-type region 104, the second P-type region 109, the first N-type region 105, the second N-type region 106, and the third N-type region 107 are respectively led out through the through hole 113, as shown in fig. 13.
And 607, forming a metal layer on the surface of the interlayer dielectric layer, respectively connecting the first P-type region, the second P-type region, the first N-type region, the second N-type region and the third N-type region with metal electrodes, forming a grid electrode of the JFET device by short-circuiting the first P-type region and the first N-type region, and forming a source electrode of the JFET device after the second N-type region is led out.
As shown in fig. 1, the first P-type region 104, the second P-type region 109, the first N-type region 105, the second N-type region 106, and the third N-type region 107 are connected to a metal electrode 114, and the first P-type region 104 and the first N-type region 105 are shorted by the metal electrode 114.
In summary, in the manufacturing method of the high-voltage JFET device provided in the embodiment of the present application, ion implantation is performed on a first deep well region and a second deep well region in a substrate, the first deep well region includes a plurality of N-type deep well segments, the first deep well region and the second deep well region are merged into an N-type deep well by high-temperature drive-in, a field oxide and a P-type well are formed in the second deep well region, a first N-type region, a second N-type region, a third N-type region, a first P-type region and a second P-type region are formed by photolithography and ion implantation processes, an interlayer dielectric layer is deposited, and the first N-type region, the second N-type region, the third N-type region, the first P-type region and the second P-type region are led out through holes in the interlayer dielectric layer to be connected with metal electrodes, so as to form a gate and a source of the device; because a segmented injection mode is adopted when the N-type deep well is formed, a current density adjusting region is formed between the source electrode and the grid electrode of the JFET, and transverse concentration gradient change is generated in the N-type deep well; the problem that the off-state withstand voltage of the existing JFET device is changed when the on-state withstand voltage is adjusted is solved; the effect of improving the on-state withstand voltage of the JFET device is achieved under the condition that the off-state withstand voltage of the JFET device is not influenced.
In an alternative implementation based on the embodiment shown in fig. 7, the method further comprises, before step 604, depositing gate oxide and polysilicon and forming a gate and a field plate by photolithography and etching processes, that is, after step 603 and before step 604, the method further comprises steps 6031 and 6031:
step 6031, a gate oxide layer and a polysilicon layer are deposited.
Step 6032, forming a gate oxide layer and a polysilicon gate on the surface of the P-type well by a photolithography process and an etching process, wherein the polysilicon gate extends to the surface of the field oxide, and a polysilicon field plate is formed on the surface of the field oxide.
As shown in fig. 14, a gate oxide layer and a polysilicon gate 110 are formed on the surface of P-well 102, polysilicon gate 110 extends to the surface of field oxide 108, and a polysilicon field plate 111 is formed on the surface of field oxide 108.
The polysilicon gate 110 is the polysilicon gate of an L DMOS device.
In an alternative implementation based on the embodiment shown in fig. 7, forming field oxygen in the second deep well region may be achieved by:
growing a thin oxide layer on the surface of the substrate, depositing a silicon nitride layer on the thin oxide layer, opening a region corresponding to the field oxygen on the second deep well region through photoetching and etching processes, oxidizing the opened window region, and then removing the silicon nitride layer and the thin oxide layer on the surface of the substrate to obtain the field oxygen.
In an alternative embodiment based on the embodiment shown in fig. 7, the width of each N-type deep well segment is 2 to 10 microns.
In an alternative embodiment based on the embodiment shown in fig. 7, the distance between any two adjacent N-type deep well segments is 2 to 10 microns.
Different concentration gradient distributions can be formed by adjusting the width of the N-type deep well sections and the distance between the N-type deep well sections, so that different withstand voltage requirements are met.
In an alternative embodiment based on the embodiment shown in fig. 7, after ion implantation is performed on the first deep well region and the second deep well region, when high-temperature well pushing is performed, the reaction temperature is greater than 1000 degrees celsius, and the reaction time is greater than 100 minutes.
Referring to fig. 15, a schematic diagram of a layout structure of a high-voltage JFET device according to an embodiment of the present application is provided.
As shown in fig. 15, the layout structure of the high-voltage JFET device includes a drain electrode 21, a source electrode 22, and a gate electrode 23.
The gate 23 is disposed around the drain 21, and the source 22 is disposed outside the gate 23.
The drain 21, source 22 and gate 23 are disposed in the N-type deep well 24, and the N-type deep well between the gate 23 and source 22 is disposed in segments, as shown in region S3 in fig. 15.
The segmented N-type deep wells are arranged annularly from inside to outside, and an N-type deep well gap 25 is formed between the segmented N-type deep wells.
The segmented N-type deep well is arranged between the source electrode and the grid electrode of the JFET device, segmented ion injection can be realized, DNW is connected together in a high-temperature well pushing mode, the concentration of the N-type deep well at the source end is reduced, the surface current density of the drift region is reduced, the on-state withstand voltage of the JFET device is improved, and the off-state withstand voltage of the JFET device is not influenced.
By adjusting the segmented width and the interval of the N-type deep trap, different concentration gradient distribution of a source end can be formed, and different withstand voltage requirements can be met.
In an alternative embodiment based on the embodiment shown in fig. 15, the structural layout of the high-voltage JFET device further comprises a first polysilicon field plate 26 and a second polysilicon field plate 27, as shown in fig. 16.
The first polysilicon field plate 26 is located on the inside of the second polysilicon field plate 27 and the first polysilicon field plate 26 is located on the outside of the drain electrode 21. The second polysilicon field plate 27 is located on the inner side of the gate 23, and the second polysilicon field plate 26 overlaps with the gate 23 in a partial region.
In an alternative embodiment based on the embodiment shown in fig. 15 or 16, the N-type deep well under the gate is segmented.
The width of the segmented N-type deep well below the grid and the distance between any two segments of N-type deep wells are determined according to actual conditions. Different pinch-off voltages can be achieved for the JFET device by different segmentation distances.
In an alternative embodiment based on the embodiment shown in fig. 15 or 16, the source is circular or square or semicircular or sector or rectangle in shape; the shape of the N-type deep well arranged between the source electrode and the grid electrode in a segmented mode is changed along with the shape of the source electrode of the JFET device.
Optionally, the JFET device structure is circular, elliptical, bullet-shaped, etc. according to different area requirements of the JFET device.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (13)
1. A high-voltage JFET device is characterized by comprising a substrate, an N-type deep well arranged in the substrate, and a P-type well arranged in the N-type deep well;
a first P-type region and a first N-type region are arranged in the P-type well, and the first P-type region and the first N-type region are led out and then are in short connection to form a grid electrode of the JFET device;
a second N-type region and a third N-type region are further arranged in the N-type deep well, the second N-type region and the third N-type region are respectively arranged on the outer side of the P-type well, and the second N-type region is led out to form a source electrode of the JFET device;
the surface of the N-type deep well is also provided with field oxygen, and the field oxygen is positioned between the P-type well and the third N-type region;
a current density adjusting area is arranged in the N-type deep well, the current density adjusting area is positioned between a grid electrode and a source electrode of the JFET device, and the current density adjusting area is formed by transversely pushing and connecting a plurality of N-type deep well sections;
and a second P-type region is also arranged in the substrate and is positioned at the outer side of the N-type deep well.
2. The high-voltage JFET device of claim 1, wherein a surface of the P-type well is further provided with a gate oxide layer and a polysilicon layer, and the gate oxide layer and the polysilicon layer on the surface of the P-type well extend to a surface of the field oxide;
a polysilicon field plate is also arranged on the surface of the field oxygen;
an interlayer dielectric layer is arranged on the surface of the substrate;
the first P-type region, the second P-type region, the first N-type region, the second N-type region, the third N-type region, the polysilicon layer and the polysilicon field plate are respectively connected with a metal electrode through a through hole in the interlayer dielectric layer.
3. The high-voltage JFET device of claim 1 or claim 2, wherein each N-type deep well segment has a width of 2 to 10 microns.
4. The high-voltage JFET device of claim 1 or claim 2, wherein a distance between any two adjacent N-type deep well segments is 2 microns to 10 microns.
5. A method for manufacturing a high-voltage JEFT device is characterized by comprising the following steps:
providing a substrate, performing ion implantation on a first deep well region and a second deep well region in the substrate, and performing high-temperature well pushing to form an N-type deep well, wherein the first deep well region comprises a plurality of N-type deep well sections;
forming field oxygen in the second deep well region;
forming a P-type well in the second deep well region, the P-type well being adjacent to the field oxide;
forming a first P-type region, a second P-type region, a first N-type region, a second N-type region and a third N-type region through a photoetching process and an ion implantation process, wherein the first P-type region and the first N-type region are positioned in the P-type well, the second N-type region is positioned in the N-type deep well and is far away from the field oxygen, and the third N-type region is positioned in the N-type deep well and is adjacent to the field oxygen;
depositing an interlayer dielectric layer;
respectively leading out the first P type area, the second P type area, the first N type area, the second N type area and the third N type area through a through hole in the interlayer dielectric layer;
and forming a metal layer on the surface of the interlayer dielectric layer, respectively connecting the first P-type region, the second P-type region, the first N-type region, the second N-type region and the third N-type region with metal electrodes, forming a grid electrode of the JFET device by short-circuiting the first P-type region and the first N-type region, and forming a source electrode of the JFET device after the second N-type region is led out.
6. The method of claim 5, wherein before the forming the first P-type region, the second P-type region, the first N-type region, the second N-type region and the third N-type region by the photolithography process and the ion implantation process, further comprising:
depositing a gate oxide layer and a polysilicon layer;
forming a gate oxide layer and a polysilicon gate on the surface of the P-type well through a photoetching process and an etching process, wherein the polysilicon gate extends to the surface of the field oxide, and a polysilicon field plate is formed on the surface of the field oxide;
the polysilicon gate is a polysilicon gate of an L DMOS device.
7. The method of claim 5 or 6, wherein each of the N-type deep well segments has a width of 2 to 10 microns.
8. The method of claim 5 or 6, wherein a distance between any two adjacent N-type deep well segments is 2 microns to 10 microns.
9. The method of claim 5, wherein the reaction temperature is greater than 1000 ℃ and the reaction time is greater than 100 minutes when performing the high temperature drive.
10. A layout structure of a high-voltage JFET device is characterized by comprising a drain electrode, a source electrode and a grid electrode;
the grid electrode is arranged on the outer side of the drain electrode in a surrounding mode, and the source electrode is arranged on the outer side of the grid electrode;
the drain electrode, the source electrode and the grid electrode are arranged in an N-type deep well, and the N-type deep well between the grid electrode and the source electrode is arranged in a segmented mode.
11. The structural layout of the high-voltage JFET device according to claim 10, further comprising a first polysilicon field plate and a second polysilicon field plate;
the first polysilicon field plate is positioned on the inner side of the second polysilicon field plate, and the first polysilicon field plate is positioned on the outer side of the drain electrode;
the second polysilicon field plate is positioned at the inner side of the grid electrode, and the second polysilicon field plate is partially overlapped with the grid electrode.
12. The layout structure of the high-voltage JFET device according to claim 10 or 11, wherein the N-type deep well below the gate is arranged in a segmented mode.
13. The layout structure of the high-voltage JFET device according to claim 10 or 11, wherein the source is circular or square or semicircular or fan-shaped or rectangular in shape.
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