CN105514040A - LDMOS device integrated with JFET and technical method - Google Patents

LDMOS device integrated with JFET and technical method Download PDF

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Publication number
CN105514040A
CN105514040A CN201510971891.XA CN201510971891A CN105514040A CN 105514040 A CN105514040 A CN 105514040A CN 201510971891 A CN201510971891 A CN 201510971891A CN 105514040 A CN105514040 A CN 105514040A
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type
trap
region
ldmos
substrate
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段文婷
钱文生
刘冬华
胡君
石晶
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

The invention discloses a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device integrated with JFET and arranged on a P type substrate. The P type substrate has an N type deep well therein. The N type deep well also has a P well therein. A field oxide is arranged on the surface of the P type substrate. A first P type injection region is arranged under the field oxide. One side of the field oxide is the P well, and the other side is a drain region of the LDMOS device. A source region of the LDMOS device is arranged in the P well. The P well also has a first heavy doping P type region which leads the P well out. A source region of the JFET is arranged at one side of the P well far from the field oxide. The P type substrate also has a second heavy doping P type region except the N type deep well. A silicon surface between the field oxide and the source region of the LDMOS has a gate oxide layer and a poly crystalline silicon gate. The field oxide near a drain end also has a poly crystalline silicon field plate. The substrate has a plurality of contact holes which lead out the electrodes of the device. The P well also has a second P type injection region arranged under the first heavy doping P type region and the source region of the LDMOS and at the bottom region of the P well. The invention also discloses a technical method of the device.

Description

The LDMOS device of integrated JFET and process
Technical field
The present invention relates to field of semiconductor devices, particularly the LDMOS device of a kind of integrated JFET.The invention still further relates to the process of described LDMOS device.
Background technology
LDMOS (LDMOS:LaterallyDiffusedMetalOxideSemiconductor Laterally Diffused Metal Oxide Semiconductor) device has high, the withstand voltage height of gain, power output is large, Heat stability is good, efficiency are high, Broadband Matching performance is good, be easy to the advantage such as integrated with CMOS technology, and its price is far below GaAs device, it is the very competitive power device of one.Its inner integrated JFET of 500VLDMOS, both there is discrete device high-voltage great-current feature, draw again the advantage that low-voltage ic high density intelligent logical controls, single-chip realizes the function that original multiple chip just can complete, greatly reduce area, reduce cost, improve efficiency, meet the developing direction of Modern Power Electronic Devices miniaturization, intellectuality, low energy consumption.Fig. 1 is structure is that 500VNLDMOS and Vp=30VJFET, JFET are integrated in LDMOS.In figure, device is arranged in the N-type deep trap in P type substrate, and the source electrode of LDMOS is also the grid of JFET simultaneously.During JFET charging, drain terminal voltage raises, and drives JFET electric current.P trap 104 lower position electromotive force raises along with drain terminal voltage and raises.And N-type deep trap/P trap PN junction (in Fig. 1 dotted line frame place) is in reverse-biased, source starts have leakage current to exist.When leakage current is enough large, parasitic NPN is opened (source region of N-type deep trap/P trap/LDMOS) and latch-up is occurred, and then causes component failure even to damage.
Summary of the invention
Technical problem to be solved by this invention is to provide the LDMOS device of a kind of integrated JFET, and it has lower source leakage current.
Another technical problem to be solved by this invention is to provide the process of the LDMOS device of described integrated JFET.
For solving the problem, the LDMOS device of integrated JFET of the present invention, is positioned in P type substrate, has N-type deep trap in described P type substrate, in N-type deep trap, also have P trap;
The surface of P type substrate has an oxygen, and the below of field oxygen has a P type injection region; The side of field oxygen is described P trap, and the opposite side of field oxygen is the drain region of described LDMOS device, is also the drain region of integrated JFET simultaneously;
There is in described P trap the source region of LDMOS device, also have the first heavily doped P-type district to be drawn by P trap;
Described P trap also has heavily doped N-type district, as the source region of JFET away from the side of field oxygen;
In described P type substrate, also there is outside N-type deep trap the second heavily doped P-type district, P type substrate is drawn;
Silicon face covering gate oxide layer between field oxygen and the source region of LDMOS, has polysilicon gate on gate oxide, by the field oxygen of drain terminal also has polysilicon field plate;
Substrate has multiple contact hole, device is carried out to the extraction of electrode;
In described P trap, also there is the 2nd P type injection region, be positioned at the below in the source region of the first heavily doped P-type district and LDMOS, the bottom section of P trap.
The process of the LDMOS device of integrated JFET of the present invention, comprises following processing step:
Step one, substrate forms deep trap by ion implantation, utilizes active area photoetching to open an oxygen region, etching Chang Yang district, raw long field oxide;
Step 2, well region is opened in photoetching, injects and forms P trap; Inject bottom P trap and below the oxygen of field and form first and second P type injection region;
Step 3, thermal oxide growth gate oxide, depositing polysilicon also etches, and forms polysilicon gate and drain terminal polysilicon field plate;
Step 4, carries out N-type doping and the heavy doping of P type respectively, the formation source region of LDMOS, drain region, first and second heavily doped P-type district, and as the heavily doped N-type district in JFET source region;
Step 5, etching contact hole makes and connects, and element manufacturing completes.
In described step one, substrate is P type substrate, and injecting the deep trap formed is N-type deep trap.
In described step 2, first and second P type implanted layer, for adopting same mask plate, injects formation simultaneously.
The LDMOS device of integrated JFET of the present invention, forms P type injection region bottom P trap, increases the impurity concentration bottom P trap, suppresses the unlatching of parasitic NPN pipe, reduces the source leakage current of device.Process of the present invention, then carry out the P type that P type injection region is carried out while injecting bottom P trap under an oxygen and inject, using same mask plate, when not increasing cost, improving the performance of device.
Accompanying drawing explanation
Fig. 1 is the structural representation of the LDMOS device of traditional integrated JFET.
Fig. 2 is the structural representation of the LDMOS device of the integrated JFET of the present invention.
Fig. 3 ~ 6 are present invention process step schematic diagrames.
Fig. 7 is present invention process flow chart of steps.
Description of reference numerals
101 is P type substrate, 102 is N-type deep traps, and 103 is an oxygen, and 104 is P traps, 105 is P type injection regions, 106 is gate oxides, and 107 is polysilicon gates, and 108 is source regions of JFET, 109 is second heavily doped P-type districts, 110 is contact holes, and 111 is first heavily doped P-type districts, and 112 is the 2nd P type injection regions.
Embodiment
The LDMOS device of integrated JFET of the present invention, as shown in Figure 2, is positioned in P type substrate 101, has N-type deep trap 102, in N-type deep trap 102, also have P trap 104 in described P type substrate 101; The surface of P type substrate 101 has an oxygen 103, and the below of field oxygen 103 has a P type injection region 105; The side of field oxygen 103 is described P trap 104, and the opposite side of field oxygen 103 is the drain region of described LDMOS device, is also the drain region of integrated JFET simultaneously; There is in described P trap 104 source region of LDMOS device, also have the first heavily doped P-type district 111 to be drawn by P trap; In described P trap 104, also there is the 2nd P type injection region 112, be positioned at the below in the source region of the first heavily doped P-type district 111 and LDMOS, the bottom section of P trap 104.
P trap 104 also has heavily doped N-type district 108, as the source region of JFET away from the side of field oxygen 103; In described P type substrate 101, also there is outside N-type deep trap 102 second heavily doped P-type district 109, P type substrate 101 is drawn.
Silicon face covering gate oxide layer 106 between field oxygen 103 and the source region of LDMOS, has polysilicon gate 107, by the field oxygen 103 of drain terminal also has polysilicon field plate on gate oxide 106.
Substrate has multiple contact hole 110, device is carried out to the extraction of electrode.
The LDMOS device of the integrated JFET of the present invention, increase P type in the bottom of P trap 104 and inject formation the 2nd P type injection region 112, increase the impurity concentration bottom P trap, suppress the unlatching of parasitic NPN pipe, under identical drain terminal voltage, the present invention is relative to traditional devices, and source leakage current can be reduced to original 23%.
The process of the LDMOS device of integrated JFET of the present invention, comprises following processing step:
Step one, as shown in Figure 3, P type substrate 101 forms N-type deep trap 102 by ion implantation, utilizes active area photoetching to open an oxygen region, etching Chang Yang district, raw long field oxide 103.
Step 2, well region is opened in photoetching, injects and forms P trap 104; With the below of field oxygen 103 bottom P trap 104, adopt same mask plate, inject formation the one P type injection region 105 and the 2nd P type injection region 112 simultaneously.The impurity of the 2nd P type injection region 112 and P trap 104 itself superposes, and the impurity concentration of the 2nd P type injection region is increased.As shown in Figure 4.
Step 3, thermal oxide growth gate oxide 106, depositing polysilicon also etches, and forms polysilicon gate 107 and drain terminal polysilicon field plate, as shown in Figure 5.
Step 4, carries out N-type doping and the heavy doping of P type respectively, as shown in Figure 6, and the formation source region of LDMOS, drain region, the first heavily doped P-type district 111 and the second heavily doped P-type district 109, and as the heavily doped N-type district 108 in JFET source region.
Step 5, etching contact hole 110 makes and connects, and element manufacturing completes.Finally complete as shown in Figure 2.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. a LDMOS device of integrated JFET, is positioned in P type substrate, has N-type deep trap in described P type substrate, in N-type deep trap, also have P trap;
The surface of P type substrate has an oxygen, and the below of field oxygen has a P type injection region; The side of field oxygen is described P trap, and the opposite side of field oxygen is the drain region of described LDMOS device, is also the drain region of integrated JFET simultaneously;
There is in described P trap the source region of LDMOS device, also have the first heavily doped P-type district to be drawn by P trap;
Described P trap also has heavily doped N-type district, as the source region of JFET away from the side of field oxygen;
In described P type substrate, also there is outside N-type deep trap the second heavily doped P-type district, P type substrate is drawn;
Silicon face covering gate oxide layer between field oxygen and the source region of LDMOS, has polysilicon gate on gate oxide, by the field oxygen of drain terminal also has polysilicon field plate;
Substrate has multiple contact hole, device is carried out to the extraction of electrode;
It is characterized in that: in described P trap that also there is the 2nd P type injection region, be positioned at the below in the source region of the first heavily doped P-type district and LDMOS, the bottom section of P trap.
2. manufacture the process of the LDMOS device of integrated JFET as claimed in claim 1, it is characterized in that: comprise following processing step:
Step one, substrate forms deep trap by ion implantation, utilizes active area photoetching to open an oxygen region, etching Chang Yang district, raw long field oxide;
Step 2, well region is opened in photoetching, injects and forms P trap; Inject bottom P trap and below the oxygen of field and form first and second P type injection region;
Step 3, thermal oxide growth gate oxide, depositing polysilicon also etches, and forms polysilicon gate and drain terminal polysilicon field plate;
Step 4, carries out N-type doping and the heavy doping of P type respectively, the formation source region of LDMOS, drain region, first and second heavily doped P-type district, and as the heavily doped N-type district in JFET source region;
Step 5, etching contact hole makes and connects, and element manufacturing completes.
3. as claimed in claim 2, it is characterized in that: in described step one, substrate is P type substrate, and injecting the deep trap formed is N-type deep trap.
4. as claimed in claim 2, it is characterized in that: in described step 2, first and second P type implanted layer, for adopting same mask plate, injecting formation simultaneously.
CN201510971891.XA 2015-12-22 2015-12-22 LDMOS device integrated with JFET and technical method Pending CN105514040A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128727A (en) * 2019-12-10 2020-05-08 上海华虹宏力半导体制造有限公司 Manufacturing method of JFET device, JFET device and layout structure of JFET device
CN111987094A (en) * 2020-09-29 2020-11-24 上海华虹宏力半导体制造有限公司 High voltage ESD structure
CN112909083A (en) * 2021-02-26 2021-06-04 上海华虹宏力半导体制造有限公司 High-voltage JFET device structure capable of improving voltage-withstanding reliability and manufacturing method thereof

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CN101005071A (en) * 2006-11-24 2007-07-25 杭州士兰微电子股份有限公司 Composite field effect transistor structure
CN101714558A (en) * 2008-09-30 2010-05-26 三垦电气株式会社 A semiconductor device
US20110241083A1 (en) * 2010-03-30 2011-10-06 Freescale Semiconductor, Inc. Semiconductor device and method
CN104617148A (en) * 2015-01-30 2015-05-13 上海华虹宏力半导体制造有限公司 Isolation N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
CN101005071A (en) * 2006-11-24 2007-07-25 杭州士兰微电子股份有限公司 Composite field effect transistor structure
CN101714558A (en) * 2008-09-30 2010-05-26 三垦电气株式会社 A semiconductor device
US20110241083A1 (en) * 2010-03-30 2011-10-06 Freescale Semiconductor, Inc. Semiconductor device and method
CN104617148A (en) * 2015-01-30 2015-05-13 上海华虹宏力半导体制造有限公司 Isolation N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128727A (en) * 2019-12-10 2020-05-08 上海华虹宏力半导体制造有限公司 Manufacturing method of JFET device, JFET device and layout structure of JFET device
CN111128727B (en) * 2019-12-10 2023-08-18 上海华虹宏力半导体制造有限公司 Manufacturing method of JFET device, JFET device and layout structure of JFET device
CN111987094A (en) * 2020-09-29 2020-11-24 上海华虹宏力半导体制造有限公司 High voltage ESD structure
CN111987094B (en) * 2020-09-29 2023-10-20 上海华虹宏力半导体制造有限公司 High voltage ESD structure
CN112909083A (en) * 2021-02-26 2021-06-04 上海华虹宏力半导体制造有限公司 High-voltage JFET device structure capable of improving voltage-withstanding reliability and manufacturing method thereof
CN112909083B (en) * 2021-02-26 2023-08-22 上海华虹宏力半导体制造有限公司 High-voltage JFET device structure for improving withstand voltage reliability and manufacturing method thereof

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