CN110911495B - Groove VDMOS device integrated with ESD protection and manufacturing method - Google Patents
Groove VDMOS device integrated with ESD protection and manufacturing method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000007667 floating Methods 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 74
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 239000000945 filler Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 230000001413 cellular effect Effects 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 abstract description 7
- 238000000206 photolithography Methods 0.000 abstract description 4
- 230000000670 limiting effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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Abstract
Hair brushThe invention provides a trench VDMOS device integrated with ESD protection and a manufacturing method thereof, wherein the trench VDMOS device comprises a trench VDMOS structure and an ESD protection structure; the trench VDMOS structure comprises a cell region and a terminal protection region, the terminal protection region adopts a floating field limiting ring and comprises a voltage division ring and a stop ring, the ESD protection structure comprises a plurality of Zener diode units, and the ESD protection structure is connected to two ends of a grid metal and a source metal of the trench VDMOS structure; the groove VDMOS can adjust the number of the voltage division rings and the spacing between the voltage division rings according to the voltage withstanding requirement, and the ESD protection structure is positioned on the SiO of the hard mask2Isolated from the trench VDMOS cell and compatible with the trench VDMOS fabrication process. On the premise of not influencing the performance of the device, the number of active area photolithography masks is reduced, and the manufacturing cost is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and relates to a trench VDMOS (Trench VDMOS) device integrated with ESD protection and a manufacturing method thereof.
Background
The improvement of the performance of the device and the reduction of the cost of the device are two important powers for promoting the continuous forward development of the power semiconductor device. An important component in power semiconductor devices: through continuous updating and development of the groove type power MOS device, a complete device manufacturing and processing technology can be realized through a four-time photoetching process technology, and the groove type power MOS device is widely applied to large-scale production of products.
The Chinese patents ZL200710302461.4 and ZL200810019085.2 disclose a deep groove high-power MOS device and a manufacturing method thereof at present, and relate to a groove type power MOS device manufactured by utilizing a four-time photoetching technology; the structure of the trench type power MOS device is shown in the attached figures 4 and 4 of Chinese patent ZL200710302461.4 and ZL 200810019085.2. The basic idea of the invention of the Chinese patents ZL200710302461.4 and ZL200810019085.2 is as follows: the trench power MOS device comprises a device active region formed by trench cells and a device terminal protection region formed by a trench structure on the cross section of the MOS device; the terminal protection region comprises a groove-shaped protection ring and a groove-shaped stop ring, and the protection ring and the stop ring are mutually independent, namely a certain distance is reserved between a partial pressure groove in the protection ring and the stop groove in the stop ring. The chinese patents ZL200710302461.4 and ZL200810019085.2 also disclose fabrication methods for forming MOS device structures that disclose forming MOS structures using four photolithography steps, including forming trenches using a trench reticle, forming N + active regions using a source reticle, forming holes and P + regions using a hole reticle, and forming metal electrodes using a metal reticle.
The terminal protection region in the structure of chinese patents ZL200710302461.4 and ZL200810019085.2 includes at least one voltage division ring of trench structure, and well layers of the second conductivity type exist throughout the terminal protection region, as shown in fig. 1; however, from practical simulation results, when the device is reverse voltage-resistant, the first trench structure voltage-dividing ring close to the active region bears most of the voltage drop, and the depletion layer bends upwards to the silicon surface along the side wall of the first trench structure voltage-dividing ring, specifically along the side wall of the trench close to one side of the active region; therefore, the width of the depletion layer is much narrower than that of the original depletion layer parallel to the silicon surface, so that potential lines in the depletion layer parallel to the side wall direction of the trench are too dense, an over-strong electric field is easily formed on the surface of the thin insulating gate oxide layer on the side wall of the trench, and the voltage-resistant reliability of the device is reduced.
The thickness of the gate oxide layer of the trench power MOS is relatively thin, and the structural characteristic determines that the trench power MOS device is an electrostatic sensitive device. With the continuous improvement of the process level and the great improvement of the trench power MOS device process, the device size is continuously reduced, and the gate oxide thickness is also thinner and thinner, which is more unfavorable for the electrostatic discharge (ESD) endurance of the device. Therefore, the capability of improving the electrostatic discharge protection of the trench power MOS device has a considerable effect on improving the reliability of the product. Failures caused by ESD problems include both destructive and potential failures. The destructive failure can cause the oxide layer, PN junction, even insulation layer breakdown and the like of the device, so that the device completely loses functions and cannot work normally; the latent failure does not directly destroy the functionality of the device, but causes damage inside the device, thereby weakening the electric overstress resistance of the device, shortening the service life of the device and the like, and affecting the reliability of an application circuit of the device.
Currently, common ESD protection structures include Silicon Controlled Rectifiers (SCRs), grounded-gate nmos (ggnmos), grounded-gate pmos (ggpmos), polysilicon/bulk silicon diodes, resistors, and the like. Such ESD protection structures are often used in I/O protection structures for integrated circuits and are rarely used in discrete components. Although the process implementation of the diode formed by polysilicon/bulk silicon and the ESD protection structures such as bulk silicon diodes is simple, the defects of large drain-source current, obvious parasitic effect, large substrate coupling noise and the like exist, the device can be damaged, and the normal operation of the device is not facilitated.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a trench VDMOS device integrated with ESD protection and a manufacturing method thereof, which improve the voltage endurance capability and the ESD resistance of the trench VDMOS device. Compared with the trench VDMOS of the existing four-time photoetching technology, the structure has good stability, strong process operability and reliable ESD protection and is compatible with the MOS device manufacturing process only by adding the ESD Pooly photoetching.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a groove VDMOS device integrated with ESD protection comprises a groove VDMOS structure and an ESD protection structure;
the trench VDMOS structure comprises a cell region and a terminal protection region, wherein the cell region comprises a plurality of cells which have the same structure and are connected in sequence, the cells comprise a first conduction type substrate 11, a first conduction type drift region 12 positioned on the first conduction type substrate 11, a second conduction type well region 21 positioned above the first conduction type drift region 12, a first conduction type source contact region 13 positioned above the second conduction type well region 21 and a second conduction type source contact region 22, a source metal 51 is positioned above a metal front medium 32 and is contacted with the second conduction type source contact region 22 and the first conduction type source contact region 13, the cell region further comprises a deep groove 1 extending into the first conduction type drift region 12, the gate dielectric layer 31 and the polysilicon filler 41 are positioned in the deep groove 1, and the metal front dielectric 32 is positioned above the polysilicon filler 41; the upper surface of the polysilicon filling 41 is higher than the upper surface of the second conductive type well region 21, and the lower surface of the polysilicon filling 41 is lower than the upper surface of the first conductive type drift region 12;
the terminal protection region comprises a voltage division ring 2 and a stop ring 3, and comprises a second conductive type well region 21, a hard mask medium layer 33 located above the first conductive type drift region 12, a second conductive type polycrystalline silicon region 23 located above the hard mask medium layer 33, a floating metal ring 55 located above the second conductive type polycrystalline silicon region 23, and a stop ring metal 54 located above the second conductive type polycrystalline silicon region 23 and in contact with the first conductive type contact 14.
The ESD protection structure comprises a plurality of zener diode cells, and is connected to two ends of the gate metal 52 and the source metal 51 of the trench VDMOS structure.
Preferably, the extension end of the deep groove is a circular lead terminal with a diameter larger than the width of the deep groove, or a polygonal lead terminal with a side length larger than the width of the deep groove, and the gate electrode lead hole is opened at the position of the lead terminal, so that the metal is connected with the polysilicon inside the deep groove.
Preferably, the ESD protection structure is located above the hard mask dielectric layer 33, and includes a first conductivity type polysilicon region 15, a second conductivity type polysilicon region 23, and a metal front dielectric 32 located on a polysilicon surface, where the first conductivity type polysilicon region 15 and the second conductivity type polysilicon region 23 are arranged at an interval, and the source metal 51 and the gate metal 52 are located above the metal front dielectric and are in contact with the second conductivity type polysilicon region 23 or the first conductivity type polysilicon region 15.
Preferably, the second-conductivity-type source contact region 22 is disposed in the second-conductivity-type well region 21, and the source metal 51 extends over the second-conductivity-type source contact region 22 and shorts the first-conductivity-type source terminal contact region 13 and the second-conductivity-type source contact region 22.
Preferably, the second conductive-type source contact regions 22 are arranged at intervals from the first conductive-type source contact regions 13 in the y direction, which is parallel to the length direction of the deep trenches 1.
Preferably, the doping concentration of the first conductive type source contact region 13 is higher than the doping concentration of the second conductive type source contact region 22.
Preferably, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
The invention also provides a manufacturing method of the trench VDMOS device integrated with the ESD protection, which comprises the following steps:
step 4, thermally growing to form a gate dielectric layer 31;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, depositing ESD polysilicon, injecting second conductive type ions to form a second conductive type polysilicon area 23, and etching the polysilicon to form an ESD protection polycrystal;
step 7, forming a second conductivity type well region 21 by injecting second conductivity type ions;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a first conductive type source contact region 13 and a first conductive type polycrystalline silicon region 15 by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
The invention has the beneficial effects that: the groove VDMOS can adjust the number of the voltage division rings and the spacing between the voltage division rings according to the voltage withstanding requirement, and the ESD protection structure is positioned on the SiO of the hard mask2The upper trench VDMOS cell is isolated and compatible with the trench VDMOS fabrication process. On the premise of not influencing the performance of the device, the number of active area photolithography masks is reduced, and the manufacturing cost is reduced.
Drawings
FIG. 1 is a diagram showing a simulation of off-state withstand voltage of a comparison file.
Fig. 2 is a schematic top plan view of a trench VDMOS integrated with ESD protection according to embodiment 1 of the present invention.
Fig. 3 is a sectional view a-a' of fig. 2.
Fig. 4 is a sectional view B-B' of fig. 2.
Fig. 5 is a cross-sectional view of C-C' of fig. 2.
Fig. 6 is a cross-sectional view of a trench VDMOS provided in embodiment 2 of the present invention.
Fig. 7 is a cross-sectional view of a trench VDMOS provided in embodiment 3 of the present invention.
Fig. 8 is a schematic structural diagram of a trench VDMOS cell region provided in embodiment 3 of the present invention.
FIGS. 9(a) -9(i) are process flow diagrams of the manufacturing method of example 1 of the present invention.
The structure of the semiconductor device comprises a deep groove 1, a voltage division ring 2, a stop ring 3, a first conductive type substrate 11, a first conductive type drift region 12, a first conductive type source contact region 13, a first conductive type contact 14, a first conductive type polycrystalline silicon region 15, a second conductive type well region 21, a second conductive type source contact region 22, a second conductive type polycrystalline silicon region 23, a gate dielectric layer 31, a metal front dielectric layer 32, a hard mask dielectric layer 33, a polycrystalline silicon filler 41, a source metal 51, a gate metal 52, a drain metal 53, a stop ring metal 54 and a floating metal ring 55.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
A groove VDMOS integrated with ESD protection comprises a groove VDMOS structure and an ESD protection structure;
the trench VDMOS structure comprises a cell region and a terminal protection region, wherein the cell region comprises a plurality of cells which have the same structure and are connected in sequence, the cells comprise a first conduction type substrate 11, a first conduction type drift region 12 positioned on the first conduction type substrate 11, a second conduction type well region 21 positioned above the first conduction type drift region 12, a first conduction type source contact region 13 positioned above the second conduction type well region 21 and a second conduction type source contact region 22, a source metal 51 is positioned above a metal front medium 32 and is contacted with the second conduction type source contact region 22 and the first conduction type source contact region 13, the cell region further comprises a deep groove 1 extending into the first conduction type drift region 12, the gate dielectric layer 31 and the polysilicon filler 41 are positioned in the deep groove 1, and the metal front dielectric 32 is positioned above the polysilicon filler 41; the upper surface of the polysilicon filling 41 is higher than the upper surface of the second conductive type well region 21, and the lower surface of the polysilicon filling 41 is lower than the upper surface of the first conductive type drift region 12;
the terminal protection region comprises a voltage division ring 2 and a stop ring 3, and comprises a second conductive type well region 21, a hard mask medium layer 33 located above the first conductive type drift region 12, a second conductive type polycrystalline silicon region 23 located above the hard mask medium layer 33, a floating metal ring 55 located above the second conductive type polycrystalline silicon region 23, and a stop ring metal 54 located above the second conductive type polycrystalline silicon region 23 and in contact with the first conductive type contact 14.
The ESD protection structure comprises a plurality of zener diode cells, and is connected to two ends of the gate metal 52 and the source metal 51 of the trench VDMOS structure.
FIG. 1 is a simulation diagram of the off-state withstand voltage of the comparison document, from the practical simulation result, when the device is in reverse withstand voltage, the first trench structure voltage division ring near the active region bears most of the voltage drop, and the depletion layer bends upwards to the silicon surface along the side wall of the first trench structure voltage division ring, specifically, along the side wall of the trench near the active region; therefore, the width of the depletion layer is much narrower than that of the original depletion layer parallel to the silicon surface, so that potential lines in the depletion layer parallel to the side wall direction of the trench are too dense, an over-strong electric field is easily formed on the surface of the thin insulating gate oxide layer on the side wall of the trench, and the voltage-resistant reliability of the device is reduced.
Fig. 2 is a top plan view of a trench VDMOS device with integrated ESD protection. As can be seen from the figure, the central area of the MOS device is provided with a strip-shaped cellular array, the periphery of the cellular is provided with a terminal protection ring, and the ESD protection structure is positioned below the gate Pad. The terminal protection ring is composed of a voltage division ring positioned at the inner ring and a stop ring positioned at the outer ring. The voltage division ring is two in the embodiment, but one or more than two protection ring structures can also be adopted, which needs to be determined according to the required breakdown voltage of the trench VDMOS.
Fig. 3 is a cross-sectional view a-a' of fig. 2, which is a cross-sectional view of a trench VDMOS device in accordance with an embodiment of the present invention. As can be seen from the figure, the grading ring adopts a floating field limiting ring, and includes a second conductive type well region 21, a hard mask dielectric layer 33 located above the first conductive type drift region 12, a second conductive type polysilicon region 23 located above the hard mask dielectric layer 33, and a floating metal ring 55 located above the second conductive type polysilicon region 23, where the second conductive type well region 21 and the floating metal ring 55 are in a floating state to form a terminal grading ring. The stop ring metal 54 connects the first conductivity type contact 14 and the second conductivity type polysilicon region 23 in the stop ring 3 to be equipotential, forming a stop ring.
Fig. 4 is a cross-sectional view B-B' of fig. 2, which is a cross-sectional view of a gate lead-out of a trench VDMOS device according to an embodiment of the present invention, where the extended end of the deep trench is a circular lead terminal with a diameter larger than the width of the deep trench or a polygonal lead terminal with a side length larger than the width of the deep trench, and a gate electrode lead hole is opened at the lead terminal position so that the metal is connected to the polysilicon inside the deep trench.
Fig. 5 is a cross-sectional view of C-C' of fig. 2, which is a schematic diagram of an ESD protection structure according to an embodiment of the invention, the ESD protection structure is located above the hard mask dielectric layer 33, and includes a first conductivity type polysilicon region 15, a second conductivity type polysilicon region 23, and a metal front dielectric 32 located on a polysilicon surface, the first conductivity type polysilicon region 15 and the second conductivity type polysilicon region 23 are arranged at an interval, and a source metal 51 and a gate metal 52 are located above the metal front dielectric and contact the second conductivity type polysilicon region 23 or the first conductivity type polysilicon region 15.
Preferably, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
The basic working principle of example 1 is as follows:
the voltage division ring 2 surrounds the center of the cellular area 1; when the MOS device is normally biased, the source is grounded, the drain metal 53 is forward biased, and the main junction is reverse biased to form a depletion layer. Since the concentration of the first conductivity type drift region 12 constituting the main junction is much smaller than the concentration of the second conductivity type well region 21, the depletion layer mainly spreads toward the first conductivity type drift region 12 side. When the depletion layer in the horizontal direction is expanded and contacted with the voltage division ring 2 close to the cellular region 1, most current carriers of the second conductive type well region 21 corresponding to the voltage division ring 2 flow into the depletion layer, and the horizontal electric field generated by the voltage division ring 2 is opposite to the horizontal electric field of the original main junction depletion layer in direction, so that the purpose of sharing the main junction voltage is achieved. In the same way, when the depletion region continues to expand outwards and contacts the grading ring 2 of the outer ring, the grading ring 2 has the same effect until the depletion layer expands to the outermost ring of grading ring 2, and the potential line of the depletion layer is received in the metal front medium 32 on the surface of the semiconductor substrate outside the outermost ring of grading ring 2. Because the bias voltage is weakened by the voltage division ring 2, compared with the groove-type protection terminal disclosed in ZL200710302461.4 and ZL200810019085.2, the electric field of the whole voltage division protection region, especially the intersection of the edge of the outermost ring of the voltage division ring 2 and the surface of the semiconductor substrate, is more even, the situation that the local electric field is too strong and premature breakdown is easily caused is avoided, and the voltage withstanding reliability of the device is improved. Moreover, compared with the structure disclosed in fig. 6 of ZL201010005206.5, the field oxide needs to be formed by adding a photolithography active region reticle, and the present invention utilizes a poly reticle of the ESD protection structure to implement the second conductivity type well region 21, thereby further reducing the cost.
When the grid voltage is greater than the trigger voltage of the ESD protection structure, the current passes through the grid metal 52, the ESD protection structure and the source metal 51, the grid oxide layer is prevented from being broken down by high voltage, and the reliability of the groove VDMOS is improved.
Example 2
Fig. 6 is a cross-sectional view of a trench VDMOS provided in embodiment 2, which is different from embodiment 1 in that a second-conductivity-type source contact region 22 is disposed in the second-conductivity-type well region 21, and a source metal 51 extends over the second-conductivity-type source contact region 22 and shorts the first-conductivity-type source contact region 13 and the second-conductivity-type source contact region 22.
Example 3
Fig. 7 is a cross-sectional view of a trench VDMOS provided in embodiment 3, which is different from embodiment 1 in that a second conductive-type source contact region 22 is arranged spaced apart from the first conductive-type source contact region 13 in the y direction. The y-direction is parallel to the length direction of the deep groove 1.
Fig. 8 is a schematic structural view of the trench VDMOS cell region provided in embodiment 3, wherein the doping concentration of the first-conductivity-type source contact region 13 is higher than the doping concentration of the second-conductivity-type source contact region 22.
As shown in fig. 9(a) -9(i), this embodiment further provides a method for manufacturing the trench VDMOS device with integrated ESD protection, including the following steps:
step 4, thermally growing to form a gate dielectric layer 31;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, depositing ESD polysilicon, injecting second conductive type ions to form a second conductive type polysilicon area 23, and etching the polysilicon to form an ESD protection polycrystal;
step 7, forming a second conductivity type well region 21 by injecting second conductivity type ions;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a first conductive type source contact region 13 and a first conductive type polycrystalline silicon region 15 by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A groove VDMOS device integrated with ESD protection is characterized by comprising a groove VDMOS structure and an ESD protection structure;
the VDMOS structure comprises a cell area and a terminal protection area, wherein the cell area comprises a plurality of cells which have the same structure and are sequentially connected, and the VDMOS structure comprises a first conduction type substrate, a first conduction type drift area positioned on the first conduction type substrate, a second conduction type well area positioned above the first conduction type drift area, a first conduction type source contact area and a second conduction type source contact area positioned above the second conduction type well area, source metal is positioned above a metal front medium and is contacted with the second conduction type source contact area and the first conduction type source contact area, the cell area also comprises a deep groove extending into the first conduction type drift area, a gate medium layer and a polysilicon filler positioned in the deep groove, and the metal front medium positioned above the polysilicon filler; the upper surface of the polycrystalline silicon filler is higher than the upper surface of the second conductive type well region, and the lower surface of the polycrystalline silicon filler is lower than the upper surface of the first conductive type drift region;
the terminal protection area comprises a voltage division ring which is positioned at the inner ring and surrounds the center of the cellular area and a stop ring which is positioned at the outer ring; the voltage division ring comprises a second conductive type well region positioned in the first conductive type drift region, a hard mask medium layer positioned above the first conductive type drift region, a second conductive type polycrystalline silicon region positioned above the hard mask medium layer, and a floating metal ring positioned above the second conductive type polycrystalline silicon region; the stop ring comprises a second conductive type well region positioned in the first conductive type drift region, a hard mask medium layer positioned above the first conductive type drift region, a second conductive type polycrystalline silicon region positioned above the hard mask medium layer, a first conductive type contact positioned in the second conductive type well region and stop ring metal positioned above the second conductive type polycrystalline silicon region, wherein the stop ring metal connects the first conductive type contact in the stop ring and the second conductive type polycrystalline silicon region to be equipotential so as to form the stop ring;
the ESD protection structure comprises a plurality of Zener diode units, the ESD protection structure is connected to two ends of grid metal and source metal of the groove VDMOS structure, the ESD protection structure is located above the hard mask medium layer and comprises a first conduction type polycrystalline silicon area, a second conduction type polycrystalline silicon area and a metal front medium located on the surface of the polycrystalline silicon, the first conduction type polycrystalline silicon area and the second conduction type polycrystalline silicon area are arranged at intervals, and the source metal and the grid metal are located above the metal front medium and are in contact with the second conduction type polycrystalline silicon area or the first conduction type polycrystalline silicon area.
2. The integrated ESD protected trench VDMOS device of claim 1, wherein: the extension end of the deep groove is a circular lead terminal with the diameter larger than the width of the deep groove or a polygonal lead terminal with the side length larger than the width of the deep groove, and a gate electrode lead hole is formed in the position of the lead terminal, so that metal is connected with polycrystalline silicon in the deep groove.
3. The integrated ESD protected trench VDMOS device of claim 1, wherein: the second conductive type source electrode contact region is arranged in the second conductive type well region, and the source electrode metal extends into the upper part of the second conductive type source electrode contact region and is in short circuit connection with the first conductive type source electrode contact region and the second conductive type source electrode contact region.
4. The integrated ESD protected trench VDMOS device of claim 1, wherein: the second conductive type source contact regions are arranged at intervals in the y direction parallel to the length direction of the deep trench from the first conductive type source contact regions.
5. The integrated ESD protected trench VDMOS device of claim 1, wherein: the doping concentration of the first conductive type source contact region is higher than that of the second conductive type source contact region.
6. The integrated ESD protected trench VDMOS device of any one of claims 1 to 5, wherein: the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
7. The method for manufacturing a trench VDMOS device integrated with ESD protection as claimed in any of claims 1 to 5, comprising the steps of:
step 1, a first conductive type substrate is adopted, and a first conductive type drift region (12) is formed in an epitaxial mode;
step 2, thermal growth or deposition of SiO2Forming a hard mask dielectric layer;
step 3, forming a deep groove by adopting photoetching and etching processes;
step 4, forming a gate dielectric layer by thermal growth;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, depositing ESD polycrystalline silicon, injecting second conductive type ions to form a second conductive type polycrystalline silicon area, and etching the polycrystalline silicon to form ESD protection polycrystalline silicon;
step 7, forming a second conductive type well region by injecting second conductive type ions;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a first conductive type source contact region (13) by first conductive type ion implantation, a first conductive type polysilicon region;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process; step 11, forming a second conductive type source contact region by second conductive type ion implantation;
step 12, depositing metal, and forming source metal, grid metal and stop ring metal through a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal.
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| CN101982881B (en) * | 2010-09-24 | 2012-12-12 | 江苏东光微电子股份有限公司 | ESD protection integrated power MOSFET or IGBT and preparation method thereof |
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