CN112838010A - 低导通电阻沟槽型功率半导体器件的制备方法 - Google Patents
低导通电阻沟槽型功率半导体器件的制备方法 Download PDFInfo
- Publication number
- CN112838010A CN112838010A CN202110032713.6A CN202110032713A CN112838010A CN 112838010 A CN112838010 A CN 112838010A CN 202110032713 A CN202110032713 A CN 202110032713A CN 112838010 A CN112838010 A CN 112838010A
- Authority
- CN
- China
- Prior art keywords
- layer
- main surface
- semiconductor device
- conductive type
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 230000001413 cellular effect Effects 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 238000002347 injection Methods 0.000 abstract description 6
- 239000007924 injection Substances 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明涉及一种沟槽型功率半导体器件的制备方法,尤其是一种低导通电阻沟槽型功率半导体器件的制备方法。本发明通过在元胞沟槽的槽底注入第一导电类型杂质离子,以能在元胞沟槽槽底的下方得到优化注入区,通过优化注入区能降低第一导电类型外延层的电阻率,使得导通电阻降低幅度远大于击穿电压的幅度,保证了击穿电压耐量的同时导通电阻有效的降低。在击穿电压有3%~5%余量的情况下,能优化15%~20%的导通电阻,此方法仅增加一步离子注入的工艺,工艺流程简单且制造成本也不会很高的增加,与现有工艺兼容,安全可靠。
Description
技术领域
本发明涉及一种沟槽型功率半导体器件的制备方法,尤其是一种低导通电阻沟槽型功率半导体器件的制备方法。
背景技术
随着半导体集成电路的不断发展,芯片尺寸不断缩小,工作电压也越来越小,因此,对电源管理的要求越来越高,尤其是低压直流-直流降压转换的效率。高效率小体积开关模式的电源运用普及,在PC、笔记本电脑领域,同时电动车、油电混合车(新能源车)、快速充电、无线充电等领域应用也正在快速兴起。几乎所有的这些领域使用的电源,都会用到功率MOSFET,而沟槽功率MOSFET器件则是这个大家庭的重要成员之一。
众所周知,对于沟槽MOSFETT来讲,导通电阻体现了功率半导体器件的导通能力,导通电阻的优化,可以使通态功耗降低,能源的节约,但是往往在优化的同时,击穿电压的降低幅度远远大于导通电阻优化的幅度,导致击穿电压耐量不够。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种低导通电阻的沟槽型功率半导体器件的制备方法,其通过在元胞沟槽的槽底离子注入,降低了外延层电阻率,使得导通电阻降低幅度远大于击穿电压的幅度,保证了击穿电压耐量的同时有效降低导通电阻。
按照本发明提供的技术方案,一种低导通电阻沟槽型功率半导体器件的制备方法,所述功率半导体器件的制备方法包括如下步骤:
步骤1、提供具有两个相对主面的半导体基板,所述两个相对主面包括第一主面以及与第一主面相对应的第二主面,在所述第一主面与第二主面间包括第一导电类型衬底以及邻接所述第一导电类型衬底的第一导电类型外延层;
步骤2、在第一主面上设置掩膜层,所述掩膜层覆盖在第一主面上;选择性地掩蔽和刻蚀所述掩膜层,并利用刻蚀后的掩膜层对第一导电类型外延层进行沟槽刻蚀,以能制备得到若干所需的元胞沟槽;
步骤3、利用掩膜层的遮挡,在上述第一主面上方进行第一导电类型杂质离子的注入,以能在元胞沟槽槽底的正下方制备得到优化注入区;
步骤4、去除上述掩膜层,在上述第一主面上进行所需的热氧化工艺,以能在元胞沟槽的侧壁以及底壁制备得到绝缘栅氧化层,所述绝缘栅氧化层覆盖元胞沟槽的侧壁以及底壁;
步骤5、在上述元胞沟槽内填充得到栅极导电多晶硅,所述栅极导电多晶硅通过绝缘栅氧化层与元胞沟槽的侧壁以及底壁绝缘隔离;
步骤6、在上述第一主面上进行离子注入,以在第一导电类型外延层内得到第二导电类型阱层,所述第二导电类型阱层位于元胞沟槽槽底的上方,且能在第二导电类型阱层内制备得到第一导电类型源区,所述第一导电类型源区与邻近元胞沟槽外上方的侧壁接触;
步骤7、在上述第一主面上淀积得到绝缘介质层,所述绝缘介质层覆盖在第一主面上,且绝缘介质层覆盖元胞沟槽的槽口;
步骤8、制备所需的源极接触孔,所述源极接触孔贯通绝缘介质层;
步骤9、在绝缘介质层上设置金属层,所述金属层包括源极金属层,所述源极金属层覆盖在绝缘介质层上,并能填充在源极接触孔内,填充在源极接触孔内的源极金属层与第二导电类型阱层以及第一导电类型源区欧姆接触;
步骤10、在第二主面上制备得到漏极金属层,所述漏极金属层与第一导电类型衬底欧姆接触。
所述半导体基板的材料包括硅。
步骤3中,第一导电类型杂质离子注入时,注入的能量为25KEV~35KEV,剂量为9e11~1.7e12。
步骤4中,在热氧化时,通过高温炉管工艺进行热氧化。
所述绝缘介质层包括二氧化硅层。
所述“第一导电类型”和“第二导电类型”两者中,对于N型功率半导体器件,第一导电类型指N型,第二导电类型为P型;对于P型功率半导体器件,第一导电类型与第二导电类型所指的类型与N型半导体器件相反。
本发明的优点:通过在元胞沟槽的槽底注入第一导电类型杂质离子,以能在元胞沟槽槽底的下方得到优化注入区,通过优化注入区能降低第一导电类型外延层的电阻率,使得导通电阻降低幅度远大于击穿电压的幅度,保证了击穿电压耐量的同时导通电阻有效的降低。在击穿电压有3%~5%余量的情况下,能优化15%~20%的导通电阻,此方法仅增加一步离子注入的工艺,工艺流程简单且制造成本也不会很高的增加,与现有工艺兼容,安全可靠。
附图说明
图1为本发明制备得到的功率半导体器件的示意图。
图2为本发明制备得到元胞沟槽时的示意图。
图3为本发明进行第一导电类型杂质离子注入的示意图。
附图标记说明:1-漏极金属层、2-N型衬底、3-N型外延层、4-绝缘栅氧化层、5-栅极导电多晶硅、6-P阱层、7-N+源区、8-绝缘介质层、9-源极金属层、10-掩膜层、11-元胞沟槽、12-优化注入区。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图1所示:为了能降低了外延层电阻率,使得导通电阻降低幅度远大于击穿电压的幅度,保证了击穿电压耐量的同时有效降低导通电阻,以N型功率半导体器件为例,本发明功率半导体器件的制备方法包括如下步骤:
步骤1、提供具有两个相对主面的半导体基板,所述两个相对主面包括第一主面以及与第一主面相对应的第二主面,在所述第一主面与第二主面间包括N型衬底2以及邻接所述N型衬底2的N型外延层3;
具体地,半导体基板可以采用硅,当然,也可以为其他常用的半导体材料,具体材料的类型可以根据实际需要选择。N型外延层3位于N型衬底2的上方,N型外延层3的表面能形成第一主面,N型衬底2远离第一主面的表面形成第二主面。
步骤2、在第一主面上设置掩膜层10,所述掩膜层10覆盖在第一主面上;选择性地掩蔽和刻蚀所述掩膜层10,并利用刻蚀后的掩膜层10对N型外延层3进行沟槽刻蚀,以能制备得到若干所需的元胞沟槽11;
具体,掩膜层10可以采用现有常用的形式,具体在第一主面上设置掩膜层10的过程等均与现有相一致,具体为本技术领域人员所熟知,此处不再赘述。掩膜层10覆盖在第一主面上,通过本技术领域常用的技术手段,能对掩膜层10进行选择性地掩蔽和刻蚀,以得到若干贯通掩膜层10的窗口,利用所述窗口对第一主面进行沟槽刻蚀,从而能制备得到所需的元胞沟槽11,如图2所示。具体对掩膜层10进行刻蚀,以及刻蚀得到元胞沟槽11的具体工艺过程与现有相一致,具体为本技术领域人员所熟知,此处不再赘述。
步骤3、利用掩膜层10的遮挡,在上述第一主面上方进行N型杂质离子的注入,以能在元胞沟槽11槽底的正下方制备得到优化注入区12;
具体地,在第一主面上方进行N型杂质离子的注入,由于掩膜层10的遮挡作用,以能使得N型杂质离子只会注入到元胞沟槽11槽底的正下方,从而能在元胞沟槽11槽底的正下方得到优化注入区12,优化注入区12的掺杂浓度大于N型外延层3的掺杂浓度,优化注入区12与元胞沟槽11的槽底接触,如图3所示。
本发明实施例中,注入的N型杂质离子可以为磷,注入的能量为25KEV~35KEV,注入的剂量一般需要根据击穿电压余量调配,注入剂量的范围为9e11~1.7e12。通过优化注入区12能降低导通电阻15%~20%,同时击穿电压仅影响到3%~5%。
步骤4、去除上述掩膜层10,在上述第一主面上进行所需的热氧化工艺,以能在元胞沟槽11的侧壁以及底壁制备得到绝缘栅氧化层4,所述绝缘栅氧化层4覆盖元胞沟槽的侧壁以及底壁;
具体地,采用本技术领域常用的技术手段实现对掩膜层10的去除,具体工艺过程等为本技术领域人员所熟知,此处不再赘述。
采用热氧化工艺时,采用高温炉管,具体热氧化工艺的过程等均可与现有相一致,具体为本技术领域人员所熟知,此处不再赘述。在热氧化后,能在元胞沟槽11的侧壁以及底壁制备得到绝缘栅氧化层4,同时,能在第一主面上形成表面绝缘氧化层。
步骤5、在上述元胞沟槽11内填充得到栅极导电多晶硅5,所述栅极导电多晶硅5通过绝缘栅氧化层4与元胞沟槽11的侧壁以及底壁绝缘隔离;
具体地,采用本技术领域常用的技术手段能在元胞沟槽11内填充得到栅极导电多晶硅5,栅极导电多晶硅5位于元胞沟槽11槽口的下方。
步骤6、在上述第一主面上进行离子注入,以在N型外延层3内得到P阱层6,所述P阱层6位于元胞沟槽11槽底的上方,且能在P阱层6内制备得到N+源区,所述第一导电类型源区与邻近元胞沟槽外上方的侧壁接触;
具体地,采用本技术领域常用的技术手段进行P型杂质离子注入,从而能在N型外延层3内得到P阱层6,P阱层6位于N型外延层3内的上部,且位于元胞沟槽11槽底的上方。在得到P阱层6后,通过N型杂质离子注入,能得到N+源区7,所述N+源区7与邻近元胞沟槽11外上方的侧壁接触,具体制备得到P阱层6、N+源区7的过程以及工艺条件均与现有相一致,具体为本技术领域人员所熟知,此处不再赘述。
步骤7、在上述第一主面上淀积得到绝缘介质层8,所述绝缘介质层8覆盖在第一主面上,且绝缘介质层8覆盖元胞沟槽11的槽口;
具体地,通过本技术领域常用的技术手段能制备得到绝缘介质层8,绝缘介质层8覆盖第一主面上,从而能利用绝缘介质层8覆盖元胞沟槽11的槽口。
步骤8、制备所需的源极接触孔,所述源极接触孔贯通绝缘介质层;
具体地,采用本技术领域常用的技术手段,能对绝缘介质层8进行接触孔刻蚀,以能制备得到所需的源极接触孔,源极接触孔贯通绝缘介质层8。
步骤9、在绝缘介质层上设置金属层,所述金属层包括源极金属层,所述源极金属层覆盖在绝缘介质层上,并能填充在源极接触孔内,填充在源极接触孔内的源极金属层与第二导电类型阱层以及第一导电类型源区欧姆接触;
具体地,采用本技术领域常用的技术手段,能制备得到金属层,金属层覆盖在绝缘介质层8上。制备得到的金属层一般包括源极金属层9,当然,也可包括栅极金属层,源极金属层与栅极金属层间绝缘隔离。制备得到的源极金属层9,覆盖在绝缘介质层8上,并能填充在源极接触孔内,填充在源极接触孔内的源极金属层9与P阱层6以及N+源区7欧姆接触。
步骤10、在第二主面上制备得到漏极金属层,所述漏极金属层与第一导电类型衬底欧姆接触。
具体地,采用本技术领域常用的技术手段能制备得到漏极金属层1,漏极金属层1与N型衬底2欧姆接触,通过漏极金属层1能形成漏电极,具体与现有相一致,具体为本技术领域人所熟知,此处不再赘述。
综上,本发明通过在元胞沟槽11的槽底注入N型杂质离子,以能在元胞沟槽11槽底的下方得到优化注入区12,通过优化注入区12能降低N型外延层3的电阻率,使得导通电阻降低幅度远大于击穿电压的幅度,保证了击穿电压耐量的同时导通电阻有效的降低了。在击穿电压有3%~5%余量的情况下,能优化15%~20%的导通电阻,此方法仅增加一步离子注入的工艺,工艺流程简单且制造成本也不会很高的增加,与现有工艺兼容,安全可靠。
Claims (5)
1.一种低导通电阻沟槽型功率半导体器件的制备方法,其特征是,所述功率半导体器件的制备方法包括如下步骤:
步骤1、提供具有两个相对主面的半导体基板,所述两个相对主面包括第一主面以及与第一主面相对应的第二主面,在所述第一主面与第二主面间包括第一导电类型衬底以及邻接所述第一导电类型衬底的第一导电类型外延层;
步骤2、在第一主面上设置掩膜层,所述掩膜层覆盖在第一主面上;选择性地掩蔽和刻蚀所述掩膜层,并利用刻蚀后的掩膜层对第一导电类型外延层进行沟槽刻蚀,以能制备得到若干所需的元胞沟槽;
步骤3、利用掩膜层的遮挡,在上述第一主面上方进行第一导电类型杂质离子的注入,以能在元胞沟槽槽底的正下方制备得到优化注入区;
步骤4、去除上述掩膜层,在上述第一主面上进行所需的热氧化工艺,以能在元胞沟槽的侧壁以及底壁制备得到绝缘栅氧化层,所述绝缘栅氧化层覆盖元胞沟槽的侧壁以及底壁;
步骤5、在上述元胞沟槽内填充得到栅极导电多晶硅,所述栅极导电多晶硅通过绝缘栅氧化层与元胞沟槽的侧壁以及底壁绝缘隔离;
步骤6、在上述第一主面上进行离子注入,以在第一导电类型外延层内得到第二导电类型阱层,所述第二导电类型阱层位于元胞沟槽槽底的上方,且能在第二导电类型阱层内制备得到第一导电类型源区,所述第一导电类型源区与邻近元胞沟槽外上方的侧壁接触;
步骤7、在上述第一主面上淀积得到绝缘介质层,所述绝缘介质层覆盖在第一主面上,且绝缘介质层覆盖元胞沟槽的槽口;
步骤8、制备所需的源极接触孔,所述源极接触孔贯通绝缘介质层;
步骤9、在绝缘介质层上设置金属层,所述金属层包括源极金属层,所述源极金属层覆盖在绝缘介质层上,并能填充在源极接触孔内,填充在源极接触孔内的源极金属层与第二导电类型阱层以及第一导电类型源区欧姆接触;
步骤10、在第二主面上制备得到漏极金属层,所述漏极金属层与第一导电类型衬底欧姆接触。
2.根据权利要求1所述的低导通电阻沟槽型功率半导体器件的制备方法,其特征是:所述半导体基板的材料包括硅。
3.根据权利要求1所述的低导通电阻沟槽型功率半导体器件的制备方法,其特征是:步骤3中,第一导电类型杂质离子注入时,注入的能量为25KEV~35KEV,剂量为9e11~1.7e12。
4.根据权利要求1所述的低导通电阻沟槽型功率半导体器件的制备方法,其特征是:步骤4中,在热氧化时,通过高温炉管工艺进行热氧化。
5.根据权利要求1所述的低导通电阻沟槽型功率半导体器件的制备方法,其特征是:所述绝缘介质层包括二氧化硅层。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110032713.6A CN112838010A (zh) | 2021-01-11 | 2021-01-11 | 低导通电阻沟槽型功率半导体器件的制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110032713.6A CN112838010A (zh) | 2021-01-11 | 2021-01-11 | 低导通电阻沟槽型功率半导体器件的制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112838010A true CN112838010A (zh) | 2021-05-25 |
Family
ID=75929552
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110032713.6A Pending CN112838010A (zh) | 2021-01-11 | 2021-01-11 | 低导通电阻沟槽型功率半导体器件的制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112838010A (zh) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262453B1 (en) * | 1998-04-24 | 2001-07-17 | Magepower Semiconductor Corp. | Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate |
EP1504473A1 (en) * | 2002-05-13 | 2005-02-09 | GENERAL SEMICONDUCTOR, Inc. | Trench dmos transistor structure |
US20070114599A1 (en) * | 2005-11-23 | 2007-05-24 | M-Mos Sdn. Bhd. | High density trench MOSFET with reduced on-resistance |
CN105633139A (zh) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | 具有载流子存储结构的igbt器件及其制造方法 |
CN107658343A (zh) * | 2017-10-31 | 2018-02-02 | 无锡新洁能股份有限公司 | 一种优化器件特性的半导体结构及其制造方法 |
CN111697080A (zh) * | 2020-07-21 | 2020-09-22 | 江苏长晶科技有限公司 | 半导体元胞单元、制造方法和半导体器件 |
CN111755525A (zh) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | 一种Trench MOS功率器件及制备方法 |
-
2021
- 2021-01-11 CN CN202110032713.6A patent/CN112838010A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262453B1 (en) * | 1998-04-24 | 2001-07-17 | Magepower Semiconductor Corp. | Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate |
EP1504473A1 (en) * | 2002-05-13 | 2005-02-09 | GENERAL SEMICONDUCTOR, Inc. | Trench dmos transistor structure |
US20070114599A1 (en) * | 2005-11-23 | 2007-05-24 | M-Mos Sdn. Bhd. | High density trench MOSFET with reduced on-resistance |
CN105633139A (zh) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | 具有载流子存储结构的igbt器件及其制造方法 |
CN107658343A (zh) * | 2017-10-31 | 2018-02-02 | 无锡新洁能股份有限公司 | 一种优化器件特性的半导体结构及其制造方法 |
CN111697080A (zh) * | 2020-07-21 | 2020-09-22 | 江苏长晶科技有限公司 | 半导体元胞单元、制造方法和半导体器件 |
CN111755525A (zh) * | 2020-07-24 | 2020-10-09 | 华羿微电子股份有限公司 | 一种Trench MOS功率器件及制备方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10211333B2 (en) | Scalable SGT structure with improved FOM | |
CN102623500B (zh) | 具有降低的导通电阻的沟槽型功率mosfet | |
TWI443826B (zh) | 具有整合蕭特基二極體(Schottky diode)之高密度溝槽場效電晶體及其製造方法 | |
US10861965B2 (en) | Power MOSFET with an integrated pseudo-Schottky diode in source contact trench | |
CN111509035B (zh) | 低成本高性能沟槽型功率半导体器件及其制备方法 | |
CN109524472B (zh) | 新型功率mosfet器件及其制备方法 | |
WO2022035839A1 (en) | Mosfet with distributed doped p-shield zones under trenches | |
CN112864249A (zh) | 低栅漏电荷的沟槽型功率半导体器件及其制备方法 | |
CN102945806A (zh) | 集成肖特基二极管的mos器件的制造方法 | |
CN115547838A (zh) | 金属氧化物半导体器件的制备方法及器件 | |
CN113838909B (zh) | 沟槽型原胞结构及制备方法 | |
CN112864250A (zh) | 改善栅漏电荷的沟槽型功率半导体器件及其制备方法 | |
CN110690272A (zh) | 一种结合屏蔽栅的sj mos器件结构及其制作方法 | |
CN113659009A (zh) | 体内异性掺杂的功率半导体器件及其制造方法 | |
CN110707155A (zh) | 能改善反向恢复特性的屏蔽栅mos结构及其制作方法 | |
CN101901751B (zh) | 半导体元件及其制造方法 | |
CN115020240B (zh) | 一种低压超结沟槽mos器件的制备方法及结构 | |
CN113555414B (zh) | 沟槽型碳化硅场效应晶体管及其制备方法 | |
CN211017082U (zh) | 一种超结型mosfet器件 | |
CN112838010A (zh) | 低导通电阻沟槽型功率半导体器件的制备方法 | |
CN110061049B (zh) | 一种低功耗屏蔽栅型半导体功率器件及其制备方法 | |
CN113410299B (zh) | 一种高耐压的n沟道LDMOS器件及其制备方法 | |
CN113659008A (zh) | 具有电场钳位层的匀场器件及其制造方法和应用 | |
CN107863386B (zh) | 集成tmbs结构的沟槽mos器件及其制造方法 | |
CN210379058U (zh) | 能改善反向恢复特性的屏蔽栅mos结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210525 |
|
RJ01 | Rejection of invention patent application after publication |