CN112054051A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN112054051A CN112054051A CN202010489639.6A CN202010489639A CN112054051A CN 112054051 A CN112054051 A CN 112054051A CN 202010489639 A CN202010489639 A CN 202010489639A CN 112054051 A CN112054051 A CN 112054051A
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Abstract
得到能够实现IGBT的损耗改善,并且抑制耐压下降的半导体装置。半导体装置(1)具有IGBT区域(16)以及MOSFET区域(17)。在MOSFET区域(17)形成的多个沟道掺杂P层(115)具有侧面与在IGBT区域(16)及MOSFET区域(17)之间形成的边界沟槽栅极(107e)接触的沟槽相邻沟道掺杂P层(115t)。沟槽相邻沟道掺杂P层(115t)的形成深度被设定得比边界沟槽栅极(107e)的形成深度深。在MOSFET区域(17),包含沟道掺杂P层(115)的沟道区域、层间氧化膜(110)的栅极绝缘膜及成为平面栅极的栅极多晶硅(121)而构成N型的平面构造的MOSFET。
Description
技术领域
本发明涉及包含IGBT区域及MOSFET区域而构成的半导体装置。
背景技术
在节能、装置的小型化这一市场背景下,为了实现这一需求,对于功率器件,要求比目前更为小型化。因此,在一部分的市场中通过应用将IGBT和二极管(Diode)一体化后的RC-IGBT(Reverse-conducting IGBT)而实现了小型化,目前谋求进一步的低损耗化、高性能化。例如在专利文献1中公开了RC-IGBT。
RC-IGBT作为内置有二极管的一体型IGBT,能够使功率器件小型化。因此,谋求器件的进一步小型化,谋求由RC-IGBT的下一代化、优化实现的特性改善的市场要求、期待高涨。在使RC-IGBT的总损耗降低时,与二极管部相比,IGBT部的损耗处于支配性地位的情况较多,RC-IGBT的二极管区域的面积被设计得比IGBT区域小。二极管区域的缩小会导致其电流密度的提高,但在能够满足热设计、可靠性的情况下,成为以IGBT侧的区域的确保为目的而优选提高二极管的电流密度的设计。
这里,担忧由于RC-IGBT的二极管部的设计的优化,二极管区域缩小,由此产生电流集中,二极管从接通切换至断开时的恢复动作时的破坏耐量不足。特别地,在以由该恢复特性的改善实现的高速化为目的,而进行了由重金属扩散、带电粒子束实现的寿命控制的情况下,存在以下问题,即,由于由该恢复的高速化引起的浪涌电压的产生,出现不得不进行二极管区域的扩大、大幅度的构造变更的情况。
此外,还开始出现以下问题,即,在以降低稳态损耗为目的而使晶片薄板化的情况下,二极管侧的耐压下降,与二极管侧的耐压下降相伴的SOA(Safe Operating Area)耐量显著下降。并且,处于以下状况,即,在IGBT侧,由于由其动作时的背面PN结引起的内建(built-in)电压,产生低电流时的稳态损耗,因此要求降低该损耗。
专利文献1:日本特开2013-201237号公报
在专利文献1中公开的这样的沟槽型RC-IGBT通过二极管部的构造变更,从而实现IGBT侧动作时的损耗改善,并且抑制由二极管部的电场集中引起的耐压下降。
就以往的RC-IGBT而言,二极管部形成于与IGBT部不同的区域,并且,基本上从降低损耗的观点、其制作容易度出发,大多以与IGBT相同的构造形成。即,以往的沟槽型RC-IGBT在二极管部也与IGBT部相同地,采用了形成沟槽构造的P层而由沟槽单元构造实现的PN结。
就RC-IGBT的二极管部而言,在采用沟槽单元构造的PN结的情况下,有效的N-衬底侧的厚度变薄,由此能够期待实现稳态损耗的改善。此外,二极管的稳态损耗意味着在二极管流过的接通状态下的电力损耗。
但是,以专利文献1为代表的RC-IGBT的二极管部的沟槽构造的P层存在以下问题。
(1)在沟槽构造的P层流过的电流没有作为IGBT侧的集电极电流而起作用、做贡献,因此无法实现IGBT部的损耗改善。
(2)由于沟槽构造的P层作为电场集中产生源而起作用,因此由于二极管部的电场集中而导致耐压下降。
发明内容
本发明就是为了解决上述问题(1)及(2)而提出的,其目的在于得到能够实现IGBT的损耗改善、并且抑制耐压下降的半导体装置。
本发明涉及的技术方案1所述的半导体装置,其包含在内部具有IGBT的IGBT区域和在内部具有MOSFET的MOSFET区域而构成,该半导体装置的特征在于,具有:半导体衬底,其具有第1及第2主面;以及第1导电型的漂移层,其设置于所述半导体衬底,所述IGBT区域包含:第2导电型的基极层,其设置于所述半导体衬底,在所述第1主面侧与所述漂移层相邻地配置;以及沟槽栅极,其隔着绝缘膜被埋入至从所述第1主面侧贯通所述基极层而到达所述漂移层的一部分的区域,所述MOSFET区域包含:第2导电型的含沟道区域,其设置于所述半导体衬底,选择性地设置于所述漂移层的上层部;以及第1导电型的MOS用电极区域,其选择性地设置于所述含沟道区域的上层部,未形成所述MOS用电极区域的所述含沟道区域的上层部的至少一部分被规定为沟道区域,所述MOS用电极区域还包含在所述沟道区域之上隔着栅极绝缘膜而设置的平面栅极,包含所述沟道区域、所述栅极绝缘膜及所述平面栅极而构成第1导电型的MOSFET,所述沟槽栅极包含在所述IGBT区域与所述MOSFET区域之间的边界处存在的边界沟槽栅极,所述含沟道区域包含侧面与所述边界沟槽栅极接触的沟槽栅极相邻区域,所述沟槽栅极相邻区域的形成深度比所述边界沟槽栅极的形成深度深。
发明的效果
就作为技术方案1所述的本发明的半导体装置而言,由于沟槽栅极相邻区域的形成深度比边界沟槽栅极的形成深度深,因此能够通过沟槽栅极相邻区域而缓和在边界沟槽栅极的底面端部的正下方产生的电场集中。
技术方案1所述的本发明包含沟道区域、栅极绝缘膜及平面栅极而构成第1导电型的MOSFET,因此平面栅极起到场板的作用,能够实现MOSFET区域的耐压提高。
另外,技术方案1所述的本发明在MOSFET区域,在MOSFET的非动作时,能够使由含沟道区域和漂移层实现的内置二极管起作用,因此能够作为RC-IGBT而进行动作。
并且,技术方案1所述的本发明在MOSFET区域具有MOSFET,因此能够实现低电流区域的IGBT动作时的电力损耗的改善。
附图说明
图1是表示半导体装置的构造的剖面图,该半导体装置是本发明的实施方式1。
图2是表示实施方式1的对比用的以往的半导体装置的构造的剖面图。
图3是表示实施方式1的半导体装置的输出特性的波形图。
图4是表示半导体装置的构造的剖面图,该半导体装置是本发明的实施方式2。
图5是表示半导体装置的构造的剖面图,该半导体装置是本发明的实施方式3的基本例。
图6是表示半导体装置的构造的剖面图,该半导体装置是本发明的实施方式3的变形例。
图7是表示半导体装置的构造的剖面图,该半导体装置是本发明的实施方式4的基本例。
图8是表示半导体装置的构造的剖面图,该半导体装置是本发明的实施方式4的变形例。
标号的说明
11发射极单元部,12边缘端接部,16IGBT区域,17、17B、17C1、17C2、17D1、17D2MOSFET区域,101硅衬底,102漂移层,103缓冲层,104集电极层,105集电极(collector)电极(electrode),106沟道掺杂P层,107沟槽栅极,107e边界沟槽栅极,108源极区域,109发射极铝电极,115、116沟道掺杂P层,115t、116t沟槽相邻沟道掺杂P层,124、129阳极P-哑层,125、126N型扩散层,127、128第2沟道掺杂P层。
具体实施方式
<前言>
以下,一边参照附图一边对实施方式1~实施方式4进行说明。由于附图是示意性地示出的,因此尺寸及位置的相互关系可以适当变更。在以下的说明中,对相同或相应的结构要素标注相同的标号,有时省略重复的说明。关于半导体的导电型,将第1导电型设为N型、将第2导电型设为P型而进行说明。但是,也可以使它们相反,将第1导电型设为P型,将第2导电型设为N型。N+型意味着与N型相比,施主杂质的浓度高,N-型意味着与N型相比,施主杂质的浓度低。同样地,P+型意味着与P型相比,受主杂质的浓度高,P-型意味着与P型相比,受主杂质的浓度低。
“MOS”这一用语,以前用于金属/氧化物/半导体的层叠构造,采用“Metal-Oxide-Semiconductor”的首字母。但是,特别地,就具有MOS构造的场效应晶体管(以下,简称为“MOSFET”)而言,从近年来的集成化、制造工艺的改善等观点来看,栅极绝缘膜、栅极电极的材料得到改善。
例如,就MOSFET而言,主要从自对准地形成源极-沟道掺杂层的观点出发,逐渐采用多晶硅代替金属作为栅极电极的材料。另外,从改善电气特性的观点出发,采用高介电常数的材料作为栅极绝缘膜的材料,但该材料并非必须限定于氧化物。
因此,“MOS”这一术语并非必须仅限定于在金属/氧化物/半导体的层叠构造中采用,在本说明书中也不以这样的限定为前提。即,鉴于技术常识,这里,“MOS”具有不仅作为起因于其语源的缩略语,而且还广泛地包含导电体/绝缘体/半导体的层叠构造的意义。
<实施方式1>
图1是表示半导体装置1的构造的剖面图,该半导体装置1是本发明的实施方式1。实施方式1的半导体装置1是RC-IGBT。在图1中标记有XYZ正交坐标系。在后面所示的图2、图4~图8中也标记有XYZ正交坐标系。
半导体装置1具有作为半导体衬底的硅衬底101。硅衬底101具有表面和背面,该表面是+Z方向侧的第1主面,该背面是与第1主面相对的-Z方向侧的第2主面。
硅衬底101具有发射极单元部11以及边缘端接部12,发射极单元部11被分类成IGBT区域16以及MOSFET区域17。在对半导体装置1进行俯视观察的情况下,在发射极单元部11的周围配置边缘端接部12。
就硅衬底101的整体而言,在硅衬底101设置第1导电型即N型的N型漂移层102以及N型缓冲层103。N型缓冲层103相对于N型漂移层102而设置于硅衬底101的背面侧。
在发射极单元部11的IGBT区域16以及边缘端接部12,在N型缓冲层103的背面侧设置P型集电极层104。
以下,对发射极单元部11的IGBT区域16进行说明。
在漂移层102的上层部设置第2导电型即P型的沟道掺杂P层106作为IGBT的基极层。
即,作为基极层的沟道掺杂P层106在硅衬底101的表面侧与漂移层102相邻地选择性地配置于IGBT区域16内。
在沟道掺杂P层106的上层部选择性地设置N+型源极区域108。
并且,在从硅衬底101的表面侧贯通源极区域108及沟道掺杂P层106而到达漂移层102的一部分的区域,隔着未图示的绝缘膜而埋入有沟槽栅极107。在图1、图2、图4~图8中未图示,但沟槽栅极107是隔着绝缘膜而埋入的栅极电极。
作为硅衬底101的背面构造,设置N型缓冲层103、P型集电极层104及集电极电极105。
缓冲层103设置于漂移层102的下表面,P型集电极层104设置于缓冲层103的下表面。并且,集电极电极105设置于集电极层104的下表面。
IGBT区域16从硅衬底101的表面到达至背面。与IGBT区域16相邻地设置MOSFET区域17。在图1所示的构造中,在2个IGBT区域16之间设置有MOSFET区域17。
接下来,对发射极单元部11的MOSFET区域17进行说明。
在漂移层102的上层部,选择性地设置彼此离散的多个沟道掺杂P层115。上述多个沟道掺杂P层115各自成为P型含沟道区域。
并且,在多个沟道掺杂P层115各自的上层部选择性地设置N+型源极区域108。在MOSFET区域17,源极区域108作为MOS用电极区域而起作用。IGBT区域16的源极区域108以及MOSFET区域17的源极区域108能够同时形成。
然后,在彼此相邻的一个沟道掺杂P层115与另一个沟道掺杂P层115之间,在未形成源极区域108的一个沟道掺杂P层115、未形成沟道掺杂P层115的漂移层102以及未形成源极区域108的另一个沟道掺杂P层115的上方隔着层间氧化膜110而选择性地设置栅极多晶硅121。
因此,未形成源极区域108的一个及另一个沟道掺杂P层115的上层部的一部分被规定为沟道区域,在上述沟道区域之上形成的层间氧化膜110作为栅极绝缘膜而起作用。
这样,在上述沟道区域之上隔着上述栅极绝缘膜而设置的栅极多晶硅121作为MOSFET的平面栅极而起作用。
即,除了上述沟道区域、上述栅极绝缘膜及栅极多晶硅121以外,还由未形成源极区域108及沟道掺杂P层115的漂移层102的上层部构成N型MOSFET。
此外,在IGBT区域16与MOSFET区域17的边界处设置有沟槽栅极107。以下,有时将在IGBT区域16与MOSFET区域17的边界处设置的沟槽栅极107称为“边界沟槽栅极107e”。
这样,在IGBT区域16设置的多个沟槽栅极107包含边界沟槽栅极107e。
另一方面,在多个沟道掺杂P层115之中,在IGBT区域16内,存在侧面与边界沟槽栅极107e接触的沟道掺杂P层115。以下,有时将多个沟道掺杂P层115中的侧面与边界沟槽栅极107e接触的沟道掺杂P层115称为“沟槽相邻沟道掺杂P层115t”。
这样,在MOSFET区域17设置的多个沟道掺杂P层115包含成为沟槽栅极相邻区域的沟槽相邻沟道掺杂P层115t。
而且,就实施方式1的半导体装置1而言,其特征在于,沟槽相邻沟道掺杂P层115t的形成深度比边界沟槽栅极107e的形成深度深。此外,在实施方式1中,多个沟道掺杂P层115全部以相同的深度而形成。
并且,MOSFET区域17通过沟道掺杂P层115与漂移层102之间的PN结而内置了二极管。因此,半导体装置1能够通过在IGBT区域16形成的IGBT和在MOSFET区域17形成的内置二极管,从而作为IGBT和二极管反向并联的RC-IGBT而进行动作。
作为硅衬底101的背面构造,形成有缓冲层103、也作为漏极而起作用的N型阴极层118、以及集电极电极105。
缓冲层103设置于漂移层102的下表面,N型阴极层118设置于缓冲层103的下表面。并且,集电极电极105设置于阴极层118的下表面。
接下来,对边缘端接部12进行说明。
在漂移层102的上层部选择性地设置外周P阱123,这些外周P阱123作为保护环而起作用。但是,边缘端接部12不限定于保护环,例如,也可以像VLD(Variation LateralDoping)构造那样,设为使一个P阱的浓度梯度发生了变化的构造。
并且,在漂移层102的上层部选择性地设置N+扩散层122,在N+扩散层122之上设置边缘端接-铝电极113。将该边缘端接-铝电极113设为与阴极层118同电位,漂移层102与边缘端接-铝电极113成为同电位,由此在将高电压施加于集电极电极105与发射极铝电极109之间时,不仅在漂移层102向纵向(-Z方向),而且也在漂移层102的边缘端接部12,耗尽层发生扩展、分担电压,由此使由边缘端接部12实现的耐压保持成为可能。
并且,在边缘端接部12,与IGBT区域16相同地,缓冲层103设置于漂移层102的下表面,集电极层104设置于缓冲层103的下表面。并且,集电极电极105设置于集电极层104的下表面。这里,作为一个例子,将边缘端接部12的硅衬底101的最下层设为集电极层104,但也可以从提高耐压等目的出发,设为与MOSFET区域17的硅衬底101的最下层相同的阴极层118。
因此,漂移层102、缓冲层103以及集电极电极105由IGBT区域16、MOSFET区域17以及边缘端接部12共用。集电极层104由IGBT区域16以及边缘端接部12共用。另外,阴极层118是为了MOSFET区域17而设置的。
这样,硅衬底101具有边缘端接部12和被分类成IGBT区域16以及MOSFET区域17的发射极单元部11。
在该硅衬底101的表面之上选择性地形成层间氧化膜110。层间氧化膜110以从IGBT区域16的沟槽栅极107的表面将源极区域108的一部分覆盖的方式设置。并且,层间氧化膜110以将MOSFET区域17的栅极多晶硅121的表面、背面以及侧面覆盖的方式设置,层间氧化膜110设置于漂移层102之上、沟道掺杂P层115的一部分之上以及N+型源极区域108的一部分之上。
并且,层间氧化膜110形成于边缘端接部12的外周P阱123的表面的一部分、N+扩散层122的表面的一部分以及漂移层102的表面的一部分之上,以外周P阱123以及N+扩散层122的表面的一部分露出的方式设置。
发射极铝电极109在IGBT区域16及MOSFET区域17隔着层间氧化膜110而设置于硅衬底101之上的整个面,在边缘端接部12的外周P阱123的一部分之上延伸。
发射极铝电极109与IGBT区域16的源极区域108的表面的一部分接触地设置。因此,在IGBT区域16,发射极铝电极109与源极区域108电连接。
发射极铝电极109以与MOSFET区域17的MOS用电极区域即源极区域108的表面的一部分接触的方式设置。因此,在IGBT区域16,发射极铝电极109与源极区域108电连接。
发射极铝电极109在边缘端接部12隔着层间氧化膜110而选择性地设置在硅衬底101之上。
发射极铝电极109与边缘端接部12的外周P阱123的表面的一部分接触地设置。因此,在边缘端接部12,发射极铝电极109与外周P阱123的一部分电连接。
边缘端接-铝电极113在边缘端接部12隔着层间氧化膜110而选择性地设置在硅衬底101之上。
边缘端接-铝电极113与边缘端接部12的N+扩散层122的表面的一部分接触地设置。因此,在边缘端接部12,边缘端接-铝电极113与N+扩散层122电连接。
在边缘端接部12,在包含发射极铝电极109及层间氧化膜110的整个面设置边缘端接-绝缘膜114。
在IGBT区域16,构成以上述发射极铝电极109、源极区域108、沟道掺杂P层106、漂移层102、缓冲层103、集电极层104、集电极电极105、沟槽栅极107为主要结构要素的IGBT。
以下,对IGBT接通时的动作进行说明。IGBT是通过电子载流子及空穴载流子而进行动作的双极元件,在IGBT接通时,包含沟道掺杂P层106、源极区域108以及沟槽栅极107的N型沟槽MOS栅极构造成为导通状态。此外,如前所述,在沟槽栅极107的周围形成有未图示的绝缘膜,该绝缘膜的一部分作为沟槽MOS栅极构造的栅极绝缘膜而起作用。
并且,在IGBT区域16内,电流以集电极层104、缓冲层103、漂移层102、沟道掺杂P层106、源极区域108的路径而流动。
如上所述,在IGBT区域16形成有多个由沟道掺杂P层106、源极区域108及沟槽栅极107构成的沟槽MOS栅极构造。
就这样的构造而言,IGBT通过对沟槽栅极107施加正电压,在沟道掺杂P层106的一部分形成N型沟道区域,并且对集电极电极105施加正电压而进行动作。
IGBT通过在动作时使电子载流子及空穴载流子在漂移层102积蓄,引起导电率调制而使接通电阻降低。为了降低IGBT的接通电压,需要提高载流子的积蓄效果。
接下来,对在MOSFET区域17形成的平面栅极构造的MOSFET接通时的动作进行说明。MOSFET具有以沟道掺杂P层115、源极区域108、层间氧化膜110的一部分即栅极绝缘膜、栅极多晶硅121及漂移层102为主要结构要素的平面构造的N型MOS栅极构造。
在MOSFET区域17内,电子载流子从发射极铝电极109经由源极区域108、沟道掺杂P层115的N型沟道区域、漂移层102、缓冲层103以及阴极层118而流动至集电极电极105。
另外,MOSFET具有由沟道掺杂P层115及漂移层102构成的内置二极管。因此,在对栅极多晶硅121施加了零电压或负电压的状态下,如果对发射极铝电极109施加正电压,则从沟道掺杂P层106向漂移层102注入空穴载流子,从阴极层118向漂移层102注入电子载流子。
然后,如果施加电压变得大于或等于内置二极管的内建电压,则内置二极管成为接通状态。这里,施加电压意味着将发射极侧设为+的施加于发射极铝电极109、集电极电极105之间的电压。这样,在MOSFET区域17,当不对平面栅极即栅极多晶硅121施加在正下方的沟道掺杂P层115形成沟道的程度的正电压的情况下,能够使上述内置二极管有效地动作。
在MOSFET区域17,如果内置二极管成为接通状态,则电流以发射极铝电极109、沟道掺杂P层115、漂移层102、缓冲层103、阴极层118以及集电极电极105的路径而流动。
如上所述,就实施方式1的半导体装置1而言,沟槽相邻沟道掺杂P层115t的形成深度被设定得比边界沟槽栅极107e的形成深度深。
因此,半导体装置1能够通过沟槽相邻沟道掺杂P层115t而缓和在边界沟槽栅极107e的底面端部的正下方产生的电场集中。
这是因为能够通过沟槽相邻沟道掺杂P层115t而将沟槽栅极107的底面端部的一部分覆盖。
此外,也想到使沟槽相邻沟道掺杂P层115t的形成深度与在边缘端接部12设置的外周P阱123的形成深度相同的变形例。在该变形例中,由于能够同时形成外周P阱123和沟道掺杂P层115,因此具有能够简化包含照相制版处理以及成为掺杂剂的杂质的注入工序在内的一系列的制造工艺的优点。
半导体装置1由于包含上述沟道掺杂P层115的沟道区域、层间氧化膜110的栅极绝缘膜以及成为平面栅极的栅极多晶硅121而构成N型的平面构造的MOSFET,因此主要在平面构造的MOSFET的非动作时,栅极多晶硅121起到场板的作用,能够实现MOSFET区域17的耐压提高。此外,MOSFET的非动作时相当于断开状态、通断过渡期的一部分期间。
即,就实施方式1的半导体装置1而言,针对在彼此相邻的沟道掺杂P层115、115之间的沟道掺杂P层115的热扩散所形成的曲线状的扩散部界面处容易产生的电场集中,追加了包含层间氧化膜110的栅极绝缘膜及栅极多晶硅121的平面MOS栅极构造。因此,栅极多晶硅121如上所述起到场板的作用,相应地能够实现MOSFET区域17的耐压提高。
另外,半导体装置1在MOSFET区域17,在MOSFET的非动作时,能够使由含沟道区域即沟道掺杂P层115和漂移层102构成的内置二极管起作用,因此能够作为RC-IGBT而进行动作。
并且,半导体装置1在MOSFET区域17具有MOSFET,因此能够实现低电流区域的IGBT动作时的电力损耗的改善。
以下,对这一点详细叙述。图2是表示实施方式1的对比用的以往的半导体装置9的构造的剖面图。图3是表示实施方式1的半导体装置1的输出特性的波形图。
如图2所示,出于简化制造工序等理由,在IGBT区域16及二极管区域26共通地形成有沟道掺杂P层106及沟槽栅极107。然后,在二极管区域26,由沟道掺杂P层106和漂移层102构成二极管。因此,在二极管区域26不存在MOSFET。
因此,就图2所示的以往的半导体装置9而言,在集电极电压Vc较低的低电流区域,IGBT不动作,因此如图3的输出波形L3所示的那样,不流过集电极电流Ic。
另一方面,实施方式1的半导体装置1如图3的输出波形L1所示的那样,与MOSFET的输出波形L2相同地,在上述低电流区域也流过集电极电流Ic。
然后,实施方式1的半导体装置1如图3的输出波形L1所示的那样,与IGBT的输出波形L3相同地,流过集电极电压Vc较高的高电流区域的集电极电流Ic。
这样,实施方式1的半导体装置1的输出波形L1如图3所示,在低电流区域与MOSFET的输出波形L2一致,在高电流区域与IGBT的输出波形L3一致。
并且,就实施方式1的半导体装置1而言,在MOSFET区域17,彼此分离地形成多个沟道掺杂P层115,由此如果进行最佳设计,则能够实质上扩展漂移层102侧的区域。即,能够以不存在沟道掺杂P层115的区域的量而使成为漂移层102的区域的体积扩展,能够实现MOSFET区域17的耐压提高。
特别是近年来,使硅衬底101变薄,即,使漂移层102变薄而实现了以IGBT为首的功率器件元件的电力损耗的降低,但相反地,耐压下降成为问题。因此,通过分离形成MOSFET区域17的多个沟道掺杂P层115,从而能抑制由电场集中引起的耐压下降。
此外,作为与形成深度较深的沟道掺杂P层115的形成相对的矛盾,设想到内置二极管动作时的特性即恢复损耗的增加。作为该恢复损耗的对策,想到由重金属扩散、带电粒子束实现的现存的寿命控制,通过适当地进行该寿命控制,从而能够抑制恢复损耗的恶化。
<实施方式2>
图4是表示半导体装置2的构造的剖面图,该半导体装置2是本发明的实施方式2。实施方式2的半导体装置2与实施方式1相同,是RC-IGBT。
以下,以实施方式2的半导体装置2的特征为中心进行说明,关于与实施方式1相同的构造以及动作,标注相同标号而适当省略说明。
半导体装置2具有被分类成IGBT区域16以及MOSFET区域17B的发射极单元部11。
就MOSFET区域17B而言,在多个含沟道区域即多个沟道掺杂P层115之间的漂移层102的上层部,彼此离散地设置多个N型扩散层125。多个N型扩散层125成为至少一个上层扩散区域。即,在彼此离散地设置的多个沟道掺杂P层115中的彼此相邻的一对沟道掺杂P层115之间设置1个N型扩散层125。
在MOSFET区域17B,除了沟道掺杂P层115的一部分的沟道区域、层间氧化膜110的一部分的栅极绝缘膜以及栅极多晶硅121以外,还由源极区域108以及N型扩散层125构成N型MOSFET。此外,上述沟道区域及上述栅极绝缘膜与实施方式1的半导体装置1相同。
上述结构的实施方式2的半导体装置2与实施方式1的半导体装置1相同地,由于具有沟槽相邻沟道掺杂P层115t,因此取得与实施方式1相同的效果。
并且,实施方式2的半导体装置2的多个N型扩散层125具有以下的特征(1)以及特征(2)。
(1)多个N型扩散层125与漂移层102相比,N型杂质浓度设定得高。
(2)多个N型扩散层125的形成深度比多个含沟道区域即多个沟道掺杂P层115的形成深度浅。
实施方式2具有上述特征(1),由此在MOSFET区域17B内,能够使彼此相邻的沟道掺杂P层115、115之间的J-FET电阻下降,实现MOSFET的接通状态的低电阻化。
并且,实施方式2的半导体装置2通过上述特征(1)而实现MOSFET的接通状态的低电阻化,相应地,就多个沟道掺杂P层115而言,能够缩小相邻的沟道掺杂P层115、115之间的距离而提高耐压。
因此,实施方式2的半导体装置2与实施方式1相比,MOSFET区域17B的接通电阻与耐压之间的折衷关系本身有改善倾向,因此在实施方式2中,能够以相同耐压来设计更低的接通电阻的MOSFET区域17B。
其结果,MOSFET区域17B具有内置二极管,并且能够使MOSFET的有效区域比实施方式1宽。
此外,实施方式2的半导体装置2具有上述特征(2),由此能够将多个N型扩散层125的形成区域抑制为所需的最小限度,抑制由N型扩散层125引起的MOSFET区域17B的耐压下降。
<实施方式3>
(基本例)
图5是表示半导体装置3A的构造的剖面图,该半导体装置3A是本发明的实施方式3的基本例。实施方式3的半导体装置3A与实施方式1相同,是RC-IGBT。
以下,以实施方式3的半导体装置3A的特征为中心进行说明,关于与实施方式1相同的构造以及动作,标注相同标号而适当省略说明。
半导体装置3A具有被分类成IGBT区域16以及MOSFET区域17C1的发射极单元部11。以下,对MOSFET区域17C1的构造进行说明。
在漂移层102的上层部,彼此离散地选择性地设置多个沟道掺杂P层116。在漂移层102的上层部,选择性地设置彼此分离的多个第2沟道掺杂P层127。
然后,多个第2沟道掺杂P层127的P型杂质浓度被设定得比沟道掺杂P层116的杂质浓度低,多个第2沟道掺杂P层127的形成深度比多个沟道掺杂P层116的形成深度浅。
多个沟道掺杂P层116及多个第2沟道掺杂P层127被1对1地设置,对应的沟道掺杂P层116及第2沟道掺杂P层127以侧面接触的方式一体地构成组合沟道掺杂P层。上述多个组合沟道掺杂P层成为彼此离散地设置的含沟道区域。
即,多个沟道掺杂P层116各自成为第1部分扩散区域,多个第2沟道掺杂P层127各自成为第2部分扩散区域,通过第1及第2部分扩散区域的组合而构成含沟道区域。
因此,作为实施方式3的基本例的半导体装置3A在硅衬底101的上层部选择性地设置上述多个组合沟道掺杂P层。
并且,在多个组合沟道掺杂P层各自的上层部选择性地设置MOS用电极区域即N型源极区域108。具体地说,从沟道掺杂P层116的上层部至第2沟道掺杂P层127的上层部而形成源极区域108。
并且,在多个含沟道区域即多个组合沟道掺杂P层之间的漂移层102的上层部设置多个N型扩散层126。多个N型扩散层126成为至少一个上层扩散区域。
此外,N型扩散层126的形成深度比第2沟道掺杂P层127的形成深度深,比沟道掺杂P层116的形成深度浅。具体地说,在N型扩散层126的上层部选择性地形成有一对第2沟道掺杂P层127,N型扩散层126是从第2沟道掺杂P层127、127之间的区域延伸至第2沟道掺杂P层127、127下方的区域而形成的。
在MOSFET区域17C1,除了第2沟道掺杂P层127的一部分的沟道区域、层间氧化膜110的一部分的栅极绝缘膜及栅极多晶硅121以外,还由源极区域108及N型扩散层126构成N型MOSFET。此外,上述沟道区域是栅极多晶硅121的下方的未形成源极区域108的第2沟道掺杂P层127的上层区域。另外,上述栅极绝缘膜与实施方式1的半导体装置1相同。
另一方面,多个沟道掺杂P层116包含在IGBT区域16内侧面与边界沟槽栅极107e接触的沟道掺杂P层116。以下,有时将侧面与边界沟槽栅极107e接触的沟道掺杂P层116称为“沟槽相邻沟道掺杂P层116t”。
这样,在MOSFET区域17C1设置的多个沟道掺杂P层116包含成为沟槽栅极相邻区域的沟槽相邻沟道掺杂P层116t。即,多个第1部分扩散区域包含沟槽栅极相邻区域。
而且,就作为实施方式3的基本例的半导体装置3A而言,其特征在于,沟槽相邻沟道掺杂P层116t的形成深度比边界沟槽栅极107e的形成深度深。
并且,MOSFET区域17C1主要通过沟道掺杂P层116与漂移层102之间的PN结而内置了二极管。因此,半导体装置3A能够通过在IGBT区域16形成的IGBT和在MOSFET区域17C1形成的内置二极管,从而作为IGBT和二极管反向并联的RC-IGBT而进行动作。
就上述结构的作为实施方式3的基本例的半导体装置3A而言,该半导体装置3A的多个沟道掺杂P层116具有与实施方式1的半导体装置1的沟槽相邻沟道掺杂P层115t相当的沟槽相邻沟道掺杂P层116t,因此取得与实施方式1相同的效果。
此外,半导体装置3A的N型扩散层126具有与实施方式2的半导体装置2的N型扩散层125的上述特征(1)以及特征(2)相同的特征,因此取得与实施方式2相同的效果。
并且,就作为实施方式3的基本例的半导体装置3A而言,多个沟道掺杂P层116及多个第2沟道掺杂P层127具有以下特征(3)。
(3)第2沟道掺杂P层127以侧面与沟道掺杂P层116接触的方式形成,第2沟道掺杂P层127的形成深度比沟道掺杂P层116的形成深度浅。
实施方式3的半导体装置3A具有上述特征(3),由于第2部分扩散区域即第2沟道掺杂P层127的存在,能够缓和对应的第1部分扩散区域即沟道掺杂P层116的热扩散所形成的曲线状的扩散部界面处的电场集中。
以下,对这一点进行说明。容易产生由沟道掺杂P层116的热扩散所形成的曲线状的扩散部界面引起的电场集中。因此,通过将比沟道掺杂P层116浅的第2沟道掺杂P层127与沟道掺杂P层116相邻配置,从而能够缓和上述电场集中。
(变形例)
图6是表示半导体装置3B的构造的剖面图,该半导体装置3B是本发明的实施方式3的变形例。实施方式3的半导体装置3B与实施方式1相同,是RC-IGBT。
以下,以实施方式3的半导体装置3B的特征为中心进行说明,关于与实施方式1相同的构造以及动作,标注相同标号而适当省略说明。
半导体装置3B具有被分类成IGBT区域16及MOSFET区域17C2的发射极单元部11。以下,对MOSFET区域17C2的构造进行说明。
在漂移层102的上层部选择性地设置彼此分离的多个沟道掺杂P层116。在漂移层102的上层部选择性地设置彼此分离的多个第2沟道掺杂P层128。
多个沟道掺杂P层116及多个第2沟道掺杂P层128之间的关系和图5所示的半导体装置3A的沟道掺杂P层116与第2沟道掺杂P层127之间的关系相同,由对应的沟道掺杂P层116和第2沟道掺杂P层128构成组合沟道掺杂P层。
因此,作为实施方式3的变形例的半导体装置3B与半导体装置3A相同,在硅衬底101的上层部选择性地设置多个组合沟道掺杂P层。
并且,半导体装置3B与半导体装置3A相同,在多个组合沟道掺杂P层各自的上层部选择性地设置MOS用电极区域即N型源极区域108。
此外,作为实施方式3的变形例的半导体装置3B在不具有与基本例的半导体装置3A的N型扩散层126相当的层这一点上不同。
在MOSFET区域17C2,除了第2沟道掺杂P层128的一部分的沟道区域、层间氧化膜110的一部分的栅极绝缘膜以及栅极多晶硅121以外,还由未形成源极区域108以及组合沟道掺杂P层的漂移层102的上层部构成N型MOSFET。此外,上述沟道区域是栅极多晶硅121下方的未形成源极区域108的第2沟道掺杂P层128的上层区域。另外,上述栅极绝缘膜与实施方式1的半导体装置1相同。
在MOSFET区域17C2,也与MOSFET区域17C1相同,多个沟道掺杂P层116包含成为沟槽栅极相邻区域的沟槽相邻沟道掺杂P层116t。
而且,半导体装置3B与半导体装置3A相同地,其特征在于,沟槽相邻沟道掺杂P层116t的形成深度比边界沟槽栅极107e的形成深度深。
并且,MOSFET区域17C2主要通过沟道掺杂P层116与漂移层102之间的PN结而内置了二极管。因此,半导体装置3B能够通过在IGBT区域16形成的IGBT和在MOSFET区域17C2形成的内置二极管,从而作为IGBT和二极管反向并联的RC-IGBT而进行动作。
就上述结构的作为实施方式3的变形例的半导体装置3B而言,该半导体装置3B的沟道掺杂P层116具有与实施方式1的半导体装置1的沟槽相邻沟道掺杂P层115t相当的沟槽相邻沟道掺杂P层116t,因此取得与实施方式1相同的效果。
并且,就作为实施方式3的变形例的半导体装置3B而言,多个沟道掺杂P层116及多个第2沟道掺杂P层128与半导体装置3A相同,具有以下特征(3B)。
(3B)第2沟道掺杂P层128以侧面与沟道掺杂P层116接触的方式形成,第2沟道掺杂P层128的形成深度比沟道掺杂P层116的形成深度浅。
实施方式3的半导体装置3B具有上述特征(3B),与半导体装置3A相同,由于第2部分扩散区域即第2沟道掺杂P层128的存在,能够缓和沟道掺杂P层116的热扩散所形成的曲线状的扩散部界面处的电场集中。
<实施方式4>
(基本例)
图7是表示半导体装置4A的构造的剖面图,该半导体装置4A是本发明的实施方式4的基本例。实施方式4的半导体装置4A与实施方式1相同,是RC-IGBT。
以下,以实施方式4的半导体装置4A的特征为中心进行说明,关于与实施方式1相同的构造以及动作,标注相同标号而适当省略说明。
半导体装置4A具有被分类成IGBT区域16及MOSFET区域17D1的发射极单元部11。
在MOSFET区域17D1,在彼此离散地设置的多个含沟道区域即多个沟道掺杂P层115之间的漂移层102的上层部,以不与沟道掺杂P层115、115各自接触的方式选择性地设置多个阳极P-哑层124。即,在多个沟道掺杂P层115中的相邻的一对沟道掺杂P层115、115之间,以不与沟道掺杂P层115、115接触的方式设置1个阳极P-哑层124。
多个阳极P-哑层124各自的表面与硅衬底101的表面一致。多个阳极P-哑层124成为至少一个上层哑区域,被设定为电浮置。
在MOSFET区域17D1,除了沟道掺杂P层115的一部分的沟道区域、层间氧化膜110的一部分的栅极绝缘膜以及栅极多晶硅121以外,还由源极区域108、以及未形成沟道掺杂P层115以及阳极P-哑层124的漂移层102的上层部构成N型MOSFET。此外,上述沟道区域及上述栅极绝缘膜与实施方式1的半导体装置1相同。
上述结构的实施方式4的基本例的半导体装置4A与实施方式1的半导体装置1相同地具有沟槽相邻沟道掺杂P层115t,因此取得与实施方式1相同的效果。
并且,就作为实施方式4的基本例的半导体装置4A而言,半导体装置4A的多个阳极P-哑层124具有以下特征(4)。
(4)多个阳极P-哑层124在沟道掺杂P层115、115之间的漂移层102的上层部以不与沟道掺杂P层115接触的方式设置,被设定为电浮置。
实施方式4的基本例具有上述特征(4),由于上层哑区域即阳极P-哑层124的存在,能够缓和沟道掺杂P层115的热扩散所形成的曲线状的扩散部界面处的电场集中。
(变形例)
图8是表示半导体装置4B的构造的剖面图,该半导体装置4B是本发明的实施方式4的变形例。实施方式4的半导体装置4B与实施方式1相同,是RC-IGBT。
以下,以实施方式4的半导体装置4B的特征为中心进行说明,关于与实施方式1相同的构造以及动作,标注相同标号而适当省略说明。
半导体装置4B具有被分类成IGBT区域16及MOSFET区域17D2的发射极单元部11。
就MOSFET区域17D2而言,在彼此离散地设置的多个含沟道区域即多个沟道掺杂P层115之间的漂移层102的上层部,以不与沟道掺杂P层115、115各自接触的方式选择性地设置多个阳极P-哑层129。即,在多个沟道掺杂P层115中的相邻的一对沟道掺杂P层115、115之间,以不与沟道掺杂P层115、115接触的方式设置1个阳极P-哑层129。
多个阳极P-哑层129以将硅衬底101的第1主面即表面作为基准,多个阳极P-哑层129的表面位于并非“0”的有意义的埋入深度处的方式形成于漂移层102的内部。多个阳极P-哑层129成为至少一个上层哑区域,被设定为电浮置。
在MOSFET区域17D2,除了沟道掺杂P层115的一部分的沟道区域、层间氧化膜110的一部分的栅极绝缘膜及栅极多晶硅121以外,还由源极区域108、以及未形成沟道掺杂P层115及阳极P-哑层129的漂移层102的上层部构成N型MOSFET。此外,上述沟道区域及上述栅极绝缘膜与实施方式1的半导体装置1相同。
上述结构的实施方式4的变形例的半导体装置4B与实施方式1的半导体装置1相同地具有沟槽相邻沟道掺杂P层115t,因此取得与实施方式1相同的效果。
并且,就作为实施方式4的变形例的半导体装置4B而言,半导体装置4B的多个阳极P-哑层129与基本例的半导体装置4A的阳极P-哑层124相同,具有以下的特征(4B)。
(4B)多个阳极P-哑层129在沟道掺杂P层115、115之间的漂移层102的上层部以不与沟道掺杂P层115接触的方式设置,被设定为电浮置。
实施方式4的变形例具有上述特征(4B),由于上层哑区域即阳极P-哑层129的存在,能够缓和沟道掺杂P层115的热扩散所形成的曲线状的扩散部界面处的电场集中。
并且,阳极P-哑层129还具有以下特征(5)。
(5)阳极P-哑层129以将硅衬底101的表面作为基准,阳极P-哑层129的表面位于埋入深度处的方式形成于漂移层102的内部。
由于作为实施方式4的变形例的半导体装置4B具有上述特征(5),因此漂移层102在比上述埋入深度浅的上层部,具有在平面栅极即栅极多晶硅121的下方设置的栅极下区域。在该栅极下区域不存在阳极P-哑层129。
因此,半导体装置4B能够在漂移层102的上述栅极下区域形成将第1导电型即N型模拟地高浓度化后的积蓄层,因此能够实现MOSFET的低电阻化。
此外,本发明能够在该发明的范围内对各实施方式自由地进行组合,或者对各实施方式适当地进行变形、省略。
Claims (6)
1.一种半导体装置,其包含在内部具有IGBT的IGBT区域和在内部具有MOSFET的MOSFET区域而构成,
该半导体装置的特征在于,具有:
半导体衬底,其具有第1及第2主面;以及
第1导电型的漂移层,其设置于所述半导体衬底,
所述IGBT区域包含:
第2导电型的基极层,其设置于所述半导体衬底,在所述第1主面侧与所述漂移层相邻地配置;以及
沟槽栅极,其隔着绝缘膜被埋入至从所述第1主面侧贯通所述基极层而到达所述漂移层的一部分的区域,
所述MOSFET区域包含:
第2导电型的含沟道区域,其设置于所述半导体衬底,选择性地设置于所述漂移层的上层部;以及
第1导电型的MOS用电极区域,其选择性地设置于所述含沟道区域的上层部,未形成所述MOS用电极区域的所述含沟道区域的上层部的至少一部分被规定为沟道区域,
所述MOS用电极区域还包含在所述沟道区域之上隔着栅极绝缘膜而设置的平面栅极,
包含所述沟道区域、所述栅极绝缘膜及所述平面栅极而构成第1导电型的MOSFET,
所述沟槽栅极包含在所述IGBT区域与所述MOSFET区域之间的边界处存在的边界沟槽栅极,
所述含沟道区域包含侧面与所述边界沟槽栅极接触的沟槽栅极相邻区域,
所述沟槽栅极相邻区域的形成深度比所述边界沟槽栅极的形成深度深。
2.根据权利要求1所述的半导体装置,其特征在于,
所述含沟道区域包含彼此离散地设置的多个含沟道区域,
所述MOSFET区域还具有在所述多个含沟道区域之间的所述漂移层的上层部设置的第1导电型的至少一个上层扩散区域,
除了所述沟道区域、所述栅极绝缘膜以及所述平面栅极以外,还包含所述MOS用电极区域及所述至少一个上层扩散区域而构成所述MOSFET,
所述至少一个上层扩散区域与所述漂移层相比,第1导电型的杂质浓度高,
所述至少一个上层扩散区域的形成深度比所述多个含沟道区域的形成深度浅。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述含沟道区域包含第2导电型的第1部分扩散区域和第2导电型的第2部分扩散区域,该第2导电型的第2部分扩散区域以侧面与所述第1部分扩散区域接触的方式设置,所述第1部分扩散区域包含所述沟槽栅极相邻区域,
未形成所述MOS用电极区域的所述第2部分扩散区域的上层部被规定为所述沟道区域,
所述第2部分扩散区域的形成深度比所述第1部分扩散区域的形成深度浅。
4.根据权利要求2所述的半导体装置,其特征在于,
所述多个含沟道区域包含多个第1及第2部分扩散区域,所述多个第1及第2部分扩散区域中的对应的第1及第2部分扩散区域以侧面接触的方式一体地构成所述含沟道区域,
所述多个第1部分扩散区域包含所述沟槽栅极相邻区域,
所述多个第2部分扩散区域的形成深度比所述至少一个上层扩散区域的形成深度浅。
5.根据权利要求1所述的半导体装置,其特征在于,
所述含沟道区域包含彼此离散的多个含沟道区域,
所述MOSFET区域还具有在所述多个含沟道区域之间的所述漂移层的上层部以不与所述多个含沟道区域接触的方式设置的第1导电型的至少一个上层哑区域,
所述至少一个上层哑区域被设定为电浮置。
6.根据权利要求5所述的半导体装置,其特征在于,
所述至少一个上层哑区域以使得其表面位于将所述半导体衬底的所述第1主面作为基准的埋入深度的方式形成于所述漂移层的内部,
所述漂移层具有在其上方存在平面栅极的栅极下区域。
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CN103548132A (zh) * | 2011-06-30 | 2014-01-29 | 富士电机株式会社 | 半导体器件的制造方法 |
US20150349110A1 (en) * | 2014-05-30 | 2015-12-03 | Texas Instruments Incorporated | Mosfet having dual-gate cells with an integrated channel diode |
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WO2024037274A1 (zh) * | 2022-08-15 | 2024-02-22 | 重庆万国半导体科技有限公司 | 一种具有反向导通特性的igbt器件及其制备方法 |
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US20200388608A1 (en) | 2020-12-10 |
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US11251177B2 (en) | 2022-02-15 |
CN112054051B (zh) | 2024-06-04 |
JP7118033B2 (ja) | 2022-08-15 |
JP2020202224A (ja) | 2020-12-17 |
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