CN111707852A - Method, device, equipment and storage medium for synchronizing signals of multi-channel waveform generator - Google Patents
Method, device, equipment and storage medium for synchronizing signals of multi-channel waveform generator Download PDFInfo
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Abstract
The invention discloses a signal synchronization method of a multi-channel waveform generator, which comprises the steps of collecting rising edge data of first waveform signals output by DAC channels; comparing the rising edge data of each first waveform signal, and determining a reference DAC channel which outputs the slowest waveform signal; determining a first offset digit of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel; and controlling the waveform signals output by the DAC channels to be output in a delayed mode according to the corresponding first offset digit. According to the method and the device, the signals output by each channel are subjected to time delay modulation according to the time difference of the rising edge data corresponding to each channel, and the multichannel synchronous output waveform signals of the waveform generator are ensured. The application also provides a signal synchronization device, equipment and a computer readable storage medium of the multichannel waveform generator, which have the beneficial effects.
Description
Technical Field
The present invention relates to the field of waveform generators, and in particular, to a signal synchronization method, apparatus, device, and computer readable storage medium for a multi-channel waveform generator.
Background
A waveform generator is a device that can provide electrical signals of various frequencies, waveforms and output levels. The device is used as a signal source or an excitation source for testing when measuring amplitude characteristics, frequency characteristics, transmission characteristics and other electrical parameters of various telecommunication systems or telecommunication equipment and when measuring characteristics and parameters of components.
Waveform generators, also known as signal sources or oscillators, are widely used in production practice and in the field of science and technology. The various wave curves are expressed by trigonometric functions. A circuit capable of generating various waveforms such as a triangular wave, a sawtooth wave, a rectangular wave (including a square wave), and a sine wave is called a functional waveform generator.
With the development of the waveform generator technology, the synchronization requirement of the multi-channel waveform generator is higher and higher, for example, in a quantum computing measurement and control system, tens of channels of the waveform generator are required to synchronously output signals to realize tens of or even hundreds of quantum bit synchronous control, and the requirement on signal synchronous control is high.
Disclosure of Invention
The invention aims to provide a signal synchronization method, a signal synchronization device, signal synchronization equipment and a computer readable storage medium of a multi-channel waveform generator, which improve the synchronism of a plurality of waveform signals output by the multi-channel waveform generator at the same time and meet the application requirement of the waveform generator on high synchronism requirement.
To solve the above technical problem, the present invention provides a signal synchronization method for a multi-channel waveform generator, comprising:
when each DAC channel of the AWG board card receives a channel synchronization instruction, acquiring rising edge data of a first waveform signal output by each DAC channel;
comparing the rising edge data of each first waveform signal, and determining a reference DAC channel which outputs the slowest waveform signal;
determining a first offset bit number of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel;
and controlling the waveform signals output by the DAC channels to be output in a delayed manner according to the corresponding first offset digit so as to enable the DAC channels of the AWG board card to synchronously output the waveform signals.
In an optional embodiment of the present application, after the outputting the waveform signal synchronously by each DAC channel of the AWG card, the method further comprises:
when each AWG board card in the same PXIE case receives a board card synchronization instruction, acquiring a second waveform signal output by any DAC channel in each AWG board card;
determining a reference AWG board card which outputs the slowest second waveform signal according to the rising edge data of the second waveform signal corresponding to each AWG board card;
determining a second offset digit of each AWG board card according to the time length of the time delay of the second waveform signal of the reference AWG board card relative to the second waveform signal of each AWG board card;
and controlling the waveform signals output by the AWG board card to be output in a delayed manner according to the corresponding second offset digit so as to enable each DAC channel of each AWG board card of the PXIE case to synchronously output the waveform signals.
In an optional embodiment of the present application, after the synchronously outputting the waveform signal by each DAC channel of each AWG card of the PXIE chassis, the method further includes:
when a plurality of PXIE boxes receive a box synchronization command, acquiring a third waveform signal output by any DAC channel in any AWG board card in each PXIE box;
determining a reference PXIE case which outputs the slowest third waveform signal according to rising edge data of the third waveform signal corresponding to each PXIE case;
determining a third offset bit number of each PXIE case according to a time length of a third waveform signal corresponding to the reference PXIE case relative to a third waveform signal corresponding to each PXIE case;
and controlling the waveform signals output by the PXIE boxes to be output in a delayed manner according to the corresponding third offset bit number, so that the DAC channels of the AWG boards in the PXIE boxes synchronously output the waveform signals.
In an optional embodiment of the present application, when each DAC channel of the AWG board receives a channel synchronization instruction, acquiring rising edge data of the first waveform signal output by each DAC channel, includes:
when each DAC channel of each AWG board card in a plurality of PXIE chassis receives a synchronization instruction, acquiring a first waveform signal of each DAC channel of each AWG board card in each PXIE chassis;
correspondingly, comparing the rising edge data of each first waveform signal to determine the reference DAC channel with the slowest output waveform signal, includes:
determining a reference DAC channel with the slowest output signal in all the DAC channels according to first waveform signals corresponding to all the DAC channels in the PXIE chassis;
controlling the waveform signals output by the DAC channels to be output in a delayed mode according to the corresponding first offset digit, and the method comprises the following steps:
and controlling the first waveform signals of all the DAC channels in each PXIE box to be output in a delayed mode according to the corresponding first offset bit number, so that each DAC channel of the AWG board card in each PXIE box synchronously outputs the waveform signals.
In an optional embodiment of the present application, acquiring rising edge data of the first waveform signal output by each of the DAC channels includes:
and collecting the rising edge data of the first waveform signal output by each DAC channel at a sampling rate not lower than 1 GBPS.
The present application also provides a signal synchronization device of a multi-channel waveform generator, including:
the data acquisition module is used for acquiring rising edge data of the first waveform signal output by each DAC channel when each DAC channel of the AWG board card receives a channel synchronization instruction;
the data comparison module is used for comparing the rising edge data of each first waveform signal and determining a reference DAC channel which outputs the slowest waveform signal;
the offset bit number module is used for determining a first offset bit number of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel;
and the delay synchronization module is used for controlling the waveform signals output by the DAC channels to be output in a delay manner according to the corresponding first offset digit so as to enable the DAC channels of the AWG board card to synchronously output the waveform signals.
In an optional embodiment of the present application, the system further includes a board synchronization module, where the board synchronization module includes:
the AWG card acquisition unit is used for acquiring a second waveform signal output by any one DAC channel in each AWG card when each AWG card in the same PXIE chassis receives a card synchronization instruction after each DAC channel of the AWG card synchronously outputs the waveform signal;
the reference AWG board card unit is used for determining the reference AWG board card which outputs the slowest second waveform signal according to the rising edge data of the second waveform signal corresponding to each AWG board card;
the AWG board card offset unit is used for determining a second offset bit number of each AWG board card according to the time length of the time delay of the second waveform signal of the reference AWG board card relative to the second waveform signal of each AWG board card;
and the card synchronizing unit is used for controlling the waveform signals output by the AWG cards to be output in a delayed manner according to the corresponding second offset bits, so that the DAC channels of the AWG cards of the PXIE case synchronously output the waveform signals.
In an optional embodiment of the present application, the data acquisition module is configured to acquire rising edge data of the first waveform signal output by each DAC channel at a sampling rate not lower than 1 GBPS.
The present application also provides a signal synchronization apparatus of a multi-channel waveform generator, including:
the host is used for sending channel synchronization instructions to each DAC channel of the AWG board card;
the comparator is used for acquiring the first waveform signals output by the DAC channels and outputting rising edge data of the first waveform signals;
and the FPGA is connected with the comparator and is used for acquiring rising edge data corresponding to the first waveform signal output by each DAC channel and executing the operation steps of realizing the signal synchronization method of the multi-channel waveform generator.
The present application also provides a computer readable storage medium having stored thereon a computer program for execution by a processor to implement the operational steps of the signal synchronization method of a multichannel waveform generator as described in any one of the above.
The invention provides a signal synchronization method of a multi-channel waveform generator, which comprises the following steps: when each DAC channel of the AWG board card receives a channel synchronization instruction, collecting rising edge data of a first waveform signal output by each DAC channel; comparing the rising edge data of each first waveform signal, and determining a reference DAC channel which outputs the slowest waveform signal; determining a first offset digit of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel; and controlling the waveform signals output by the DAC channels to be output in a delayed mode according to the corresponding first offset digit so that the DAC channels of the AWG board card synchronously output the waveform signals.
In the application, when each DAC channel of an AWG board card of a waveform generator outputs a waveform signal, rising edge data of the waveform signal of each DAC channel is collected, under normal conditions, if the waveform signal of each DAC channel is synchronously output, output time corresponding to the rising edge of each waveform signal should be the same, but because the synchronous output signals among the DAC channels have errors, the output time of the rising edge of each waveform signal has differences; according to the method and the device, each waveform signal is subjected to delay output control according to the time difference of rising edge output among the waveform signals, so that the waveform signals output by each DAC channel achieve synchronous output, the synchronism of the waveform signals output by the waveform generator is guaranteed to be high to a certain extent, and different application requirements of the waveform generator are met.
The application also provides a signal synchronization device, equipment and a computer readable storage medium of the multichannel waveform generator, which have the beneficial effects.
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In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a signal synchronization method of a multi-channel waveform generator according to an embodiment of the present application;
fig. 2 is a schematic diagram of an internal structure of an AWG board card according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a plurality of AWG boards in the PXIE according to the embodiment of the present application;
fig. 4 is a schematic diagram illustrating an architecture of a plurality of PXIE boxes for synchronously outputting waveform signals according to an embodiment of the present disclosure;
fig. 5 is a block diagram of a signal synchronization apparatus of a multi-channel waveform generator according to an embodiment of the present invention.
Detailed Description
In a quantum computing measurement and control system, a multi-channel waveform generator is needed to realize multi-quantum bit control. In the waveform generator, one AWG card has 4 signal output channels, and one PXIE box can be inserted with 16 AWG cards at most, so that the signal output channels of 64 AWG cards can be provided in one PXIE box at most. One quantum bit in the quantum measurement and control system needs 3 signal output channels, so that one PXIE case can realize the control of 21 quantum bit at most. If 100 quantum bit control needs to be realized, 5 PXIE boxes need to be adopted, all signal output channels of all the PXIE boxes need to synchronously output signals, and most preferably, the synchronous output at a sub-nanosecond level can be achieved.
Therefore, the technical scheme of signal synchronization of the multi-channel waveform generator is provided, the high synchronism of the output signals of the multi-channel waveform generator is improved to a certain extent, and the wide application of the multi-channel waveform generator is facilitated.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, fig. 1 is a schematic flowchart of a signal synchronization method of a multi-channel waveform generator according to an embodiment of the present application, where the method may include:
s11: the AWG board card receives a channel synchronization instruction.
Channel synchronization instructions can be sent to each DAC channel of the AWG board card through an external host case, and other triggering mechanisms can be adopted to trigger each DAC channel to output signals simultaneously.
However, because the lengths of the communication links are different and the transmission signals of the communication links may differ, in an actual application process, even if the DAC channels are triggered at the same time, the actual waveform signal output times may also differ, thereby resulting in the asynchronization of the waveform signals output by the DAC channels.
S12: and each DAC channel of the AWG board card respectively outputs a first waveform signal.
S13: and the FPGA respectively acquires the rising edge data of the first waveform signal of each DAC channel.
In this embodiment, the rising edge data of the first waveform signal of each DAC channel and the subsequent synchronous output of each DAC channel are realized through the FPGA, and of course, other processors may also be used in this embodiment to realize the synchronous output of each DAC channel, for example, the host box may be used to collect the rising edge data of the first waveform signal of each DAC channel, and this embodiment is described by taking the FPGA as an example only.
As shown in fig. 2, fig. 2 is a schematic diagram of an internal structure of an AWG board card provided in the embodiment of the present application, where the AWG board card 1 includes 4 DAC chips, that is, 4 DAC channels outputting waveform signals, each DAC channel is connected to one comparator 3, each comparator 3 collects a waveform signal output by each DAC channel, when the waveform signal rises to a level greater than a predetermined signal, the comparator 3 outputs a high level signal, when the waveform signal falls to a level less than the predetermined signal, the comparator 3 outputs a low level signal, if 1 and 0 respectively represent the high level signal and the low level signal output by the comparator 3, and when the signal output by the comparator 3 connected to one DAC channel changes from 0 to 1, a rising edge time of the DAC channel is corresponding; the signal output by each comparator 3 is also the rising edge data of each DAC channel.
The comparators 3 connected with the respective DAC channels are respectively connected with the Iserdes modules of the FPGA2, so that the rising edge data of the 4 DAC channels of the AWG board card 1 can be input to the FPGA2 in parallel, and the operating frequency of the FPGA2 can be reduced.
S14: and comparing the rising edge data of the first waveform signals to determine the reference DAC channel with the slowest output waveform signal.
S15: and determining a first offset bit number of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel.
S16: and outputting the waveform signals output by the DAC channels in a delayed manner according to the corresponding first offset digit so as to enable the DAC channels of the AWG board card to synchronously output the waveform signals.
It will be appreciated that the accuracy of synchronizing the output waveform signals for the various DAC channels of the AWG card should have a large correlation with the FPGA sampling frequency. And the first number of offset bits determined at the comparison of the rising edge data of the respective DAC channels is also determined based on the sampling rate.
For example, the sampling frequency of each DAC channel by the FPGA is 1ns apart, and then at the 1ns, if the waveform signals of the first DAC channel and the second DAC channel are both 0, and the waveform signals of the third DAC channel and the fourth DAC channel are both 1; when the second DAC channel is in the 2 nd ns, the waveform signal of the first DAC channel is 0, and the waveform signals of the second DAC channel, the third DAC channel and the fourth DAC channel are all 1; at the time of 3ns, the waveform signals of the first DAC channel, the second DAC channel, the third DAC channel and the fourth DAC channel are all 1, and then the first DAC channel is also the DAC channel that outputs the slowest waveform signal, and accordingly, the first DAC channel is taken as the reference DAC channel, and the first offset bits of the second DAC channel, the third DAC channel and the fourth DAC channel are 1ns, 2ns and 2ns, respectively.
Taking two DAC channels as an example, a waveform signal of the two DAC channels is simultaneously collected inside the FPGA, and rising edge data is sampled by two comparators: binary data 4 ' b1100 sampled by the first DAC channel, and data sampled by the second DAC channel is 4 ' b1110, which means that the second DAC channel outputs a waveform 1ns earlier than the first DAC channel, the waveform data sent by the second DAC channel is output by delaying 1ns integrally according to the comparison result, and then the received rising edge data are both 4 ' b1100 through the comparator result, the waveforms output by the two DAC channels are within 1ns, the sub-nanosecond level is achieved, and the difference of actual tested channels is within 100 ps.
Optionally, in order to improve the accuracy of the synchronous output waveform signals of the DAC channels, when the FPGA acquires rising edge data of each first waveform signal, the FPGA may sample at a sampling rate not lower than 1GBPS, so as to ensure that the accuracy of the synchronization of the DAC channels is within 1 ns.
In summary, in the present application, by comparing the rising edge data of the waveform signals output by each DAC channel, and delaying the waveform signals of the DAC channels that output the waveform signals faster until the waveform signals are consistent with the DAC channel that outputs the waveform signal slowest, it is ensured that each DAC channel outputs the waveform signals synchronously; furthermore, when rising edge data of the room compensation signals of different DAC channels are collected, each DAC channel is sampled at a sampling rate not less than 1GBPS, and further the synchronous precision of synchronously outputting waveform signals by each DAC channel is ensured to be within 1ns, the progress of synchronously outputting signals by a plurality of DAC channels is ensured to a great extent, and various different high-requirement applications of the waveform generator are met.
In consideration of the practical application of the AWG card, it is not limited to synchronizing the DAC channels in a single AWG card, but also requires synchronizing the output waveform signals among a plurality of AWG cards. Therefore, after the AWG boards in one AWG board synchronously output waveform signals, a plurality of AWG boards can synchronously output the waveform signals by adopting a similar principle. Then, in another optional embodiment of the present application, on the basis of the plurality of DAC channels outputting waveform signals synchronously in a single AWG card, the method may further include:
s21: and when each AWG board card in the same PXIE case receives a board card synchronization instruction, acquiring a second waveform signal output by any DAC channel in each AWG board card.
As shown in fig. 3, fig. 3 is a schematic structural diagram of a plurality of AWG boards inside the PXIE according to the embodiment of the present application. A cascade switch board 5 is arranged in the PXIE chassis 6, each AWG board 1 is connected to the cascade switch board 5 through the backplane 4, the main chassis can send a board synchronization instruction to each AWG board 1 through the cascade switch board 5, and the cascade switch board 5 collects rising edge data corresponding to a waveform signal output from the DAC channel of each AWG board 1.
Obviously, because the waveform signals output by the DAC channels of the same AWG card 1 in the PXIE chassis 6 are already synchronously modulated, accordingly, when acquiring the waveform signals in the respective AWG cards 1, only the rising edge data of the waveform signal of any one DAC channel may be acquired in each AWG card 1.
S22: and determining the reference AWG board card which outputs the second waveform signal slowest according to the rising edge data of the second waveform signal corresponding to each AWG board card.
S23: and determining a second offset digit of each AWG board card according to the time length of the time delay of the second waveform signal of the reference AWG board card relative to the second waveform signal of each AWG board card.
S24: and outputting the waveform signals output by each AWG board card in a delayed manner according to the corresponding second offset digit so as to enable each DAC channel of each AWG board card of the PXIE case to synchronously output the waveform signals.
When the waveform signals output by all the AWG board cards are synchronously modulated, the modulation principle is the same as the principle of synchronously modulating the waveform signals output by a plurality of DAC channels of a single AWG board card, the rising edge data corresponding to all the AWG board cards are compared to determine the reference AWG board card with the slowest output waveform signal, then the time sequence of the waveform signals output by all the DAC channels of other AWG board cards is taken as the reference, the waveform signals output by all the DAC channels of other AWG board cards are subjected to delay modulation, and therefore all the DAC channels of all the AWG board cards in the same PXIE case can synchronously output the waveform signals. Similarly, when the rising edge data corresponding to each AWG board card is sampled, the sampling rate can be controlled to be not less than 1GBPS, so as to ensure that the synchronization precision reaches a sub-nanosecond level.
Furthermore, after controlling all DAC channels of all AWG boards in the same PXIE chassis to synchronously output waveform signals, a plurality of PXIE chassis can be controlled to synchronously output waveform signals in a similar manner. In another optional embodiment of the present application, the method may further include:
s31: when a plurality of PXIE boxes receive a box synchronization command, collecting a third waveform signal output by any DAC channel in any AWG board card in each PXIE box.
As shown in fig. 4, fig. 4 is a schematic diagram of an architecture for synchronously outputting waveform signals from a plurality of PXIE boxes according to an embodiment of the present disclosure.
The mainframe box can send a box synchronization command to each PXIE box 6 through the cascade switch board 5 in each PXIE box 6, and respectively acquire rising edge data corresponding to the waveform signal output by the PXIE box 6 through each cascade switch board 5.
In this embodiment, the synchronous modulation is performed on each PXIE enclosure 6 after each DAC channel of each AWG board card 1 in each PXIE enclosure 6 has been subjected to the synchronous modulation. Therefore, theoretically, the rising edge data of the waveform signals output by all the DAC channels in each PXIE chassis 6 should be the same, and when collecting the rising edge data, only the rising edge data corresponding to one DAC channel in each PXIE chassis is collected arbitrarily.
S32: and determining the reference PXIE case which outputs the slowest third waveform signal according to the rising edge data of the third waveform signal corresponding to each PXIE case.
S33: and determining a third offset bit number of each PXIE case according to the time length of the delay of the third waveform signal corresponding to the reference PXIE case relative to the third waveform signal corresponding to each PXIE case.
S34: and delaying and outputting the waveform signals output by each PXIE case according to the corresponding third offset digit, so that each DAC channel of each AWG board card in each PXIE case synchronously outputs the waveform signals.
In this embodiment, the principle and the manner of synchronizing the waveform signals of the plurality of DAC channels output between the PXIE chassis are the same as those of the AWG board card and the plurality of DAC channels, and are not described herein again.
In the above embodiment, when the multi-channel output waveform signals of the waveform generator are synchronously modulated, the multi-channel output waveform signals of the same AWG board card are synchronously modulated first, then the synchronous modulation of the plurality of AWG board cards in the same PXIE chassis is realized, and finally the synchronous modulation of the plurality of PXIE chassis is realized. The application is not limited to the final implementation of synchronous modulation of multiple PXIE chassis in this way.
In another optional embodiment of the present application, there is also provided a signal synchronization method of a multi-channel waveform generator, which may include:
s41: and the main chassis sends a synchronization command to the cascade switch boards of the PXIE chassis.
S42: and the main case collects waveform signals of the DAC channels of the AWG boards in the PXIE boxes.
The sampling rate may also be not less than 1 GBPS.
S43: and determining a reference DAC channel with the slowest output signal in all the DAC channels according to the waveform signals corresponding to all the DAC channels in the PXIE boxes.
S44: and determining the offset digit of each DAC channel according to the time length of the waveform signal of the reference DAC channel relative to the waveform signal of each DAC channel.
S45: and delaying and outputting the waveform signals of all the DAC channels in each PXIE box according to the corresponding offset digit, so that each DAC channel of the AWG board card in each PXIE box synchronously outputs the waveform signals.
In the embodiment, when all the DAC channels of each PXIE chassis are synchronously modulated, the rising edge data of the waveform signals of all the DAC channels are collected at the same time, and all the channels of the same team are uniformly modulated at one time, so that the complexity of multi-time hierarchical modulation is greatly reduced, and the modulation process of synchronously outputting the waveform signals by a plurality of PXIE chassis is simplified.
It should be understood that, it is only necessary to modulate the signals output by the AWG cards in one PXIE chassis into synchronous output signals, and a similar one-time modulation method may also be used, which is not limited in this application.
The following describes a signal synchronization apparatus of a multi-channel waveform generator according to an embodiment of the present invention, and the signal synchronization apparatus of the multi-channel waveform generator described below and the signal synchronization method of the multi-channel waveform generator described above may be referred to in correspondence with each other.
Fig. 5 is a block diagram of a signal synchronization apparatus of a multi-channel waveform generator according to an embodiment of the present invention, and the signal synchronization apparatus of the multi-channel waveform generator according to fig. 5 may include:
the data acquisition module 100 is configured to acquire rising edge data of a first waveform signal output by each DAC channel when each DAC channel of the AWG board receives a channel synchronization instruction;
the data comparison module 200 is configured to compare rising edge data of each first waveform signal, and determine a reference DAC channel that outputs the slowest waveform signal;
an offset bit number module 300, configured to determine a first offset bit number of each DAC channel according to a time length of a time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel;
and a delay synchronization module 400, configured to delay and output the waveform signal output by each DAC channel according to the corresponding first offset bit number, so that each DAC channel of the AWG board synchronously outputs the waveform signal.
In an optional embodiment of the present application, the system further includes a board synchronization module, where the board synchronization module includes:
the AWG card acquisition unit is used for acquiring a second waveform signal output by any one DAC channel in each AWG card when each AWG card in the same PXIE chassis receives a card synchronization instruction after each DAC channel of the AWG card synchronously outputs the waveform signal;
the reference AWG board card unit is used for determining the reference AWG board card which outputs the slowest second waveform signal according to the rising edge data of the second waveform signal corresponding to each AWG board card;
the AWG board card offset unit is used for determining a second offset bit number of each AWG board card according to the time length of the delay of the second waveform signal of the reference AWG board card relative to the second waveform signal of each AWG board card;
and the card synchronizing unit is used for outputting the waveform signals output by the AWG cards in a delayed manner according to the corresponding second offset bits, so that the DAC channels of the AWG cards of the PXIE case synchronously output the waveform signals.
In another optional embodiment of the present application, the data acquisition module 100 is configured to acquire rising edge data of the first waveform signal output by each DAC channel at a sampling rate not lower than 1 GBPS.
The signal synchronization device of the multi-channel waveform generator of this embodiment is used to implement the signal synchronization method of the multi-channel waveform generator, and therefore, the specific implementation manner of the signal synchronization device of the multi-channel waveform generator may be found in the foregoing embodiments of the signal synchronization method of the multi-channel waveform generator, for example, the data acquisition module 100, the data comparison module 200, the offset bit number module 300, and the delay synchronization module 400 are respectively used to implement steps S11 to S16 in the signal synchronization method of the multi-channel waveform generator, so that the specific implementation manner thereof may refer to the description of the corresponding embodiments of the respective components, and will not be described herein again.
The present application further provides an embodiment of a signal synchronization apparatus for a multi-channel waveform generator, the apparatus comprising:
the host is used for sending channel synchronization instructions to each DAC channel of the AWG board card;
the comparator is used for acquiring the first waveform signals output by the DAC channels and outputting rising edge data of the first waveform signals;
and the FPGA is connected with the comparator and is used for acquiring rising edge data corresponding to the first waveform signal output by each DAC channel and executing the operation steps of realizing the signal synchronization method of the multi-channel waveform generator.
It should be noted that the FPGA may be embedded in the PXIE chassis or the host, and the FPGA may also be another form of processor, which is not limited in this application.
The present application further provides an embodiment of a computer-readable storage medium having stored thereon a computer program for execution by a processor to implement the operational steps of the signal synchronization method of a multi-channel waveform generator as claimed in any one of the preceding claims.
The computer-readable storage medium may be Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include elements inherent in the list. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In addition, parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of corresponding technical solutions in the prior art, are not described in detail so as to avoid redundant description.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A method for signal synchronization of a multi-channel waveform generator, comprising:
when each DAC channel of the AWG board card receives a channel synchronization instruction, acquiring rising edge data of a first waveform signal output by each DAC channel;
comparing the rising edge data of each first waveform signal, and determining a reference DAC channel which outputs the slowest waveform signal;
determining a first offset bit number of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel;
and controlling the waveform signals output by the DAC channels to be output in a delayed manner according to the corresponding first offset digit so as to enable the DAC channels of the AWG board card to synchronously output the waveform signals.
2. The method for signal synchronization of a multi-channel waveform generator of claim 1 further comprising, after synchronizing the output waveform signals for each of said DAC channels of said AWG card,:
when each AWG board card in the same PXIE case receives a board card synchronization instruction, acquiring a second waveform signal output by any DAC channel in each AWG board card;
determining a reference AWG board card which outputs the slowest second waveform signal according to the rising edge data of the second waveform signal corresponding to each AWG board card;
determining a second offset digit of each AWG board card according to the time length of the time delay of the second waveform signal of the reference AWG board card relative to the second waveform signal of each AWG board card;
and controlling the waveform signals output by the AWG board card to be output in a delayed manner according to the corresponding second offset digit so as to enable each DAC channel of each AWG board card of the PXIE case to synchronously output the waveform signals.
3. The method for signal synchronization of a multi-channel waveform generator as claimed in claim 2, further comprising, after synchronizing the output waveform signals of the respective DAC channels of the AWG card of the PXIE chassis, the step of:
when a plurality of PXIE boxes receive a box synchronization command, acquiring a third waveform signal output by any DAC channel in any AWG board card in each PXIE box;
determining a reference PXIE case which outputs the slowest third waveform signal according to rising edge data of the third waveform signal corresponding to each PXIE case;
determining a third offset bit number of each PXIE case according to a time length of a third waveform signal corresponding to the reference PXIE case relative to a third waveform signal corresponding to each PXIE case;
and controlling the waveform signals output by the PXIE boxes to be output in a delayed manner according to the corresponding third offset bit number, so that the DAC channels of the AWG boards in the PXIE boxes synchronously output the waveform signals.
4. The method of signal synchronization for a multi-channel waveform generator of claim 1 wherein collecting leading edge data for the first waveform signal output by each of the DAC channels of the AWG card when the respective DAC channel receives a channel synchronization instruction comprises:
when each DAC channel of each AWG board card in a plurality of PXIE chassis receives a synchronization instruction, acquiring a first waveform signal of each DAC channel of each AWG board card in each PXIE chassis;
correspondingly, comparing the rising edge data of each first waveform signal to determine the reference DAC channel with the slowest output waveform signal, includes:
determining a reference DAC channel with the slowest output signal in all the DAC channels according to first waveform signals corresponding to all the DAC channels in the PXIE chassis;
controlling the waveform signals output by the DAC channels to be output in a delayed mode according to the corresponding first offset digit, and the method comprises the following steps:
and controlling the first waveform signals of all the DAC channels in each PXIE box to be output in a delayed mode according to the corresponding first offset bit number, so that each DAC channel of the AWG board card in each PXIE box synchronously outputs the waveform signals.
5. The signal synchronization method of a multi-channel waveform generator according to any one of claims 1 to 4, wherein acquiring rising edge data of the first waveform signal output from each of the DAC channels comprises:
and collecting the rising edge data of the first waveform signal output by each DAC channel at a sampling rate not lower than 1 GBPS.
6. A signal synchronizing device of a multi-channel waveform generator, comprising:
the data acquisition module is used for acquiring rising edge data of the first waveform signal output by each DAC channel when each DAC channel of the AWG board card receives a channel synchronization instruction;
the data comparison module is used for comparing the rising edge data of each first waveform signal and determining a reference DAC channel which outputs the slowest waveform signal;
the offset bit number module is used for determining a first offset bit number of each DAC channel according to the time length of the time delay of the first waveform signal of the reference DAC channel relative to the first waveform signal of each DAC channel;
and the delay synchronization module is used for controlling the waveform signals output by the DAC channels to be output in a delay manner according to the corresponding first offset digit so as to enable the DAC channels of the AWG board card to synchronously output the waveform signals.
7. The signal synchronizing device of a multi-channel waveform generator according to claim 6, further comprising a board synchronization module, the board synchronization module comprising:
the AWG card acquisition unit is used for acquiring a second waveform signal output by any one DAC channel in each AWG card when each AWG card in the same PXIE chassis receives a card synchronization instruction after each DAC channel of the AWG card synchronously outputs the waveform signal;
the reference AWG board card unit is used for determining the reference AWG board card which outputs the slowest second waveform signal according to the rising edge data of the second waveform signal corresponding to each AWG board card;
the AWG board card offset unit is used for determining a second offset bit number of each AWG board card according to the time length of the time delay of the second waveform signal of the reference AWG board card relative to the second waveform signal of each AWG board card;
and the card synchronizing unit is used for controlling the waveform signals output by the AWG cards to be output in a delayed manner according to the corresponding second offset bits, so that the DAC channels of the AWG cards of the PXIE case synchronously output the waveform signals.
8. The signal synchronizer of the multi-channel waveform generator as claimed in claim 6 or 7, wherein said data acquisition module is configured to acquire rising edge data of the first waveform signal outputted from each of said DAC channels at a sampling rate not lower than 1 GBPS.
9. A signal synchronizing device of a multi-channel waveform generator, comprising:
the host is used for sending channel synchronization instructions to each DAC channel of the AWG board card;
the comparator is used for acquiring the first waveform signals output by the DAC channels and outputting rising edge data of the first waveform signals;
and the FPGA is connected with the comparator and is used for acquiring rising edge data corresponding to the first waveform signal output by each DAC channel and executing the operation steps of the signal synchronization method of the multi-channel waveform generator according to any one of claims 1 to 5.
10. A computer-readable storage medium, characterized in that it stores a computer program which is executed by a processor to implement the operational steps of the signal synchronization method of a multi-channel waveform generator according to any one of claims 1 to 5.
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| CN114528998A (en) * | 2022-01-26 | 2022-05-24 | 山东浪潮科学研究院有限公司 | Multi-board-card signal synchronization method, device and medium for quantum measurement and control system |
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Application publication date: 20200925 |