CN114326925A - Signal synchronous output method, device, equipment and medium - Google Patents
Signal synchronous output method, device, equipment and medium Download PDFInfo
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- CN114326925A CN114326925A CN202111533127.6A CN202111533127A CN114326925A CN 114326925 A CN114326925 A CN 114326925A CN 202111533127 A CN202111533127 A CN 202111533127A CN 114326925 A CN114326925 A CN 114326925A
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Abstract
The embodiment of the application discloses a method, a device, equipment and a medium for synchronously outputting signals. Determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal; acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position; comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively to determine the delay time corresponding to the other slot positions respectively; and performing signal delay processing with different time lengths on different slot positions according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions. By the method, different slot positions synchronously output waveform signals.
Description
Technical Field
The present application relates to the field of quantum computing, and in particular, to a method, an apparatus, a device, and a medium for synchronously outputting signals.
Background
In recent years, with the development of superconducting quantum computing technology, superconducting quantum computing measurement and control systems have more and more requirements, measurement and control systems have various forms, and the requirements on technical indexes of the measurement and control systems are more and more strict. The synchronism of the output signals of the multi-channel arbitrary waveform generator for controlling the superconducting quantum chip is one of important indexes.
Taking a PXIE chassis as an example, an external trigger signal is accessed to a chassis panel, the signal is divided into a plurality of trigger signals after passing through a buffer chip on a backplane, and different trigger signals are respectively connected to different slots.
Disclosure of Invention
The embodiment of the application provides a signal synchronous output method, a device, equipment and a medium, which are used for solving the following technical problems: because the PCB wiring of a plurality of trigger signals is not processed with strict equal length, the transmission delay of the trigger signals of different slot positions is different, so that the waveform signal output is difficult to be synchronously performed.
The embodiment of the application adopts the following technical scheme:
the embodiment of the application provides a signal synchronous output method. The method comprises the steps of determining slot positions corresponding to different arbitrary waveform generators according to received slot position judgment signals; acquiring the time of respectively outputting waveform signals after different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position; comparing the time of outputting the waveform signals by other slots with the time of outputting the waveform signals by the reference slot respectively to determine the delay time corresponding to other slots respectively; and according to the delay time, performing signal delay processing with different durations on different slot positions so as to realize synchronous output of waveform signals of different slot positions.
This application embodiment is through determining the trench that different arbitrary waveform generator corresponds, and determine the time that different arbitrary waveform generator signals, can determine the delay time of different trench signals, carry out the delay processing to different trenches according to this delay time, let the trench delay signal waveform that the signal time is very fast, thereby realize that different trenches send waveform signal in step, and then solve the signal and input the different trenches of quick-witted case from the machine case, because PCB walks the line inconsistent, so that the signal is difficult to the problem of synchronous output.
In an implementation manner of the present application, according to the delay time, signal delay processing with different durations is performed on different slot positions, which specifically includes: taking the slot position with the longest delay time as a first slot position; and performing signal delay processing with different time lengths on different slot positions according to the delay time length corresponding to the first slot position.
In an implementation manner of the present application, according to a time delay duration corresponding to the first slot, signal delay processing is performed on different slots at different time durations, specifically including: taking the time delay duration corresponding to the first slot position as the time duration for signal time delay processing of the reference slot position; and determining delay difference values between the other different slot positions and the first slot position respectively, and taking the delay difference values as the time length for performing signal delay processing on the other different slot positions respectively.
In an implementation manner of the present application, determining delay times corresponding to other slot positions respectively specifically includes: and determining the time of sending out the signal by delaying after each slot position receives the trigger signal according to the working clock frequency of the field programmable gate array.
According to the embodiment of the application, the time of sending the signal after each slot position is delayed after the triggering signal is received is determined according to the working clock frequency of the field programmable gate array. Therefore, the accuracy of the time for receiving the signal is improved, and the calculated delay time is more accurate.
In an implementation manner of the present application, the slot positions corresponding to different arbitrary waveform generators are determined according to the received slot position determination signal, and the method specifically includes: and determining the slot position where the level signal changes, and taking the slot position where the level signal changes as the slot position where the current arbitrary waveform generator is inserted.
In an implementation manner of the present application, the slot that first sends out the waveform signal is used as a reference slot, and specifically includes: after one or more arbitrary waveform generators are inserted into part of slots in a chassis, receiving a first waveform signal output by the one or more arbitrary waveform generators through an oscilloscope; determining a second slot position with the fastest time for sending the first waveform signal; after the one or more arbitrary waveform generators are reinserted into the residual slot positions in the chassis, receiving second waveform signals output by the one or more arbitrary waveform generators through an oscilloscope until waveform signal output time corresponding to all slot positions to be tested is obtained; and comparing the output time corresponding to the second waveform signal with the output time of the second slot position to determine the reference slot position.
In an implementation manner of the present application, acquiring the time for respectively outputting waveform signals after different arbitrary waveform generators receive a trigger signal specifically includes: and taking the time of the oscillograph for acquiring the waveform signals output by different arbitrary waveform generators as the time of respectively outputting the waveform signals by different slot positions.
The embodiment of the application provides a signal synchronization output device, includes: the slot position determining unit is used for determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judging signal; a reference slot position determination unit; acquiring the time of respectively outputting waveform signals after different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position; the delay time determining unit is used for comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively so as to determine the delay time corresponding to other slot positions respectively; and the delay processing unit is used for carrying out signal delay processing on different slot positions with different time lengths according to the delay time so as to realize synchronous output of waveform signals of different slot positions.
The embodiment of the application provides a signal synchronization output device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to: determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal; acquiring the time of respectively outputting waveform signals after different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position; comparing the time of outputting the waveform signals by other slots with the time of outputting the waveform signals by the reference slot respectively to determine the delay time corresponding to other slots respectively; and according to the delay time, performing signal delay processing with different durations on different slot positions so as to realize synchronous output of waveform signals of different slot positions.
A non-volatile computer storage medium provided in an embodiment of the present application stores computer-executable instructions, and the computer-executable instructions are configured to: determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal; acquiring the time of respectively outputting waveform signals after different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position; comparing the time of outputting the waveform signals by other slots with the time of outputting the waveform signals by the reference slot respectively to determine the delay time corresponding to other slots respectively; and according to the delay time, performing signal delay processing with different durations on different slot positions so as to realize synchronous output of waveform signals of different slot positions.
The embodiment of the application adopts at least one technical scheme which can achieve the following beneficial effects: this application embodiment is through determining the trench that different arbitrary waveform generator corresponds, and determine the time that different arbitrary waveform generator signals, can determine the delay time of different trench signals, carry out the delay processing to different trenches according to this delay time, let the trench delay signal waveform that the signal time is very fast, thereby realize that different trenches send waveform signal in step, and then solve the signal and input the different trenches of quick-witted case from the machine case, because PCB walks the line inconsistent, so that the signal is difficult to the problem of synchronous output.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative effort. In the drawings:
fig. 1 is a flowchart of a signal synchronization output method according to an embodiment of the present application;
fig. 2 is a block diagram of a signal synchronization output process provided in an embodiment of the present application;
fig. 3 is a diagram illustrating an example of synchronous output of an 8-slot signal according to an embodiment of the present application;
fig. 4 is a schematic diagram of a signal synchronization output apparatus according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a signal synchronization output device according to an embodiment of the present application.
Detailed Description
The embodiment of the application provides a signal synchronous output method, a device, equipment and a medium.
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any inventive step based on the embodiments of the present disclosure, shall fall within the scope of protection of the present application.
In recent years, with the development of superconducting quantum computing technology, superconducting quantum computing measurement and control systems have more and more requirements, measurement and control systems have various forms, and the requirements on technical indexes of the measurement and control systems are more and more strict. The synchronism of the output signals of the multi-channel arbitrary waveform generator for controlling the superconducting quantum chip is one of important indexes.
Taking a PXIE chassis as an example, an external trigger signal is accessed to a chassis panel, the signal is divided into a plurality of trigger signals after passing through a buffer chip on a backplane, and different trigger signals are respectively connected to different slots.
In order to solve the above problem, embodiments of the present application provide a method, an apparatus, a device, and a medium for synchronously outputting signals. Through determining the trench that different arbitrary waveform generator corresponds, and determine the time that different arbitrary waveform generator signals, can determine the delay time that different trench signals, carry out delay processing to different trench according to this delay time, let the trench delay that signal time is fast send signal waveform, thereby realize that different trench sends waveform signal in step, and then solve the signal and input different trench of quick-witted case from the machine case, because PCB walks the line inconsistent, so that the problem that the signal is difficult to synchronous output.
The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a flowchart of a signal synchronous output method according to an embodiment of the present disclosure. As shown in fig. 1, the signal synchronization output method includes the following steps:
s101, the signal synchronous output device determines the slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal.
In one embodiment of the present application, the signal synchronization output device determines a slot where a level signal changes, and takes the slot where the level signal changes as a slot into which the current arbitrary waveform generator is inserted.
Specifically, in a PXIE bus chassis-based system applied to the field of quantum computing, when an external trigger signal is used, the signal is input from the chassis to the chassis at different slot positions with different delay time of PCB traces because the signal is not buffered at the chassis backplane to have equal lengths of all slot positions PCB traces, so that output signals at different slot positions are difficult to synchronize. Therefore, different slot positions need to be delayed, so that the time of sending signals by all slot positions is synchronized.
Further, the external trigger signal receiver box panel is first powered up and the system is powered up. The arbitrary waveform generator is inserted into the slot position of the chassis, the level of the slot position will change at the moment, and a slot position judgment signal is sent out. And the Field Programmable Gate Array (FPGA) judges the slot position of the arbitrary waveform generator in the case according to the level change of the slot position of the system.
S102, the signal synchronous output device obtains the time of respectively outputting the waveform signals after different arbitrary waveform generators receive the trigger signals, and the slot position which sends out the waveform signal firstly is used as a reference slot position.
In one embodiment of the application, an external required frequency trigger signal is accessed into a system through a front panel of a chassis, a plurality of arbitrary waveform generator modules are inserted into different slot positions of the chassis, and an oscilloscope is used for measuring the state of an output signal of the arbitrary waveform generator modules in the different slot positions when the signal is used as trigger. And finding out the slot position which firstly sends out the waveform, wherein the delay of the slot position trigger signal is the lowest, and the slot position is taken as a reference slot position.
In one embodiment of the application, after one or more arbitrary waveform generators are inserted into a part of slots in a chassis, a first waveform signal output by the one or more arbitrary waveform generators is received through an oscilloscope. And determining a second slot position with the fastest time for sending the first waveform signal. And after the one or more arbitrary waveform generators are reinserted into the residual slot positions in the chassis, receiving second waveform signals output by the one or more arbitrary waveform generators through an oscilloscope until waveform signal output time corresponding to all the slot positions to be tested is obtained. And comparing the output time corresponding to the second waveform signal with the output time of the second slot position to determine the reference slot position.
Specifically, there are a plurality of slots in the chassis. According to the embodiment of the application, one or more arbitrary waveform generators can be inserted into partial slot positions in the chassis, the trigger signal is sent out at the moment, and the waveform signals can be sent out after the trigger signal is received by the arbitrary waveform generators. And receiving the waveform signal through a preset oscilloscope. And determining the slot position which sends the signal most quickly according to the time of the oscilloscope receiving the waveform signal, and taking the slot position as a second slot position. At the moment, the one or more arbitrary waveform generators are reinserted into other slot positions of the case, the trigger signal is reissued, the oscillograph receives waveform signals respectively sent by the current slot positions to determine the time of outputting the waveform signals respectively corresponding to the current slot positions, the time of receiving the output waveform signals for the second time is compared with the time corresponding to the second slot position, and the slot position which sends the waveform most quickly is used as a reference slot position.
It should be noted that, according to the number of the oscilloscopes with arbitrary waveforms and the number of slots in the chassis, the number of the oscilloscopes receiving the output waveforms each time and the number of times the oscilloscopes receive the waveforms may be adjusted accordingly.
In an embodiment of the present application, the time that the oscilloscope acquires the waveform signals output by different arbitrary waveform generators is used as the time that different slot positions output the waveform signals respectively.
Specifically, in order to uniformly measure the time of the output signal of the arbitrary waveform generator, the time when the oscilloscope receives the waveform is used as the time of the output signal of the arbitrary waveform generator in the embodiment of the present application, so that the time measurement standard is unified, and the error generated during time measurement is reduced.
S103, the signal synchronous output equipment compares the time of the waveform signals output by other slot positions with the time of the waveform signals output by the reference slot position respectively to determine the delay time corresponding to other slot positions respectively.
In one embodiment of the present application, the lowest delayed slot position output signal is used as a determination reference, and the other slot position output signals are compared with the lowest delayed slot position output signal, and the comparison delay time between the different slot position output signals and the slot position is recorded.
In one embodiment of the present application, the time for each slot to delay the signal transmission after receiving the trigger signal is determined according to the operating clock frequency of the field programmable gate array.
It should be noted that the programmable gate array is a product developed on the basis of programmable devices such as PAL, GAL, etc. The circuit is a semi-custom circuit in the field of application-specific integrated circuits, not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
And S104, performing signal delay processing with different durations on different slot positions by the signal synchronous output equipment according to the delay time so as to realize synchronous output of waveform signals of different slot positions.
In one embodiment of the present application, the slot with the longest delay time is taken as the first slot. And performing signal delay processing with different time lengths on different slot positions according to the delay time length corresponding to the first slot position.
Specifically, in the embodiment of the present application, the slot position with the longest delay time is used as the first slot position, and the other slot positions are subjected to delay processing, so that the time for outputting the waveform after the delay of the other slot positions is the same as the time for outputting the waveform by the first slot position, that is, the purpose of synchronously outputting the waveform signal by different slot positions is achieved.
In an embodiment of the present application, a delay time duration corresponding to the first slot is used as a time duration for performing signal delay processing on the reference slot. And determining delay difference values between the other different slot positions and the first slot position respectively, and taking the delay difference values as the time length for performing signal delay processing on the other different slot positions respectively.
Specifically, the delay time duration corresponding to the first slot is a time difference between the first slot and the reference slot. Therefore, according to the delay duration corresponding to the first slot position, the reference slot position is subjected to delay processing, and the synchronous output waveform of the reference slot position and the first slot position can be realized.
Further, the time delay difference value between the other slot position and the first slot position is determined, and the time delay processing is respectively carried out on the other slot positions according to the time delay difference value. For example, the delay time of the third slot and the first slot is 0.1S, and at this time, the third slot is delayed by 0.1S, so that the waveform can be synchronously output by the third slot and the first slot.
Fig. 2 is a block diagram of a signal synchronization output process according to an embodiment of the present disclosure. As shown in fig. 2, an external trigger signal is coupled into the chassis panel and powers up the system. After any waveform generator is inserted into the slot position, the level signal corresponding to the slot position changes, and the FPGA judges the slot position of any waveform generator in the case according to the level change of the system slot position. And finding out the slot position with the lowest delay of the trigger signal according to the time of the output waveforms sent out by the plurality of arbitrary waveform generator modules at different slot positions. The delay time between the other slot and the lowest delayed slot is determined. And performing corresponding delay processing on each slot position according to different delay times. And the FPGA program receives the trigger signal through the slot position implementation and then carries out different delay processing so as to realize the output synchronization of all slot position signals.
Fig. 3 is a diagram illustrating an example of synchronous output of an 8-slot signal according to an embodiment of the present application. As shown in fig. 3, an 8-slot PXIE chassis is taken as an example for explanation, an external trigger signal is accessed to a chassis panel, the signal is divided into 8 trigger signals after passing through a buffer chip on a backplane, different trigger signals are respectively connected to different slots, and because the 8 trigger signal PCB traces do not perform strict equal-length processing, transmission delays of the trigger signals of different slots are different.
An external trigger signal is coupled to the chassis panel and powers up the system. And the FPGA judges which slot position of the current arbitrary waveform generator is in the slot positions 1 to 8 according to the level of the system slot position. One or more arbitrary waveform generators are sequentially inserted into the case, for example, two arbitrary waveform generators can be sequentially inserted into the case, the arbitrary waveform generators send out waveform signals after receiving the trigger signals, and the time for sending out the waveform signals by the arbitrary waveform generators is judged through an oscilloscope so as to determine the slot position with the fastest output signal. For example, slot No. 1 is the slot in which the output signal is fastest. The time difference between the time when the slot No. 2 to 7 outputs the signal and the time when the slot No. 1 outputs the signal is tested. And determining the time length of different slot positions needing delay processing after receiving the trigger signal according to the tested time difference. And the FPGA program realizes the output synchronization of all slot position signals through different delay processing.
Fig. 4 is a schematic diagram of a signal synchronization output apparatus according to an embodiment of the present application. As shown in fig. 4, the signal synchronization output apparatus includes a slot position determining unit 401, a reference slot position determining unit 402, a delay time determining unit 403, and a delay processing unit 404.
A slot position determining unit 401, which determines slot positions corresponding to different arbitrary waveform generators according to the received slot position determination signal;
a reference slot position determination unit 402; acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
a delay time determining unit 403, comparing the time of outputting the waveform signal by the other slot with the time of outputting the waveform signal by the reference slot, respectively, to determine the delay time corresponding to the other slot;
and the delay processing unit 404 performs signal delay processing with different durations on different slot positions according to the delay time, so as to realize synchronous output of the waveform signals by the different slot positions.
Further, the apparatus further comprises:
a first slot position determining unit 405, which takes the slot position with the longest delay time as the first slot position; and performing signal delay processing with different time lengths on different slot positions according to the delay time length corresponding to the first slot position.
Further, the apparatus further comprises:
a signal delay unit 406, configured to use a delay time duration corresponding to the first slot as a time duration for performing signal delay processing on the reference slot; and determining delay difference values between the other different slot positions and the first slot position respectively, and taking the delay difference values as the time length for performing signal delay processing on the other different slot positions respectively.
Further, the apparatus further comprises:
the time determination unit 407 determines, according to the operating clock frequency of the fpga, the time for each slot to delay the signal sending time after receiving the trigger signal.
Further, the apparatus further comprises:
the slot position determining unit 408 determines a slot position where the level signal changes, and takes the slot position where the level signal changes as a slot position into which the current arbitrary waveform generator is inserted.
Further, the apparatus further comprises:
a reference slot position test unit 409, which inserts one or more arbitrary waveform generators into a part of slots in the chassis, and receives a first waveform signal output by the one or more arbitrary waveform generators through an oscilloscope; determining a second slot position with the fastest time for sending the first waveform signal; after the one or more arbitrary waveform generators are reinserted into the residual slot positions in the chassis, receiving second waveform signals output by the one or more arbitrary waveform generators through the oscilloscope until waveform signal output time corresponding to all slot positions to be tested is obtained; and comparing the output time corresponding to the second waveform signal with the output time of the second slot position to determine the reference slot position.
Further, the apparatus further comprises:
the output time determining unit 410 is configured to use the time when the oscilloscope acquires the waveform signals output by the different arbitrary waveform generators as the time when the different slot positions output the waveform signals respectively.
Fig. 5 is a schematic structural diagram of a signal synchronization output device according to an embodiment of the present application. As shown in fig. 5, the signal synchronization output apparatus includes,
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal;
acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively to determine the delay time corresponding to the other slot positions respectively;
and performing signal delay processing with different time lengths on different slot positions according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions.
An embodiment of the present application further provides a non-volatile computer storage medium storing computer-executable instructions, where the computer-executable instructions are configured to:
determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal;
acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively to determine the delay time corresponding to the other slot positions respectively;
and performing signal delay processing with different time lengths on different slot positions according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments of the apparatus, the device, and the nonvolatile computer storage medium, since they are substantially similar to the embodiments of the method, the description is simple, and for the relevant points, reference may be made to the partial description of the embodiments of the method.
The foregoing description of specific embodiments of the present application has been presented. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art to which the embodiments of the present application pertain. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A method for synchronously outputting signals, the method comprising:
determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal;
acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively to determine the delay time corresponding to the other slot positions respectively;
and performing signal delay processing with different time lengths on different slot positions according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions.
2. The method according to claim 1, wherein the performing signal delay processing with different durations for different slots according to the delay time specifically includes:
taking the slot position with the longest delay time as a first slot position;
and performing signal delay processing with different time lengths on different slot positions according to the delay time length corresponding to the first slot position.
3. The method according to claim 2, wherein the performing, according to the delay time duration corresponding to the first slot, signal delay processing of different slot lengths on different slots specifically includes:
taking the time delay duration corresponding to the first slot position as the time duration for performing signal time delay processing on the reference slot position; and
and determining delay difference values between the other different slot positions and the first slot position respectively, and taking the delay difference values as the time length for performing signal delay processing on the other different slot positions respectively.
4. The method according to claim 1, wherein the determining the delay times corresponding to the other slots respectively comprises:
and determining the time of sending out the signal by delaying after each slot position receives the trigger signal according to the working clock frequency of the field programmable gate array.
5. The method according to claim 1, wherein the determining the slot positions corresponding to different arbitrary waveform generators according to the received slot position determination signal specifically includes:
and determining the slot position where the level signal changes, and taking the slot position where the level signal changes as the slot position where the current arbitrary waveform generator is inserted.
6. The method according to claim 1, wherein the step of using the slot that first transmits the waveform signal as a reference slot comprises:
after one or more arbitrary waveform generators are inserted into partial slot positions in a chassis, receiving a first waveform signal output by the one or more arbitrary waveform generators through an oscilloscope;
determining a second slot position with the fastest time for sending the first waveform signal;
after the one or more arbitrary waveform generators are reinserted into the residual slot positions in the chassis, receiving second waveform signals output by the one or more arbitrary waveform generators through the oscilloscope until waveform signal output time corresponding to all slot positions to be tested is obtained;
and comparing the output time corresponding to the second waveform signal with the output time of the second slot position to determine the reference slot position.
7. The method according to claim 6, wherein the obtaining of the time when the different arbitrary waveform generators respectively output the waveform signals after receiving the trigger signal specifically comprises:
and taking the time of the oscillograph for acquiring the waveform signals output by the different arbitrary waveform generators as the time of respectively outputting the waveform signals by the different slot positions.
8. A signal synchronization output apparatus comprising:
the slot position determining unit is used for determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judging signal;
a reference slot position determination unit; acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
the delay time determining unit is used for comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively so as to determine the delay time corresponding to the other slot positions respectively;
and the delay processing unit is used for carrying out signal delay processing on different slot positions with different time lengths according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions.
9. A signal synchronization output apparatus comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal;
acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively to determine the delay time corresponding to the other slot positions respectively;
and performing signal delay processing with different time lengths on different slot positions according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions.
10. A non-transitory computer storage medium storing computer-executable instructions configured to:
determining slot positions corresponding to different arbitrary waveform generators according to the received slot position judgment signal;
acquiring the time for respectively outputting the waveform signals after the different arbitrary waveform generators receive the trigger signals, and taking the slot position which firstly sends out the waveform signals as a reference slot position;
comparing the time of outputting the waveform signals by other slot positions with the time of outputting the waveform signals by the reference slot position respectively to determine the delay time corresponding to the other slot positions respectively;
and performing signal delay processing with different time lengths on different slot positions according to the delay time so as to realize synchronous output of the waveform signals by the different slot positions.
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| CN115144736A (en) * | 2022-09-01 | 2022-10-04 | 合肥本源量子计算科技有限责任公司 | Quantum chip testing method and device and quantum computer |
-
2021
- 2021-12-15 CN CN202111533127.6A patent/CN114326925A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115144736A (en) * | 2022-09-01 | 2022-10-04 | 合肥本源量子计算科技有限责任公司 | Quantum chip testing method and device and quantum computer |
| CN115144736B (en) * | 2022-09-01 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum chip testing method and device and quantum computer |
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