CN110854184B - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN110854184B
CN110854184B CN201810876005.9A CN201810876005A CN110854184B CN 110854184 B CN110854184 B CN 110854184B CN 201810876005 A CN201810876005 A CN 201810876005A CN 110854184 B CN110854184 B CN 110854184B
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semiconductor device
material layer
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CN110854184A (zh
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刘暐昌
陈震
王献德
向往
塔威
方玲刚
薛尚
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制造方法。所述半导体元件包括第一栅极、栅介电层、一对第二栅极、第一间隙壁以及第二间隙壁。所述第一栅极配置于基底上。所述栅介电层配置于所述第一栅极与所述基底之间。所述一对第二栅极配置于所述基底上且分别位于所述第一栅极的二侧，其中所述一对第二栅极的顶面高于所述第一栅极的顶面。所述第一间隙壁配置于所述一对第二栅极的自所述第一栅极的顶面凸出的侧壁上，且覆盖所述第一栅极的顶面。所述第二间隙壁配置于所述栅介电层与所述一对第二栅极之间、所述第一栅极与所述一对第二栅极之间以及所述第一间隙壁与所述一对第二栅极之间。

Description

半导体元件及其制造方法
技术领域
本发明涉及一种半导体元件及其制造方法，且特别是涉及一种高电阻值栅极的顶面上不具有硅化物层的半导体元件及其制造方法。
背景技术
在一般常见的半导体元件(例如金属氧化物半导体(MOS)晶体管)中，为了提高元件的处理效能，通常会于导电区域(例如栅极、源极、漏极等)的表面上形成硅化物(silicide)层来降低所述区域的电阻值。
然而，对于需要具有高电阻值的元件来说，为了避免在对其他元件进行硅化物制作工艺时于其表面上形成硅化物层，通常会额外增加制作工艺步骤以于所述元件的表面上形成保护层。如此一来，将导致制作工艺步骤繁杂，且不易与一般常用的制作工艺整合在一起。
发明内容
本发明提供一种半导体元件，其中高电阻值栅极的顶面上不具有硅化物层。
本发明提供一种半导体元件的制造方法，其用以制造上述的半导体元件。
本发明的半导体元件包括第一栅极、栅介电层、一对第二栅极、第一间隙壁以及第二间隙壁。所述第一栅极配置于基底上。所述栅介电层配置于所述第一栅极与所述基底之间。所述一对第二栅极配置于所述基底上且分别位于所述第一栅极的二侧，其中所述一对第二栅极的顶面高于所述第一栅极的顶面。所述第一间隙壁配置于所述一对第二栅极的自所述第一栅极的顶面凸出的侧壁上，且覆盖所述第一栅极的顶面。所述第二间隙壁配置于所述栅介电层与所述一对第二栅极之间、所述第一栅极与所述一对第二栅极之间以及所述第一间隙壁与所述一对第二栅极之间。
在本发明的半导体元件的一实施例中，还包括第三间隙壁，其配置于所述一对第二栅极的远离所述第一栅极的侧壁上。
在本发明的半导体元件的一实施例中，所述第三间隙壁的材料与所述第一间隙壁的材料例如相同。
在本发明的半导体元件的一实施例中，还包括硅化物层，其配置于所述一对第二栅极的顶面上。
在本发明的半导体元件的一实施例中，所述一对第二栅极的顶面例如低于所述第二间隙壁的顶面，且所述半导体元件还包括配置于所述一对第二栅极的顶面上且位于所述第二间隙壁上的第四间隙壁，且所述硅化物层位于所述一对第二栅极的被暴露的顶面上。
在本发明的半导体元件的一实施例中，所述第三间隙壁的材料、所述第四间隙壁的材料与所述第一间隙壁的材料例如相同。
在本发明的半导体元件的一实施例中，所述第一间隙壁的材料例如为氮化物。
在本发明的半导体元件的一实施例中，所述第二间隙壁的材料例如为氧化物。
在本发明的半导体元件的一实施例中，所述一对第二栅极的自所述第一栅极的顶面凸出的侧壁的高度和所述第一栅极的宽度的比例例如大于2。
本发明的半导体元件的制造方法包括以下步骤：在基底上形成栅极结构，其中所述栅极结构包括位于所述基底上的栅介电层、位于所述栅介电层上的第一栅极以及位于所述第一栅极上的硬掩模层；在所述栅极结构的侧壁上形成第一间隙壁；分别于所述栅极结构的两侧的所述第一间隙壁上形成第二栅极，其中所述第二栅极的顶面高于所述第一栅极的顶面；移除所述硬掩模层；以及于所述第一间隙壁的自所述第一栅极的顶面凸出的侧壁上与所述第二栅极的侧壁上形成第二间隙壁，其中所述第二间隙壁覆盖所述第一栅极的顶面。
在本发明的半导体元件的制造方法的一实施例中，所述栅极结构的形成方法包括：在所述基底上依序形成栅介电材料层、栅极材料层与硬掩模材料层；以及进行图案化制作工艺，移除部分所述栅介电材料层、部分所述栅极材料层与部分所述硬掩模材料层。
在本发明的半导体元件的制造方法的一实施例中，所述第一间隙壁的形成方法包括：在所述基底上共形地形成间隙壁材料层；以及进行各向异性蚀刻制作工艺，移除部分所述间隙壁材料层而保留位于所述栅极结构的侧壁上的所述间隙壁材料层。
在本发明的半导体元件的制造方法的一实施例中，所述第二栅极的形成方法包括：在所述基底上共形地形成栅极材料层；以及进行各向异性蚀刻制作工艺，移除部分所述栅极材料层而保留位于所述栅极结构的侧壁上的所述栅极材料层。
在本发明的半导体元件的制造方法的一实施例中，在进行所述各向异性蚀刻制作工艺之后，位于所述栅极结构的侧壁上的所述栅极材料层的顶面例如低于所述硬掩模层的顶面。
在本发明的半导体元件的制造方法的一实施例中，所述第二间隙壁的形成方法包括：在所述基底上共形地形成间隙壁材料层；以及进行各向异性蚀刻制作工艺，移除部分间隙壁材料层而保留位于所述第一间隙壁的侧壁上、所述第一栅极的顶面上以及所述第二栅极的侧壁上的所述间隙壁材料层。
在本发明的半导体元件的制造方法的一实施例中，还包括于所述第二栅极的顶面上形成硅化物层。
在本发明的半导体元件的制造方法的一实施例中，所述第一间隙壁的材料例如为氧化物。
在本发明的半导体元件的制造方法的一实施例中，所述第二间隙壁的材料例如为氮化物。
在本发明的半导体元件的制造方法的一实施例中，所述硬掩模层的材料例如为氮化物。
在本发明的半导体元件的制造方法的一实施例中，所述硬掩模层的高度和所述第一栅极的宽度的比例例如大于2。
基于上述，在本发明中，第一栅极的顶面被第一间隙壁覆盖而不会有硅化物层形成于其上，因此可确保第一栅极具有符合需求的较高的电阻值。此外，由于形成于第一栅极上方且位于相对的第二间隙壁的侧壁上的第一间隙壁在形成的过程中会合并在一起而能够覆盖第一栅极的顶面，因此不需进行额外的制作工艺而可以达到保护第一栅极的顶面的目的。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A至图1D为本发明实施例所绘示的半导体元件的制造流程剖面示意图；
图2为图1A的结构的上视示意图；
图3为本发明另一实施例所绘示的半导体元件的剖面示意图。
具体实施方式
在下文中，将参照附图来说明本发明实施例。在附图中，为清楚说明，可能夸大或缩小各元件的形状、尺寸、比例等。
图1A至图1D为依照本发明实施例所绘示的半导体元件的制造流程剖面示意图。图2为图1A的结构的上视示意图。首先，请同时参照图1A与图2，提供基底100。基底100例如是硅基底。在本实施例中，基底100具有周边区100a与存储器区100b。周边区100a可用以形成逻辑元件、电阻元件、电容元件等。存储器区100b用以形成各种存储器元件。然后，在周边区100a的基底100上形成栅极结构102，以及于存储器区100b的基底100上形成栅极结构104。以下将对此做进一步地说明。
请参照图2，在本实施例中，栅极结构102的末端部分的宽度大于中间部分的宽度而成「I」字状，而栅极结构104的末端部分的宽度与中间部分的宽度则实质上相等而呈长条状。由沿剖线A-A与剖线B-B的剖面可明显看出，栅极结构102的末端部分的宽度明显大于中间部分的宽度，以利于在后续制作工艺中形成与栅极结构102连接的接触窗。
在本实施例中，栅极结构102与栅极结构104的形成方法例如包括下列步骤。首先，在基底100上形成栅介电材料层(例如氧化物层)。然后，移除存储器区100b中的栅介电材料层。接着，在周边区100a中的栅介电材料层上形成掩模层。而后，在存储器区100b中的基底100上依序形成第一氧化物层、氮化物层与第二氧化物层，即一般所熟知的ONO堆叠结构。接着，移除掩模层，并于基底100上依序形成栅极材料层与硬掩模材料层。然后，进行图案化制作工艺，移除部分介电材料层、部分栅极材料层与部分硬掩模材料层，以于周边区100a的基底上形成包括栅介电层102a、栅极102b与硬掩模层102c的栅极结构102，以及于存储器区100b的基底100上形成包括穿隧介电层104a、电荷存储层104b、电荷阻挡层104c、控制栅极104d与硬掩模层104e的栅极结构104。或者，在其他实施例中，也可以是先形成存储器区100b中的ONO堆叠结构，再形成周边区100a中的栅介电材料层。
特别一提的是，为了有利于后续制作工艺，将栅极结构104的中间部分形成为硬掩模层102c的高度和栅极102b的宽度的比例大于2的形式。举例来说，可通过控制所形成的硬掩模材料层的厚度或控制图案化制作工艺中所形成的栅极102b的宽度来达成上述的比例。后续将对此做进一步的说明。
然后，请参照图1B，在栅极结构102的侧壁上形成间隙壁106，以及于栅极结构104的侧壁上形成间隙壁108。在本实施例中，间隙壁106与间隙壁108的材料例如为氧化物。在其他实施例中，间隙壁106与间隙壁108也可以具有由氧化物层与氮化物层构成的复合结构。在本实施例中，间隙壁106与间隙壁108的形成方法包括以下步骤。首先，在基底100上共形地形成间隙壁材料层。然后，进行各向异性蚀刻制作工艺，移除部分间隙壁材料层而保留位于栅极结构102与栅极结构104的侧壁上的间隙壁材料层，且暴露出栅极结构102与栅极结构104的顶面(即硬掩模层102c与硬掩模层104e的顶面)。
接着，请参照图1C，分别于栅极结构102的两侧的间隙壁106上形成栅极110，以及于栅极结构104的一侧的间隙壁108上形成栅极112。在存储器区100b中，栅极112可作为选择栅极之用。栅极110与栅极112的形成方法包括以下步骤。首先，在基底100上共形地形成栅极材料层(如金属层或多晶硅层)。然后，进行各向异性蚀刻制作工艺，移除部分栅极材料层而保留位于栅极结构102与栅极结构104的侧壁上的栅极材料层，且暴露出栅极结构102与栅极结构104的顶面(即硬掩模层102c与硬掩模层104e的顶面)。在本实施例中，在进行上述各向异性蚀刻制作工艺之后，栅极110的顶面高于栅极102b的顶面，且与间隙壁106的顶面实质上共平面。
然后，移除硬掩模层102c与硬掩模层104e。移除硬掩模层102c与硬掩模层104e的方法例如是以磷酸作为蚀刻液来进行蚀刻制作工艺。在本实施例中，由于硬掩模层102c的高度和栅极102b的宽度的比例大于2，因此在移除硬掩模层102c之后，形成于栅极102b上方且位于相对的间隙壁106之间的空间的深宽比会大于2。
此外，在本实施例中，位于存储器区100b中的栅极112的高度小于位于周边区100a中的栅极110的高度，且在存储器区100b中栅极112仅形成于栅极结构104的一侧。因此，可在适当的时机于周边区100a的基底100上形成掩模层来覆盖基底100上的元件，然后对存储器区100b中的间隙壁108与栅极112进行蚀刻制作工艺来形成所需的结构。上述制作工艺步骤为本领域技术人员所熟知，在此不另行说明。在另一实施例中，位于存储器区100b中的栅极112的高度可与位于周边区100a中的栅极110的高度相同，因此仅需将栅极112的一侧的间隙壁108与栅极112移除即可，而不需调整另一侧的间隙壁108与栅极112的高度。
然后，请参照图1D，于间隙壁106的自栅极102b的顶面凸出的侧壁上与栅极110的侧壁上形成间隙壁114，以及于间隙壁108的自栅极104d的顶面凸出的侧壁上与栅极112的侧壁上形成间隙壁116。在本实施例中，间隙壁114与间隙壁116的形成方法包括以下步骤。首先，在基底100上共形地形成间隙壁材料层。然后，进行各向异性蚀刻制作工艺，移除部分间隙壁材料层而保留位于间隙壁106、栅极110、间隙壁108、栅极112的侧壁上的间隙壁材料层，且暴露出栅极102b的部分顶面、栅极110的顶面、栅极104d的部分顶面与栅极112的顶面。
在本实施例中，在栅极结构102的中间部分处(参照沿剖线B-B的剖面)，由于栅极102b上方且位于相对的间隙壁106之间的空间的深宽比较大(例如大于2)，因此形成于相对的间隙壁106上的间隙壁114会合并在一起而覆盖栅极102b的顶面。此外，在栅极结构102的末端部分处(参照沿剖线A-A的剖面)，由于栅极102b具有较大的宽度而使得栅极102b上方且位于相对的间隙壁106之间的空间的深宽比较小(例如小于或等于2)，因此形成于相对的间隙壁106上的间隙壁114不会合并在一起而暴露出栅极102b的部分顶面。
之后，进行硅化物制作工艺(silicide process)，在暴露出的栅极102b的顶面、暴露出的栅极110的顶面、暴露出的栅极104d的顶面与暴露出的栅极112的顶面上形成硅化物层120。由于栅极结构102的中间部分处的栅极102b的上方已被间隙壁114覆盖(如沿剖线B-B的剖视图所示)，因此在上述硅化物制作工艺中，硅化物层120不会形成于栅极结构102的中间部分处的栅极102b的顶面上。
在本实施例中，硅化物层120形成于栅极结构102的末端部分处的栅极102b的部分顶面上以及栅极104d的部分顶面，因此在后续形成与其连接的接触窗时，接触窗可与硅化物层120连接而使元件有更佳的电性表现。此外，由于栅极结构102的中间部分处的栅极102b的顶面上已被间隙壁114覆盖而未形成有硅化物层120，因此可确保此部分的栅极102b具有符合需求的较高的电阻值。
另外，在本实施例中，通过使栅极结构102的中间部分处的栅极102b上方且位于相对的间隙壁106之间的空间的深宽比较大(例如大于2)，使得间隙壁114在形成的过程中在此空间合并而覆盖栅极102b的顶面，因此不需进行额外的制作工艺即可达到保护栅极102b的顶面的目的，且可与一般的存储器制作工艺整合在一起，意即不需调整现有的制作工艺步骤即可达成上述目的。
在本实施例中，栅极110的顶面高于栅极102b的顶面，且与间隙壁106的顶面实质上共平面，但本发明不限于此。在其他实施例中，在形成栅极110时，可视实际需求而使栅极110的顶面低于间隙壁106的顶面但仍高于栅极102b的顶面。因此，在形成间隙壁114时，间隙壁114还会形成于的间隙壁106的远离栅极102b的侧壁上，如图3所示。如此一来，可进一步避免栅极110上的硅化物层120与栅极120b上的硅化物层120接触而产生短路的问题。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种半导体元件，其特征在于，包括：
第一栅极，配置于基底上；
栅介电层，配置于所述第一栅极与所述基底之间；
一对第二栅极，配置于所述基底上且分别位于所述第一栅极的二侧，其中所述一对第二栅极的顶面高于所述第一栅极的顶面；
第一间隙壁，配置于所述一对第二栅极的自所述第一栅极的顶面凸出的侧壁上，且覆盖所述第一栅极的顶面，所述第一间隙壁包括两个合并在一起的间隔物，所述两个合并在一起的间隔物的中间具有凹部；以及
第二间隙壁，配置于所述栅介电层与所述一对第二栅极之间、所述第一栅极与所述一对第二栅极之间以及所述第一间隙壁与所述一对第二栅极之间。
2.如权利要求1所述的半导体元件，还包括第三间隙壁，配置于所述一对第二栅极的远离所述第一栅极的侧壁上。
3.如权利要求2所述的半导体元件，其中所述第三间隙壁的材料与所述第一间隙壁的材料相同。
4.如权利要求2所述的半导体元件，还包括硅化物层，配置于所述一对第二栅极的顶面上。
5.如权利要求4所述的半导体元件，其中所述一对第二栅极的顶面低于所述第二间隙壁的顶面，且所述半导体元件还包括配置于所述一对第二栅极的顶面上且位于所述第二间隙壁上的第四间隙壁，且所述硅化物层位于所述一对第二栅极的被暴露的顶面上。
6.如权利要求5所述的半导体元件，其中所述第三间隙壁的材料、所述第四间隙壁的材料与所述第一间隙壁的材料相同。
7.如权利要求1所述的半导体元件，其中所述第一间隙壁的材料包括氮化物。
8.如权利要求1所述的半导体元件，其中所述第二间隙壁的材料包括氧化物。
9.如权利要求1所述的半导体元件，其中所述一对第二栅极的自所述第一栅极的顶面凸出的侧壁的高度和所述第一栅极的宽度的比例大于2。
10.一种半导体元件的制造方法，其特征在于，包括：
在基底上形成栅极结构，其中所述栅极结构包括位于所述基底上的栅介电层、位于所述栅介电层上的第一栅极以及位于所述第一栅极上的硬掩模层；
在所述栅极结构的侧壁上形成第一间隙壁；
分别于所述栅极结构的两侧的所述第一间隙壁上形成第二栅极，其中所述第二栅极的顶面高于所述第一栅极的顶面；
移除所述硬掩模层；以及
在所述第一间隙壁的自所述第一栅极的顶面凸出的侧壁上与所述第二栅极的侧壁上形成第二间隙壁，其中所述第二间隙壁覆盖所述第一栅极的顶面，所述第二间隙壁包括两个合并在一起的间隔物，所述两个合并在一起的间隔物的中间具有凹部。
11.如权利要求10所述的半导体元件的制造方法，其中所述栅极结构的形成方法包括：
在所述基底上依序形成栅介电材料层、栅极材料层与硬掩模材料层；以及
进行图案化制作工艺，移除部分所述栅介电材料层、部分所述栅极材料层与部分所述硬掩模材料层。
12.如权利要求10所述的半导体元件的制造方法，其中所述第一间隙壁的形成方法包括：
在所述基底上共形地形成间隙壁材料层；以及
进行各向异性蚀刻制作工艺，移除部分所述间隙壁材料层而保留位于所述栅极结构的侧壁上的所述间隙壁材料层。
13.如权利要求10所述的半导体元件的制造方法，其中所述第二栅极的形成方法包括：
在所述基底上共形地形成栅极材料层；以及
进行各向异性蚀刻制作工艺，移除部分所述栅极材料层而保留位于所述栅极结构的侧壁上的所述栅极材料层。
14.如权利要求13所述的半导体元件的制造方法，其中在进行所述各向异性蚀刻制作工艺之后，位于所述栅极结构的侧壁上的所述栅极材料层的顶面低于所述硬掩模层的顶面。
15.如权利要求10所述的半导体元件的制造方法，其中所述第二间隙壁的形成方法包括：
在所述基底上共形地形成间隙壁材料层；以及
进行各向异性蚀刻制作工艺，移除部分间隙壁材料层而保留位于所述第一间隙壁的侧壁上、所述第一栅极的顶面上以及所述第二栅极的侧壁上的所述间隙壁材料层。
16.如权利要求10所述的半导体元件的制造方法，还包括在所述第二栅极的顶面上形成硅化物层。
17.如权利要求10所述的半导体元件的制造方法，其中所述第一间隙壁的材料包括氧化物。
18.如权利要求10所述的半导体元件的制造方法，其中所述第二间隙壁的材料包括氮化物。
19.如权利要求10所述的半导体元件的制造方法，其中所述硬掩模层的材料包括氮化物。
20.如权利要求10所述的半导体元件的制造方法，其中所述硬掩模层的高度和所述第一栅极的宽度的比例大于2。
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