CN110556343A - Packaging structure and packaging process for preventing layering - Google Patents
Packaging structure and packaging process for preventing layering Download PDFInfo
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- CN110556343A CN110556343A CN201910961854.9A CN201910961854A CN110556343A CN 110556343 A CN110556343 A CN 110556343A CN 201910961854 A CN201910961854 A CN 201910961854A CN 110556343 A CN110556343 A CN 110556343A
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- base island
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- packaging
- delamination
- electroplating
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 53
- 238000012858 packaging process Methods 0.000 title claims abstract description 37
- 238000009713 electroplating Methods 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052802 copper Inorganic materials 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 31
- 238000005553 drilling Methods 0.000 claims abstract description 27
- 230000008569 process Effects 0.000 claims abstract description 22
- 230000032798 delamination Effects 0.000 claims description 51
- 238000005538 encapsulation Methods 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 230000002265 prevention Effects 0.000 claims description 25
- 230000007704 transition Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 7
- 229910010165 TiCu Inorganic materials 0.000 claims description 5
- 229910001258 titanium gold Inorganic materials 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 22
- 238000007747 plating Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 7
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- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
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- 238000006303 photolysis reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
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- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
the invention provides a packaging structure for preventing layering and a packaging process, which adopts the technical processes of substrate preparation, chip mounting, first packaging, copper bump exposure, drilling, electroplating, second packaging, carrier plate peeling and the like, adopts a fastener to be packaged in a plastic package body in a plastic package manner, the fastener is fixedly connected with a base island, so that the contact area between the base island and the plastic package body is increased, the bonding degree between the plastic package body and the base island is improved, the fastener is arranged at any position on the base island where other electronic components are not influenced, the position can be flexibly adjusted, the packaging structure is suitable for chips with different packaging sizes and different sizes in the field of chip packaging, the fastener increases the contact area between the base island and the plastic package body, improves the heat conduction on the base island, can improve the heat dissipation efficiency of the base island and the chip connected with the base island, and effectively avoids the phenomenon that materials with different thermal expansion coefficients are separated by layering due to high temperature, thereby improving the reliability of the chip package.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging process for preventing layering.
background
With the development of electronic products, semiconductor technology has been widely used to manufacture memory, Central Processing Unit (CPU), Liquid Crystal Display (LCD), Light Emitting Diode (LED), laser diode, and other devices or chip sets.
Since electronic components such as semiconductor components, micro-electromechanical components (MEMS) or optoelectronic components have minute and fine circuits and structures, in order to prevent dust, acid-base substances, moisture, oxygen, etc. from contaminating or eroding the electronic components, thereby affecting their reliability and life, it is necessary to provide the electronic components with related functions such as electrical energy creation, signal transmission, heat dissipation, protection and support, etc. by packaging technology.
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures such as inspection, Test, packaging and the like, and finally warehousing and shipping.
In the field of chip packaging, the adopted packaging materials are more in variety, the physical properties of different materials are different, and particularly the thermal expansion coefficients of different materials are different, so that parts of different materials which are in mutual contact have obvious influence, for a large-size packaging body, the size of a chip is larger, the size of a base island is larger than that of the chip, a layering phenomenon easily occurs in a strict working environment or test after the chip is packaged by a chip packaging piece, particularly, the heat on the chip cannot be timely dissipated, the temperature on the chip and the plastic packaging material can be gathered, the temperature on the chip and the plastic packaging material is not uniformly dispersed, the thermal expansion efficiency is increased, the layering separation phenomenon of the chip and a frame or the base island is more easily caused, and the performance and the effective use of a product are seriously influenced.
disclosure of Invention
Aiming at the defects in the prior art, the invention provides a packaging structure and a packaging process for preventing layering.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
the utility model provides a packaging structure of prevention layering, includes a plastic envelope body, has at least an electronic component plastic envelope in the plastic envelope body, at least one base island and at least one pin have on the electronic component, the top of pin exposes in the surface of the plastic envelope body, the surface of base island is equipped with at least one fastener, fixed connection between fastener and the base island, and the fastener plastic envelope is in the plastic envelope body.
furthermore, the fastener comprises a connecting piece with one end connected with the base island, and the other end of the connecting piece is plastically packaged in the plastic package body.
furthermore, the fastener still includes the ear spare that is used for the solid plastic-sealed body of card, the ear spare with the one end of keeping away from the base island on the connecting piece is connected fixedly.
Furthermore, a chip is arranged on the electronic component, the back face of the chip is attached to the base island, a gasket is arranged in the plastic package body, the gasket is not connected with the base island, the pins are respectively arranged on the base island and the gasket, and the chip and the gasket are connected through a rewiring layer.
Further, the gasket and the base island are located on the same plane and have the same thickness, and the gasket and the pins on the base island are located on the same side of the plane formed by the gasket and the base island.
Further, the pin is an outer pin.
Furthermore, the redistribution layer is parallel to the base island, a sunken table with a hat-shaped cross section is arranged at one end, connected with the gasket, of the redistribution layer, the sunken table protrudes towards the direction of the gasket, and the table top of the sunken table is attached to and fixed with the surface of the gasket.
Furthermore, the base island and the gasket are made of copper metal.
Furthermore, the connecting piece and the ear piece are made of metal capable of being electroplated.
furthermore, the chip and the base island are in transition connection through a metal transition layer, and the material of the metal transition layer comprises at least one of TiNiAg, TiAu or TiCu.
A packaging process of a packaging structure for preventing delamination comprises the following steps:
The method comprises the following steps: preparing a substrate, namely placing the back surface of the substrate on a carrier plate, wherein the carrier plate is used for supporting and protecting, pins on the substrate are exposed on the back surface of the substrate, a base island protruding out of the surface of the substrate and a gasket which is not in contact with the base island are arranged on one surface, far away from the carrier plate, of the substrate, and the base island and the gasket are respectively electrically connected with the two pins;
step two: chip mounting, namely loading the back surface of a chip which finishes the BUMP process on one surface of the base island, which is far away from the substrate, mutually attaching the chip and the base island, wherein a copper BUMP is arranged on the active surface of the chip which finishes the BUMP process, and the active surface of the chip is back to the substrate;
Step three: the first encapsulation is carried out on the carrier plate to form a first plastic package body, and the base island, the gasket, the pins, the chip and the copper bumps are all plastically packaged in the first plastic package body;
Step four: exposing the copper bump, and operating the first plastic package body in a grinding, etching or laser drilling mode to expose the copper bump on the active surface of the chip on the outer surface of the first plastic package body;
Step five: drilling holes, namely drilling holes on one surface, positioned on the exposed copper bump, of the first plastic package body, wherein the drilling holes are divided into two types, one type is an anti-layering locking hole, the other type is a functional through hole, the bottom of the anti-layering locking hole extends to the surface of the base island, part of the outer surface of the base island is exposed at the bottom of the anti-layering locking hole, the bottom of the functional through hole extends to the surface of the gasket, and the outer surface of the gasket is exposed at the bottom of the functional through hole;
Step six: electroplating, wherein the electroplating comprises two parts, one part is electroplating of the redistribution layer, and the other part is electroplating of the connecting piece;
Electroplating of a rewiring layer: carrying out metal electroplating connection between the copper bump of the chip and the gasket to form a rewiring layer, wherein one end of the rewiring layer is fixedly connected with the copper bump of the chip, the other end of the rewiring layer extends to the functional through hole along the outer surface of the first plastic package body and extends along the hole wall of the functional through hole, and is fixedly connected with the gasket exposed at the bottom of the functional through hole, and the hole wall of the functional through hole is covered with a layer of electroplated layer to form a metal sunken table with a hat-shaped section;
Electroplating the connecting piece: electroplating is carried out in each anti-layering lockhole to form a connecting piece, the bottom end of the connecting piece is fixedly connected with the base island, and the connecting piece formed by electroplating is filled in the whole anti-layering lockhole or covers the inner wall of the whole anti-layering lockhole;
Step seven: performing second encapsulation on the basis of the first plastic package body formed by the first encapsulation to form a plastic package body, wherein the plastic package body comprises the first plastic package body, and the redistribution layer, the concave table and the connecting piece are all positioned in the plastic package body;
Step eight: and (3) stripping the carrier plate used in the step one, and exposing the pins after stripping to form the outer pins.
Further, in the first step, the material of the carrier includes at least one of a metal or alloy plate, a BT material, an FR-4 material, a silicon-based material, an EMC material, a glass material, or a film material.
further, in the second step, a metal transition layer is arranged between the chip and the base island for transition connection, and the material of the metal transition layer comprises at least one of TiNiAg, TiAu or TiCu.
further, in step five, the drilling mode includes a laser drilling mode, a mechanical drilling mode or an etching mode.
Further, in the fifth step, a plurality of uniformly distributed delamination-proof lock holes are formed in one surface of the first plastic package body, which is located on the exposed copper bump.
Further, in the sixth step, the method further comprises ear piece electroplating, when or after the connecting piece is electroplated, one end, far away from the base island, of the connecting piece is electroplated to form the ear piece, the ear piece is attached to the surface of the first plastic package body, the thickness of the ear piece is the same as that of the redistribution layer, the ear piece is parallel to the base island, the ear piece and the connecting piece are integrated, and after the second-time encapsulation in the seventh step, the whole ear piece is located in the plastic package body.
Compared with the prior art, the invention has the following beneficial effects:
The invention provides a packaging structure for preventing delamination, which adopts a fastener to be plastically packaged in a plastic package body, the fastener is fixedly connected with a base island, thereby increasing the contact area between the base island and the plastic package body, greatly improving the bonding degree between the plastic package body and the base island, designing the fastener into a structure of a connecting piece and an ear piece, the base island is connected with the ear piece through the connecting piece, the ear piece only clamps and fixes the plastic package body in the plastic package body, and due to the action of the connecting piece, the base island at the back of a chip or a frame used for replacing the base island in actual use is tightly locked with the plastic package body, thereby effectively preventing the delamination between the chip and the frame or the base island, and also preventing the delamination between the plastic package body and the base island or the frame, in the structure, the fastener can be installed at any place on the island without influencing other electronic components, and the position can be flexibly adjusted, on all encapsulation sizes and the not chip of equidimension that is applicable to the chip package field, because the effect of fastener, increase area of contact between island and the plastic-sealed body, also can improve the heat conduction on the island, thereby make the temperature in the encapsulation body more even, can not produce the phenomenon that temperature deviation is big, also can improve the efficiency that heat energy gived off on the island and the chip of being connected with the island, thereby when reliability test and the practical application in later stage, effectively avoid producing the phenomenon that the layering breaks away from because of high temperature leads to producing between different thermal expansion coefficient's the material, thereby improve the reliability of chip package, promote the performance of chip.
Drawings
FIG. 1 is a schematic diagram illustrating steps of a packaging process of a delamination prevention package structure according to the present invention;
FIG. 2 ~ is a flowchart of a delamination prevention package and a packaging process according to a first embodiment of the invention;
FIG. 10 is a schematic structural diagram of a delamination prevention package structure according to an embodiment of the invention;
FIG. 11 is a schematic structural diagram illustrating a plating state in a packaging process of a delamination prevention package structure according to a second embodiment;
FIG. 12 is a top view of FIG. 11;
FIG. 13 is a schematic diagram illustrating a plating state in a packaging process of a delamination prevention package structure according to a third embodiment;
FIG. 14 is a top view of FIG. 13;
FIG. 15 is a schematic structural diagram illustrating a plating state in a packaging process of a delamination prevention packaging structure according to a fourth embodiment;
FIG. 16 is a top view of FIG. 15;
FIG. 17 is a schematic structural diagram illustrating a plating state in a packaging process of a delamination prevention packaging structure according to a fifth embodiment;
fig. 18 is a top view of fig. 17.
Detailed Description
the present invention will now be described in connection with particular embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functionality throughout.
The directional phrases used in this disclosure include, for example: upper, lower, left, right, front, rear, inner, outer, front, rear, side, etc. are directions with reference to the drawings only, and the embodiments described below by referring to the drawings and directional terms used are exemplary only for explaining the present invention, and are not to be construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials that one of ordinary skill in the art would recognize for other processes and/or uses of other materials.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a packaging process of a delamination prevention package structure according to the present invention.
The packaging process of the packaging structure for preventing delamination comprises the following steps:
S1: preparing a substrate; s2: chip mounting; s3: first packaging; s4: exposing the copper bump; s5: drilling; s6: electroplating; s7: second encapsulation and S8: and stripping the carrier plate. The above steps are described in detail below with reference to the accompanying drawings and embodiments.
[ EXAMPLES one ]
A packaging process of a packaging structure for preventing delamination comprises the following steps:
Referring to fig. 2 ~, fig. 2 ~, fig. 9, a process flow diagram of a delamination prevention package structure and a packaging process according to a first embodiment of the invention, and fig. 10, a structure diagram of a delamination prevention package structure according to a first embodiment of the invention.
Regarding step S1: and (4) preparing a substrate.
as shown in fig. 2, fig. 2 is a schematic structural diagram of a substrate and a carrier.
The method comprises the steps of placing the back surface of a substrate a on a carrier plate b, wherein the carrier plate b is made of at least one of metal or alloy plate materials, BT materials, FR-4 materials, silicon-based materials, EMC materials, glass materials or film materials, the carrier plate b is used for supporting and protecting, two pins 40 are embedded in the substrate a, are exposed on the back surface of the substrate a, are in contact with the carrier plate b and are attached to the carrier plate b, a base island 30 protruding out of the surface of the substrate a and a gasket 60 not in contact with the base island 30 are arranged on one surface, far away from the carrier plate b, of the substrate a, the base island 30 and the gasket 60 are electrically connected with the two pins 40 in the substrate a respectively, the base island 30 and the gasket 60 are located on the same horizontal plane, are made of metal materials and are made of copper pads.
The substrate a and the carrier plate b are bonded through glue, soluble matters or meltable matters, such as hydrogel, pyrolytic gel or photolytic gel, so that the substrate a and the carrier plate b can be peeled off conveniently in the later period.
Among them, hydrogels (hydrogels) are a very hydrophilic three-dimensional network structure gel which rapidly swells in water and can hold a large volume of water in this swollen state without dissolution, and can swell and hold a large amount of water due to the presence of a crosslinked network, and the amount of water absorption is closely related to the degree of crosslinking. The higher the degree of crosslinking, the lower the water absorption. This property is very much like a soft tissue. The water content in the hydrogel can be as low as a few percent, and can also be as high as 99 percent. The gel is neither a completely solid nor a completely liquid in its aggregate state. The behavior of a solid is that it can maintain a certain shape and volume under certain conditions, and the behavior of a liquid is that a solute can diffuse or permeate from the hydrogel. The hydrogel can be removed by heating in water.
The pyrolytic gel is a solvent adhesive, has certain adhesive force at normal temperature, can play a role in positioning and supporting, can disappear only by heating the temperature to a set temperature, can realize simple stripping, has less residues and does not pollute an adherend.
the photodecomposition glue has certain adhesive force, can play a role in positioning and supporting, can be subjected to photodecomposition reaction after being irradiated by light to be changed into water-soluble glue, and can realize simple stripping.
Regarding step S2: and (5) chip mounting.
As shown in fig. 3, fig. 3 is a schematic diagram of a chip mounting structure.
The back surface of the chip 21 having completed the BUMP process is loaded on the side of the base island 30 away from the substrate a (the BUMP process of the chip is mature in technology, common knowledge, and not necessary technical features for solving the technical problems of the present invention, so detailed description is not given here), the chip 21 and the base island 30 are attached to each other, the active surface of the chip 21 having completed the BUMP process has a copper BUMP 21a, the active surface of the chip 21 faces away from the substrate a, the chip 21 and the base island 30 are transitionally connected by disposing a metal transition layer, and the material of the metal transition layer includes at least one of TiNiAg, TiAu or TiCu.
Because the back of the chip 21 is usually made of pure silicon material and can not be connected with other metals in an infiltration manner, when the chip 21 is mounted on the base island 30, a metal transition layer is arranged between the chip 21 and the base island 30 for excessive connection, so that the connection performance and the conductivity are improved, the phenomenon that the chip 21 is separated from the base island 30 at the later stage to cause the damage of a packaging structure is avoided, and the defective rate is greatly reduced.
Regarding step S3: and (5) packaging for the first time.
as shown in fig. 4, fig. 4 is a schematic structural diagram of the first encapsulation after the chip is mounted.
And performing first encapsulation on the carrier b to form a first plastic package body 10a, wherein the base island 30, the pad 60, the pin 40, the chip 21 and the copper bump 21a are all encapsulated in the first plastic package body 10a and are not in contact with the external atmosphere, and the material of the first plastic package body 10a is any plastic package material known to those skilled in the art, such as a resin material.
Regarding step S4: the copper bump is exposed.
As shown in fig. 5, and with reference to fig. 4, fig. 5 is a schematic structural view illustrating the exposed copper bump on the chip.
The outer surface of the first plastic package body 10a near the copper bump 21a is cut by grinding, etching or laser drilling until the copper bump 21a is exposed to the surface of the first plastic package body 10a and exposed to the atmosphere, and the outer surface of the first plastic package body 10a near the copper bump 21a is cut to form a plane parallel to the base island 30, see the portion above the dotted line y in fig. 4 and 5.
regarding step S5: and (6) drilling.
As shown in fig. 6 and 10, fig. 6 is a structural diagram illustrating a drilling state, and fig. 10 is a structural diagram illustrating a package structure for preventing delamination according to a first embodiment of the present invention.
Drilling is performed on one surface of the first plastic package body 10a, which is located on the exposed copper bump 21a, and the drilling is divided into two types, one type is an anti-delamination lock hole c, and the other type is a functional via hole d.
The two types of drilling are performed by adopting laser, mechanical or etching modes, the bottom of the delamination-proof lock hole c extends to the surface of the base island 30, part of the outer surface of the base island 30 is exposed at the bottom of the delamination-proof lock hole c, the central axis of the delamination-proof lock hole c is perpendicular to the surface of the base island 30, during drilling, operation is convenient, production efficiency is improved, but in the actual operation process, the central axis of the delamination-proof lock hole c and the surface of the base island 30 can form an inclined angle rather than a perpendicular state, the delamination-proof effect brought by electroplating at the later stage of the delamination-proof lock hole c with the inclined angle is better, in an effective unit volume, the contact surface between electroplated metal and the first plastic package body 10a can be increased after electroplating of the delamination-proof lock hole c with the inclined angle, and only in specific operation, the inclined delamination-proof lock hole c is drilled more difficult than the perpendicular lock hole c, therefore, as can be easily understood by those skilled in the art, the delamination prevention locking hole c is only for facilitating the subsequent electroplating, and the electroplated metal can smoothly pass through the first plastic package body 10a to contact the base island 30, so that the delamination prevention locking hole c with any shape and size is within the protection scope of the present invention.
The anti-layering locking holes c can be uniformly formed in the first plastic package body 10a, production and manufacturing are facilitated, even arrangement is not needed in the actual production process, and the position of each anti-layering locking hole c can be properly adjusted according to the difficulty of actual operation or the normal operation of the next procedure.
in this embodiment, the anti-delamination lock hole c is formed in a shape of a plurality of parallel linear holes, and a central axis of the anti-delamination lock hole c is perpendicular to the base island 30.
The bottom of function via hole d extends to the surface of gasket 60, and the surface of gasket 60 exposes in the bottom of function via hole d, function via hole d is in directly over gasket 60, the axis of function via hole d is parallel with the plane that gasket 60 was located, function via hole d is cylindrical, or for the cuboid, or for waist type hole all can, the hole shape listed here, be convenient for implement, and improve production efficiency's structure, of course, for the convenience of the operation of next process, or improve production efficiency, function via hole d also can be the hole of other shapes.
the delamination prevention locking hole c and the functional via hole d can be performed simultaneously.
Regarding step S6: and (4) electroplating.
Referring to fig. 7 and 10, fig. 7 is a schematic structural diagram illustrating an electroplating state, and fig. 10 is a schematic structural diagram illustrating a package structure for preventing delamination according to an embodiment of the invention.
and performing metal electroplating connection between the copper bump 21a on the chip 21 and the gasket 60 to form a redistribution layer 70, wherein one end of the redistribution layer 70 is fixedly connected with the copper bump 21a of the chip 21, the other end of the redistribution layer extends to the functional via hole d along the outer surface of the first plastic package body 10a and extends along the hole wall of the functional via hole d, and is fixedly connected with the gasket 60 exposed at the bottom of the functional via hole d, the hole wall of the functional via hole d is covered with a layer of electroplating layer to form a metal sunken table 71 with a hat-shaped section, the sunken table 71 protrudes towards the direction of the gasket 60, and the table surface of the sunken table 71 and the surface of the gasket 60 are mutually attached and fixed.
electroplating is carried out in each anti-layering lock hole c, a connecting piece 51 formed by electroplating around the inner wall of the anti-layering lock hole c is cylindrical and is closely attached to and connected with the inner wall of the anti-layering lock hole c, the bottom of the anti-layering lock hole c is also electroplated while electroplating is carried out around the inner wall of the anti-layering lock hole c, a formed electroplated layer is fixedly connected with the base island 30, and the electroplated layer and the connecting piece 51 are integrated.
In the actual operation process, the anti-delamination lock hole c can be filled with the electroplated layer to form a strip-shaped connecting piece 51 (the strip-shaped connecting piece 51 is not shown in the figure), so that the electroplating efficiency is improved, and the operation is convenient.
The redistribution layer 70 and the connection 51 can be formed by electroplating at the same time.
Further, electroplating the ear piece 52, and electroplating a circle of electroplating layer on the peripheral edge of one end of the connecting piece 51 far away from the base island 30 while or after electroplating the connecting piece 51 to form the ear piece 52, wherein the ear piece 52 is integrated with the connecting piece 51, and the connecting piece 51 is attached to the outer surface of the first plastic package body 10a and is located on the same horizontal plane with the redistribution layer 70.
In the present embodiment, the ear pieces 52 of two adjacent connecting members 51 do not contact each other.
Regarding step S7: and (5) second packaging.
Referring to fig. 8 in conjunction with fig. 7, fig. 8 is a structural diagram illustrating a second encapsulation state.
The second encapsulation is performed on the basis of the first encapsulation body 10a formed by the first encapsulation to form the encapsulation body 10, the material of the encapsulation body 10 is the same as that used for the first encapsulation body 10a, so that a delamination phenomenon is not easily generated in the later use process, the encapsulation body 10 includes the first encapsulation body 10a, the encapsulation body 10 is integrated with the first encapsulation body 10a (since the encapsulation body 10 is encapsulation performed on the basis of the first encapsulation body 10a, the first encapsulation body 10a is contained in the encapsulation body 10, so that the mark "10 a" is not shown in fig. 8, and only the mark "10" is marked), and the redistribution layer 70, the recessed table 71, the connecting member 51 and the ear piece 52 are all located in the encapsulation body 10.
regarding step S8: and stripping the carrier plate.
referring to fig. 9, fig. 9 is a schematic structural diagram of a state after the carrier is peeled off.
The carrier plate b used in step S1 is peeled off, and the peeling process is well-known in the art and is a common process in the technical disclosure, and will not be described in detail herein. After the peeling, the leads 40 are exposed to form outer leads.
A packaging structure for preventing delamination is obtained through the packaging process.
[ example two ]
A packaging process of a packaging structure for preventing delamination comprises the following steps:
Regarding step S1, step S2, step S3, step S4, step S5, step S7, and step S8, the same as in the first embodiment is true, and regarding step S6, the following is specifically made:
referring to fig. 11 and fig. 12 in conjunction with fig. 1 ~ 10, wherein fig. 11 is a structural diagram illustrating a plating state in a packaging process of a delamination prevention packaging structure according to a second embodiment, and fig. 12 is a top view of fig. 11.
Regarding step S6: and (4) electroplating.
in this embodiment, the flow and method of electroplating are the same as those in the first embodiment, except that: the ear pieces 52 on two adjacent connecting pieces 51 are connected with each other to form a whole, so that the electroplating operation is facilitated, and the contact area between the base island 30 and the plastic package body 10 is further increased by increasing the area of the ear pieces 52, so that the probability of layering among the base island, the chip and the plastic package body is greatly reduced.
A packaging structure for preventing delamination is obtained through the packaging process.
[ EXAMPLE III ]
A packaging process of a packaging structure for preventing delamination comprises the following steps:
regarding step S1, step S2, step S3, step S4, step S7, and step S8, the same as in the first embodiment, regarding step S5 and step S6, the following are concrete:
referring to fig. 13 and 14 in conjunction with fig. 1 ~ 10, fig. 13 is a schematic diagram illustrating a structure in a plating state in a packaging process of a delamination prevention packaging structure according to a third embodiment, and fig. 14 is a top view of fig. 13.
Regarding step S5: and (6) drilling.
in this embodiment, the flow and method of drilling are the same as those of the embodiment, but the difference is that during drilling, the shape of the delamination prevention keyhole c is designed into a plurality of arranged pinholes, and the pinholes are all perpendicular to the surface of the base island 30.
Regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the first embodiment, except that: in combination with step S5 in the present embodiment, the pinhole-shaped delamination preventing locking hole c is plated, the interior is filled with the plating layer, a rod-shaped connecting member 51 is formed, one end of the connecting member 51 is fixed on the base island 30, the other end is continuously plated, a circular ear piece 52 is formed, the end of the connecting member 51 away from the base island 30 is connected to the center position of the ear piece 51, the rod-shaped connecting member 51 and the circular ear piece 52 are combined with each other, a rivet structure is formed, in other embodiments, the end of the connecting member 51 away from the base island 30 may be connected to any position of the ear piece 51, and two adjacent ear pieces 52 do not contact.
In this embodiment, the combination of the connecting member 51 and the ear member 52 in the rivet structure is uniformly distributed, and in other embodiments, the combination may be distributed in other forms.
A packaging structure for preventing delamination is obtained through the packaging process.
[ EXAMPLE IV ]
A packaging process of a packaging structure for preventing delamination comprises the following steps:
Regarding step S1, step S2, step S3, step S4, step S5, step S7, and step S8, the same as in the first embodiment is true, and regarding step S6, the following is specifically made:
referring to fig. 15 and fig. 16 in conjunction with fig. 1 ~ 10, wherein fig. 15 is a schematic diagram illustrating a structure in an electroplated state in a packaging process of a delamination prevention packaging structure according to a fourth embodiment, and fig. 16 is a top view of fig. 15.
regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the third embodiment, except that: the ear pieces 52 on two adjacent connecting pieces 51 are connected with each other to form a whole, so that the electroplating operation is facilitated, and the contact area between the base island 30 and the plastic package body 10 is further increased by increasing the area of the ear pieces 52, so that the probability of layering among the base island, the chip and the plastic package body is greatly reduced.
A packaging structure for preventing delamination is obtained through the packaging process.
[ EXAMPLE V ]
A packaging process of a packaging structure for preventing delamination comprises the following steps:
regarding step S1, step S2, step S3, step S4, step S7, and step S8, the same as in the first embodiment, regarding step S5 and step S6, the following are concrete:
referring to fig. 17 and fig. 18 in conjunction with fig. 1 ~ 10, wherein fig. 17 is a schematic diagram illustrating a structure in a plating state in a packaging process of a delamination prevention packaging structure according to a fifth embodiment, and fig. 18 is a top view of fig. 17.
Regarding step S5: and (6) drilling.
In this embodiment, the first plastic package body 10a is drilled by laser, mechanical or etching to form the wavy anti-delamination locking hole c, the anti-delamination locking hole c in this embodiment has a structure of a continuous wavy surface, and wave crests between adjacent wavy surfaces are connected smoothly, so that the subsequent continuous electroplating operation is facilitated, and the base island 30 below each wave trough on the anti-delamination locking hole c is exposed.
Regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the first embodiment, except that: in combination with step S5 in this embodiment, a wavy plating layer is plated on the outer wall of the wavy delamination-preventing lock hole c, and the thickness of the plating layer is uniform.
The electroplated layer in this embodiment is equivalent to the connecting member 51 in the first embodiment, and is located at each trough of the delamination-proof lock hole c, and the electroplated layer is connected and fixed with the base island 30 below the trough of the delamination-proof lock hole c, so that the contact area between the base island 30 and the first plastic package body 10a is increased, the adhesion degree is improved, and the delamination phenomenon is avoided.
In addition, the process flow adopted in this embodiment is high in production efficiency and simple and convenient to operate in steps S5 and S6, and the corrugated plating layer connecting piece 51 is connected to the first plastic package body 10a by relatively opposing a plurality of vertical surfaces in the vertical direction, and is connected to the first plastic package body 10a by a surface equivalent to a whole in the horizontal direction, so that the contact area between the base island 30 and the first plastic package body 10a is maximized, and on this basis, the operation efficiency is simple and convenient.
a packaging structure for preventing delamination is obtained through the packaging process.
Based on the five package structures obtained in the five embodiments, the most important difference is the package structures with five different structures resulting from the processes of drilling and electroplating, and in other embodiments, at least one of the package structures with the five different structures can be selected on the same package structure to perform a packaging process, so as to form a new package structure.
Compared with the prior art, the invention has the following beneficial effects:
The invention provides a packaging structure for preventing delamination, which adopts a fastener to be plastically packaged in a plastic package body, the fastener is fixedly connected with a base island, thereby increasing the contact area between the base island and the plastic package body, greatly improving the bonding degree between the plastic package body and the base island, designing the fastener into a structure of a connecting piece and an ear piece, the base island is connected with the ear piece through the connecting piece, the ear piece only clamps and fixes the plastic package body in the plastic package body, and due to the action of the connecting piece, the base island at the back of a chip or a frame used for replacing the base island in actual use is tightly locked with the plastic package body, thereby effectively preventing the delamination between the chip and the frame or the base island, and also preventing the delamination between the plastic package body and the base island or the frame, in the structure, the fastener can be installed at any place on the island without influencing other electronic components, and the position can be flexibly adjusted, on all encapsulation sizes and the not chip of equidimension that is applicable to the chip package field, because the effect of fastener, increase area of contact between island and the plastic-sealed body, also can improve the heat conduction on the island, thereby make the temperature in the encapsulation body more even, can not produce the phenomenon that temperature deviation is big, also can improve the efficiency that heat energy gived off on the island and the chip of being connected with the island, thereby when reliability test and the practical application in later stage, effectively avoid producing the phenomenon that the layering breaks away from because of high temperature leads to producing between different thermal expansion coefficient's the material, thereby improve the reliability of chip package, promote the performance of chip.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (16)
1. The packaging structure for preventing layering is characterized by comprising a plastic packaging body (10), wherein at least one electronic component is plastically packaged in the plastic packaging body (10), the electronic component is provided with at least one base island (30) and at least one pin (40), the top end of the pin (40) is exposed out of the outer surface of the plastic packaging body (10), the outer surface of the base island (30) is provided with at least one fastener (50), the fastener (50) is fixedly connected with the base island (30), and the fastener (50) is plastically packaged in the plastic packaging body (10).
2. The packaging structure for preventing delamination according to claim 1, wherein the fastening element (50) comprises a connecting element (51) having one end connected to the base island (30), and the other end of the connecting element (51) is molded in the molding compound (10).
3. A delamination prevention package as claimed in claim 2, wherein the fastener (50) further comprises an ear (52) for clamping the plastic package (10), the ear (52) being fixedly connected to the end of the connecting member (51) remote from the base island (30).
4. The packaging structure of claim 1, wherein the electronic component comprises a chip (21), a back surface of the chip (21) is attached to the base island (30), a pad (60) is disposed in the plastic package body (10), the pad (60) is not connected to the base island (30), the lead (40) is disposed on the base island (30) and the pad (60), and the chip (21) and the pad (60) are connected by a redistribution layer (70).
5. A package structure for preventing delamination according to claim 4, wherein said pad (60) is in the same plane and the same thickness as said base island (30), and wherein said pad (60) and said leads (40) on said base island (30) are both on the same side of the plane formed by said pad (60) and said base island (30).
6. The package structure of claim 1 ~ 5, wherein the leads (40) are outer leads.
7. The anti-delamination package structure according to claim 4, wherein the redistribution layer (70) is parallel to the base island (30), a recessed mesa (71) having a hat-shaped cross section is disposed at an end of the redistribution layer (70) connected to the pad (60), the recessed mesa (71) protrudes toward the pad (60), and a mesa of the recessed mesa (71) and a surface of the pad (60) are attached to each other and fixed.
8. the package structure of claim 7, wherein the base island (30) and the pad (60) are made of copper.
9. A package structure for preventing delamination according to claim 3, wherein said connecting member (51) and said ear member (52) are made of a metal capable of being plated.
10. A delamination prevention package as claimed in claim 4, wherein the chip (21) and the substrate (30) are connected by a metal transition layer, and the material of the metal transition layer comprises at least one of TiNiAg, TiAu or TiCu.
11. A packaging process of a packaging structure for preventing delamination is characterized in that: the method comprises the following steps:
The method comprises the following steps: preparing a substrate, namely placing the back surface of a substrate (a) on a carrier plate (b), wherein the carrier plate (b) is used for supporting and protecting the substrate, pins (40) on the substrate (a) are exposed on the back surface of the substrate (a), a base island (30) protruding out of the surface of the substrate (a) and a gasket (60) which is not in contact with the base island (30) are arranged on one surface of the substrate (a) far away from the carrier plate (b), and the base island (30) and the gasket (60) are respectively electrically connected with the two pins (40);
Step two: chip mounting, namely loading the back surface of a chip (21) which is subjected to the BUMP process to one surface, far away from the substrate (a), of the base island (30), mutually attaching the chip (21) and the base island (30), wherein a copper BUMP (21 a) is arranged on the active surface of the chip (21) which is subjected to the BUMP process, and the active surface of the chip (21) is opposite to the substrate (a);
Step three: the method comprises the following steps of performing primary encapsulation on a carrier plate (b) to form a first plastic package body (10 a), wherein a base island (30), a gasket (60), a pin (40), a chip (21) and a copper bump (21 a) are all plastically packaged in the first plastic package body (10 a);
Step four: exposing the copper bump, and operating the first plastic package body (10 a) in a grinding, etching or laser drilling mode to expose the copper bump (21 a) on the active surface of the chip (21) on the outer surface of the first plastic package body (10 a);
Step five: drilling holes on one surface, which is exposed to the copper bump (21 a), of the first plastic package body (10 a), wherein the drilling holes are divided into two types, one type is an anti-delamination lock hole (c), the other type is a functional via hole (d), the bottom of the anti-delamination lock hole (c) extends to the surface of the base island (30), part of the outer surface of the base island (30) is exposed to the bottom of the anti-delamination lock hole (c), the bottom of the functional via hole (d) extends to the surface of the gasket (60), and the outer surface of the gasket (60) is exposed to the bottom of the functional via hole (d);
step six: electroplating, wherein the electroplating comprises two parts, one part is electroplating of the redistribution layer (70), and the other part is electroplating of the connecting piece (51);
Electroplating of the rewiring layer (70): carrying out metal electroplating connection between a copper bump (21 a) of a chip (21) and a gasket (60) to form a rewiring layer (70), wherein one end of the rewiring layer (70) is fixedly connected with the copper bump (21 a) of the chip (21), the other end of the rewiring layer extends to a functional through hole (d) along the outer surface of the first plastic package body (10 a), extends along the hole wall of the functional through hole (d), and is fixedly connected with the gasket (60) exposed at the bottom of the functional through hole (d), and the hole wall of the functional through hole (d) is covered with an electroplated layer to form a metal sunken platform (71) with a hat-shaped section;
Electroplating of the connecting piece (51): electroplating is carried out in each anti-layering lock hole (c) to form a connecting piece (51), the bottom end of the connecting piece (51) is fixedly connected with the base island (30), and the connecting piece (51) formed by electroplating is filled in the whole anti-layering lock hole (c) or covers the inner wall of the whole anti-layering lock hole (c);
Step seven: performing second encapsulation on the basis of the first encapsulation body (10 a) formed by the first encapsulation to form the encapsulation body (10), wherein the encapsulation body (10) comprises the first encapsulation body (10 a), and the rewiring layer (70), the sunken table (71) and the connecting piece (51) are all located in the encapsulation body (10);
Step eight: and (3) stripping the carrier plate (b) used in the step one, and exposing the pins (40) after stripping to form the outer pins.
12. The packaging process of claim 11, wherein in the first step, the material of the carrier (b) comprises at least one of a metal or alloy plate, a BT material, a FR-4 material, a silicon-based material, an EMC material, a glass material or a film material.
13. The packaging process of the delamination prevention package structure as recited in claim 11, wherein in the second step, the chip (21) and the base island (30) are transitionally connected by disposing a metal transition layer, and a material of the metal transition layer comprises at least one of TiNiAg, TiAu, or TiCu.
14. the packaging process of claim 11, wherein in step five, the drilling manner comprises laser drilling, mechanical drilling or etching.
15. The packaging process of the delamination prevention package structure as recited in claim 11, wherein in the fifth step, a plurality of uniformly distributed delamination prevention locking holes (c) are formed on a surface of the first plastic package body (10 a) where the copper bumps (21 a) are exposed.
16. The packaging process of the delamination prevention packaging structure as recited in claim 11, further comprising electroplating the ear piece (52) in step six, wherein the electroplating is performed on an end of the connecting member (51) away from the base island (30) at the same time or after the electroplating of the connecting member (51) to form the ear piece (52), the ear piece (52) is attached to the surface of the first plastic package body (10 a) and has a thickness equal to that of the redistribution layer (70), the ear piece (52) is parallel to the base island (30), the ear piece (52) and the connecting member (51) are integrated, and after the second encapsulation in step seven, the ear piece (52) is entirely located in the plastic package body (10).
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| CN114121853A (en) * | 2022-01-27 | 2022-03-01 | 深圳中科四合科技有限公司 | Packaging structure of large-size chip adaptive small-size packaging body |
| CN114361045A (en) * | 2022-03-16 | 2022-04-15 | 合肥矽迈微电子科技有限公司 | Deep hole processing method based on semiconductor packaging |
| CN115954284A (en) * | 2023-03-15 | 2023-04-11 | 合肥矽迈微电子科技有限公司 | Packaging process of MOSFET chip |
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