CN110556343B - Packaging structure and packaging process for preventing layering - Google Patents
Packaging structure and packaging process for preventing layering Download PDFInfo
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- CN110556343B CN110556343B CN201910961854.9A CN201910961854A CN110556343B CN 110556343 B CN110556343 B CN 110556343B CN 201910961854 A CN201910961854 A CN 201910961854A CN 110556343 B CN110556343 B CN 110556343B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 75
- 230000003405 preventing effect Effects 0.000 title claims abstract description 61
- 238000012858 packaging process Methods 0.000 title claims abstract description 25
- 238000009713 electroplating Methods 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052802 copper Inorganic materials 0.000 claims abstract description 30
- 239000010949 copper Substances 0.000 claims abstract description 30
- 238000005553 drilling Methods 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims description 23
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
According to the packaging structure and the packaging process for preventing layering, the fastener is adopted to be packaged in the plastic package body through the process flows of substrate preparation, chip mounting, first packaging, copper bump exposure, drilling, electroplating, second packaging, carrier plate peeling and the like, so that the contact area between the base island and the plastic package body is increased, the bonding degree between the plastic package body and the base island is improved, the fastener is arranged on any place on the base island without affecting other electronic components, the position of the fastener can be flexibly adjusted, the packaging structure and the packaging process are suitable for chips with all packaging sizes and different sizes in the chip packaging field, the contact area between the base island and the plastic package body is increased by the fastener, the heat conduction on the base island is improved, the heat dissipation efficiency on the base island and the chips connected with the base island can be improved, the phenomenon that layering separation is caused between materials with different thermal expansion coefficients due to high temperature is effectively avoided, and the reliability of chip packaging is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging process for preventing layering.
Background
With the development of electronic products, semiconductor technology has been widely used for manufacturing memories, central Processing Units (CPUs), liquid crystal display devices (LCDs), light Emitting Diodes (LEDs), laser diodes, and other devices or chip sets.
Because electronic components such as semiconductor components, micro-electromechanical components (MEMS) or optoelectronic components have very fine circuits and structures, in order to avoid pollution or corrosion of the electronic components by dust, acid-base substances, moisture, oxygen, etc., and further affect the reliability and life thereof, the technology needs to provide the functions of the electronic components such as electrical energy creation, signal transmission, heat dissipation, protection and support, etc. by using packaging technology.
Semiconductor packaging refers to the process of processing a wafer that passes testing to obtain individual chips according to product model and functional requirements. The packaging process is as follows: the wafer from the wafer front process is cut into small chips (Die) through the dicing process, then the cut chips are attached to the corresponding islands of the substrate (Lead frame) frame by glue, and then the bonding pads (Bond pads) of the chips are connected to the corresponding pins (Lead) of the substrate by using ultra-fine metal (gold tin copper aluminum) wires or conductive resin, and the required circuit is formed; and then packaging and protecting the independent wafer by using a plastic shell, performing a series of operations after plastic packaging, performing finished product testing after packaging, generally performing procedures such as checking in, testing Test and packaging, and finally warehousing and delivering.
In the field of chip packaging, the packaging materials adopted are more in variety, the physical characteristics of different materials are different, especially the thermal expansion coefficients of the different materials are different, so that the components of the different materials in contact with each other have obvious influence, the size of a chip is larger for a large-size packaging body, the size of a base island is larger than that of the chip, layering phenomenon easily occurs in a strict working environment or test after chip packaging, especially the heat on the chip cannot be timely emitted, the temperature on the chip and the plastic packaging material is concentrated, the temperature on the chip and the plastic packaging material are not uniformly dispersed, the thermal expansion efficiency is increased, the layering separation phenomenon of the chip and a frame or the base island is more easy to occur, and the performance and the effective use of a product are seriously influenced.
Disclosure of Invention
The invention provides a packaging structure and a packaging process for preventing layering, which aims at overcoming the defects of the prior art.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
the utility model provides a prevent layered packaging structure, includes a plastic envelope body, at least one electronic component plastic envelope in the plastic envelope body, have at least one base island and at least one pin on the electronic component, the top of pin expose in the surface of plastic envelope body, the surface of base island is equipped with at least one fastener, fixed connection between fastener and the base island, and the fastener plastic envelope is in the plastic envelope body.
Further, the fastener comprises a connecting piece with one end connected with the base island, and the other end of the connecting piece is in plastic package.
Further, the fastener also comprises an ear piece for clamping and fixing the plastic package body, and the ear piece is fixedly connected with one end, far away from the base island, of the connecting piece.
Further, a chip is arranged on the electronic component, the back of the chip is attached to the base island, a gasket is arranged in the plastic package body, the gasket is not connected with the base island, pins are respectively arranged on the base island and the gasket, and the chip is connected with the gasket through a redistribution layer.
Further, the pad and the base island are positioned on the same plane and have the same thickness, and the pad and the pins on the base island are positioned on the same side of the plane formed by the pad and the base island.
Further, the pins are external pins.
Further, the rewiring layer is parallel to the base island, a concave table with a hat-shaped section is arranged at one end, connected with the gasket, of the rewiring layer, the concave table protrudes towards the direction of the gasket, and the table top of the concave table is mutually adhered to and fixed with the surface of the gasket.
Further, the base island and the gasket are made of copper metal.
Further, the connecting piece and the ear piece are made of electroplated metal.
Further, the chip and the base island are in transitional connection through the arrangement of a metal transition layer, and the material of the metal transition layer comprises at least one of TiNiAg, tiAu or TiCu.
A packaging process for preventing delamination of a package structure, comprising the steps of:
step one: preparing a substrate, namely placing the back surface of the substrate on a carrier plate, wherein the carrier plate is used for supporting and protecting, pins on the substrate are exposed on the back surface of the substrate, and a base island protruding from the surface of the substrate and a gasket which is not contacted with the base island are arranged on one surface of the substrate, which is far away from the carrier plate, and the base island and the gasket are respectively electrically connected with the two pins;
step two: chip mounting, namely loading the back surface of a chip which is subjected to the BUMP process on one surface, far away from a substrate, of the base island, mutually attaching the chip and the base island, wherein the active surface of the chip which is subjected to the BUMP process is provided with copper BUMPs, and the active surface of the chip faces away from the substrate;
step three: performing primary encapsulation on the carrier plate to form a first plastic package body, wherein the base island, the gasket, the pins, the chip and the copper bumps are all plastic packaged in the first plastic package body;
step four: exposing the copper bump, and operating the first plastic package body in a grinding, etching or laser drilling mode to enable the copper bump on the active surface of the chip to be exposed on the outer surface of the first plastic package body;
step five: drilling, namely drilling on one surface of the first plastic package body, which is exposed to the copper bump, wherein the drilling is divided into two types, one type is an anti-layering lock hole, the other type is a functional via hole, the bottom of the anti-layering lock hole extends to the surface of the base island, part of the outer surface of the base island is exposed to the bottom of the anti-layering lock hole, the bottom of the functional via hole extends to the surface of the gasket, and the outer surface of the gasket is exposed to the bottom of the functional via hole;
step six: electroplating, wherein the electroplating comprises two parts, one part is a rewiring layer electroplating and the other part is a connecting piece electroplating;
electroplating a rewiring layer: the method comprises the steps of performing metal electroplating connection between a copper bump of a chip and a gasket to form a re-wiring layer, wherein one end of the re-wiring layer is fixedly connected with the copper bump of the chip, the other end of the re-wiring layer extends to a functional via along with the outer surface of a first plastic package body and extends along the hole wall of the functional via to be fixedly connected with the gasket exposed at the bottom of the functional via, and the hole walls of the functional via are covered with a layer of electroplated layer to form a metal concave table with a hat-shaped section;
electroplating a connecting piece: electroplating is carried out in each layering preventing lock hole to form a connecting piece, the bottom end of the connecting piece is fixedly connected with the base island, and the connecting piece formed by electroplating is filled with the whole layering preventing lock hole or covers the inner wall of the whole layering preventing lock hole;
step seven: the second encapsulation is carried out on the basis of the first plastic package body formed by the first encapsulation, so that a plastic package body is formed, the plastic package body comprises the first plastic package body, and the rewiring layer, the concave table and the connecting piece are all located in the plastic package body;
step eight: and (3) stripping the carrier plate, namely stripping the carrier plate used in the step one, exposing the pins after stripping, and forming the outer pins.
Further, in the first step, the material of the carrier plate includes at least one of a metal or alloy plate, a BT material, an FR-4 material, a silicon-based material, an EMC material, a glass material, or a thin film material.
In the second step, the chip and the island are in transitional connection through a metal transition layer, and the material of the metal transition layer comprises at least one of TiNiAg, tiAu or TiCu.
Further, in the fifth step, the drilling mode includes laser drilling, mechanical drilling or etching.
In the fifth step, a plurality of uniformly distributed delamination preventing lock holes are formed on the surface of the first plastic package body, which is exposed to the copper bump.
Further, in the step six, the method further comprises the step of electroplating the ear piece, wherein the ear piece is formed by electroplating at one end, far away from the base island, of the connecting piece at the same time or after the connecting piece is electroplated, the ear piece is attached to the surface of the first plastic package body, the thickness of the ear piece is the same as that of the rewiring layer, the ear piece is parallel to the base island, the ear piece and the connecting piece are integrated, and after the second encapsulation in the step seven, the whole ear piece is in the plastic package body.
Compared with the prior art, the invention has the following beneficial effects:
according to the layered packaging structure, the fastening piece is adopted to be in plastic packaging in the plastic packaging body, the fastening piece is fixedly connected with the base island, so that the contact area between the base island and the plastic packaging body is increased, the bonding degree between the plastic packaging body and the base island can be greatly improved, the fastening piece is designed into a structure of the connecting piece and the ear piece, the base island and the ear piece are connected through the connecting piece, the plastic packaging body is tightly clamped and fixed in the plastic packaging body by the ear piece, due to the effect of the connecting piece, the base island at the back of a chip or the frame adopted by the base island is tightly locked with the plastic packaging body in the actual use, the layered separation between the chip and the frame or between the base island is effectively prevented, the layered separation between the plastic packaging body and the base island or the frame is also prevented, in the structure, the fastening piece can be installed at any place on the base island without influencing other electronic components, the position can be flexibly adjusted, the structure is suitable for all packaging sizes in the chip packaging field and chips with different sizes, the island contact area between the base island and the plastic packaging body is increased, due to the effect of the fastening piece, the island heat on the base island can be further improved, the thermal conductivity of the base island can be more evenly increased, the thermal conductivity of the chip can be greatly improved, the thermal insulation coefficient can be greatly, the thermal insulation coefficient can be effectively improved, the thermal insulation coefficient can not be effectively expanded, and the thermal insulation phenomenon can be effectively prevented from the thermal insulation phenomenon can be caused, and the thermal insulation phenomenon can not be effectively spread to the thermal insulation phenomenon between the chip and the thermal insulation can be effectively spread to the thermal insulation, and the thermal insulation can be effectively, and has different thermal insulation performance.
Drawings
FIG. 1 is a schematic diagram illustrating a packaging process of a delamination preventing packaging structure according to the present invention;
FIGS. 2-9 are process flow diagrams of a packaging structure and a packaging process for preventing delamination in the first embodiment of the present invention;
fig. 10 is a schematic structural diagram of a package structure for preventing delamination according to the first embodiment of the present invention;
FIG. 11 is a schematic diagram of a structure of a packaging process for preventing a layered packaging structure according to a second embodiment;
FIG. 12 is a top view of FIG. 11;
fig. 13 is a schematic structural diagram of a plating state in a packaging process of a layered packaging structure according to a third embodiment;
FIG. 14 is a top view of FIG. 13;
fig. 15 is a schematic structural diagram of a plating state in a packaging process of a layered packaging structure according to a fourth embodiment;
FIG. 16 is a top view of FIG. 15;
fig. 17 is a schematic structural diagram of a plating state in a packaging process of a layered packaging structure according to a fifth embodiment;
fig. 18 is a top view of fig. 17.
Detailed Description
The present invention will be described below in conjunction with specific embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout.
The directional terms mentioned in this invention are, for example: the upper, lower, left, right, front, rear, inner, outer, front, back, side, etc. are only with reference to the directions of the drawings, and the embodiments and directional terms used below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention. In addition, various specific examples of processes and materials are provided herein, as will be appreciated by those of ordinary skill in the art as applications of other processes and/or use of other materials.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a packaging process of a delamination prevention packaging structure according to the present invention.
The packaging technology of the packaging structure for preventing layering comprises the following steps:
s1: preparing a substrate; s2: chip loading; s3: a first encapsulation; s4: exposing the copper bump; s5: drilling holes; s6: electroplating; s7: second encapsulation and S8: and (5) stripping the carrier plate. The following describes the above steps in detail with reference to the drawings and embodiments.
[ embodiment one ]
A packaging technology for preventing layered packaging structure comprises the following steps:
referring to fig. 2 to 10, fig. 2 to 9 are process flow diagrams of a packaging structure and a packaging process for preventing delamination in a first embodiment of the present invention; fig. 10 is a schematic structural diagram of a package structure for preventing delamination in the first embodiment of the present invention.
Regarding step S1: and (5) preparing a substrate.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a substrate and a carrier.
The back of the substrate a is placed on a carrier plate b, the material of the carrier plate b comprises at least one of metal or alloy plates, BT material, FR-4 material, silicon-based material, EMC material, glass material or film material, the carrier plate b is used for supporting and protecting, two pins 40 are embedded in the substrate a and are exposed on the back of the substrate a, the carrier plate b is contacted with and attached to the substrate a, a base island 30 protruding from the surface of the substrate a and a gasket 60 which is not contacted with the base island 30 are arranged on one surface of the substrate a, the base island 30 and the gasket 60 are respectively electrically connected with the two pins 40 in the substrate a, the base island 30 and the gasket 60 are positioned on the same horizontal plane and have the same thickness, the gaskets 60 are all made of metal materials, and the gaskets 60 are copper gaskets.
The substrate a and the carrier b are bonded by glue, soluble matters or fusible matters, such as hydrogel, pyrolytic glue or photolytic glue, and the like, so that the substrate a and the carrier b are conveniently peeled off in the later stage.
Among them, hydrogels (hydrogels) are a type of extremely hydrophilic three-dimensional network structure gel which rapidly swells in water and can hold a large volume of water in this swollen state without dissolution, and since a crosslinked network exists, hydrogels can swell and hold a large volume of water, and the absorption amount of water is closely related to the degree of crosslinking. The higher the degree of crosslinking, the lower the water absorption. This property is much like a soft tissue. The water content in the hydrogel may be as low as a few percent or as high as 99 percent. The aggregated state of the gel is neither a complete solid nor a complete liquid. The behavior of a solid is that a certain shape and volume can be maintained under certain conditions, and the behavior of a liquid is that a solute can diffuse or permeate from a hydrogel. The hydrogel may be removed by heating in water.
The thermal decomposition adhesive is a solvent adhesive, has certain adhesive force at normal temperature, can play a role in positioning and supporting, can disappear after the temperature is heated to a set temperature, can realize simple stripping, has fewer residues and does not pollute an adherend.
The photodecomposition adhesive has certain adhesive force, can play a role in positioning and supporting, can generate photodecomposition reaction to become water-soluble after illumination, and can realize simple stripping.
Regarding step S2: and (5) chip mounting.
As shown in fig. 3, fig. 3 is a schematic diagram of a chip mounting structure.
The backside of the chip 21 after completing the BUMP process is loaded onto the side of the island 30 away from the substrate a (the BUMP process of the chip is well known to those skilled in the art, and is not a necessary technical feature for solving the technical problem of the present invention, and is not described in detail herein), the chip 21 and the island 30 are attached to each other, the active side of the chip 21 after completing the BUMP process has a copper BUMP 21a, the active side of the chip 21 faces away from the substrate a, and a metal transition layer is disposed between the chip 21 and the island 30 for transition connection, and the material of the metal transition layer includes at least one of TiNiAg, tiAu or TiCu.
Since the back of the chip 21 is usually made of pure silicon material and cannot be connected with other metals in a penetrating way, when the chip 21 is mounted on the base island 30, a metal transition layer is arranged between the chip 21 and the base island 30 for excessive connection, so that the connection performance and the conductivity are improved, the phenomenon that the packaging structure is damaged due to mutual separation between the chip 21 and the base island 30 in the later stage is avoided, and the defective rate is greatly reduced.
Regarding step S3: and (5) first encapsulation.
As shown in fig. 4, fig. 4 is a schematic structural diagram of the first encapsulation after chip mounting.
The first encapsulation is performed on the carrier board b to form a first plastic package body 10a, and the base island 30, the pad 60, the pins 40, the chip 21 and the copper bumps 21a are all encapsulated in the first plastic package body 10a and are not in contact with the external atmosphere, and the material of the first plastic package body 10a is any plastic package material known to those skilled in the art, such as a resin material.
Regarding step S4: exposing the copper bumps.
As shown in fig. 5, and referring to fig. 4, fig. 5 is a schematic structural view of copper bump exposure on a chip.
The outer surface of the first plastic package body 10a on the side close to the copper bump 21a is cut down by grinding, etching or laser drilling until the copper bump 21a is exposed to the surface of the first plastic package body 10a and is exposed to the atmosphere, and the outer surface of the first plastic package body 10a on the side close to the copper bump 21a is cut down to form a plane parallel to the island 30, please refer to the portion above the dotted line y in fig. 4 and 5.
Regarding step S5: drilling.
Fig. 6 is a schematic view of a structure of a drilled hole, and fig. 10 is a schematic view of a package structure for preventing delamination according to a first embodiment of the present invention.
Drilling is performed on one surface of the first plastic package body 10a, which is located on the exposed copper bump 21a, and the drilling is divided into two types, namely an anti-delamination lock hole c and a functional via d.
The two types of drilling holes are drilled in a laser, mechanical or etching mode, the bottom of the delamination preventing keyhole c extends to the surface of the base island 30, part of the outer surface of the base island 30 is exposed to the bottom of the delamination preventing keyhole c, the central axis of the delamination preventing keyhole c is perpendicular to the surface of the base island 30, and the operation is convenient during drilling, so that the production efficiency is improved, but in the actual operation process, the central axis of the delamination preventing keyhole c and the surface of the base island 30 can have an inclined angle, the delamination preventing keyhole c with the inclined angle is not necessarily in a perpendicular state, the delamination preventing effect brought by electroplating is better after the later stage of the delamination preventing keyhole c with the inclined angle is adopted, in the effective unit volume, the contact surface between electroplated metal and the first plastic package body 10a can be increased, and the inclined delamination preventing keyhole c is harder to drill holes than the perpendicular holes only in specific operation, so that the same technical personnel can easily know that the delamination preventing keyhole c can only conveniently realize subsequent electroplating, and the metal island can smoothly pass through the first plastic package body 10a and the delamination preventing keyhole c is in any dimension within the scope of the invention.
The anti-layering lock holes c can be uniformly formed in the first plastic package body 10a, so that the production and the manufacture are facilitated, in the actual production process, the uniform arrangement is not performed, and the positions of the anti-layering lock holes c can be properly adjusted according to the actual operation difficulty or the normal operation of the next procedure.
In this embodiment, the delamination preventing keyhole c is a plurality of parallel straight holes, and the central axis of the delamination preventing keyhole c is perpendicular to the island 30.
The bottom of the functional via hole d extends to the surface of the spacer 60, and the outer surface of the spacer 60 is exposed at the bottom of the functional via hole d, the functional via hole d is located right above the spacer 60, the central axis of the functional via hole d is parallel to the plane where the spacer 60 is located, the functional via hole d is cylindrical, or rectangular, or may be a waist-shaped hole, the hole shapes listed herein are all structures which are convenient to implement and improve the production efficiency, and of course, in order to facilitate the operation of the next procedure, or improve the production efficiency, the functional via hole d may be a hole with other shapes.
The delamination preventing keyhole c and the functional via d can be performed simultaneously.
Regarding step S6: electroplating.
Referring to fig. 7 and 10, fig. 7 is a schematic structural diagram of an electroplating state, and fig. 10 is a schematic structural diagram of a packaging structure for preventing delamination in a first embodiment of the present invention.
The copper bump 21a on the chip 21 is connected with the pad 60 by metal plating to form a re-wiring layer 70, one end of the re-wiring layer 70 is connected and fixed with the copper bump 21a of the chip 21, the other end of the re-wiring layer extends to the position of the functional via hole d along with the outer surface of the first plastic package body 10a, and extends along with the hole wall of the functional via hole d, and is connected and fixed with the pad 60 exposed at the bottom of the functional via hole d, the hole wall of the functional via hole d is covered with a layer of electroplated coating to form a metal concave table 71 with a hat-shaped section, the concave table 71 protrudes towards the direction of the pad 60, and the table top of the concave table 71 is mutually adhered and fixed with the surface of the pad 60.
Electroplating is performed in each layering preventing lock hole c, a connecting piece 51 formed by electroplating is cylindrical and closely attached to the inner wall of each layering preventing lock hole c, electroplating is performed on the bottom of each layering preventing lock hole c while electroplating is performed on the inner wall of each layering preventing lock hole c, formed electroplating layers are fixedly connected with the base island 30, and the electroplating layers are integrated with the connecting piece 51.
In the actual operation process, the anti-layering lock hole c can be filled with an electroplated layer to form a strip-shaped connecting piece 51 (the strip-shaped connecting piece 51 is not shown in the figure), so that the electroplating efficiency is improved, and the operation is convenient.
The redistribution layer 70 and the connection 51 can be electroplated simultaneously.
Further, the ear piece 52 is electroplated, and a circle of electroplated layer is electroplated on the periphery edge of one end, far away from the base island 30, of the connecting piece 51 at the same time or after the connecting piece 51 is electroplated, so that the ear piece 52 is formed, the ear piece 52 and the connecting piece 51 are integrated, the connecting piece 51 is attached to the outer surface of the first plastic package body 10a and is positioned on the same horizontal plane with the rewiring layer 70, in this embodiment, the thickness of the rewiring layer 70 is consistent with the thickness of the rewiring layer 70, so that the production and cost saving are facilitated, but in the actual operation process, the thickness can be inconsistent.
In the present embodiment, the ear pieces 52 on the adjacent two connection pieces 51 do not contact each other.
Regarding step S7: and (5) secondary encapsulation.
Referring to fig. 8 in combination with fig. 7, fig. 8 is a schematic structural diagram of the second encapsulated state.
The second encapsulation is performed on the basis of the first plastic package body 10a formed by the first encapsulation, so that the plastic package body 10 is formed, the material of the plastic package body 10 is the same as the material used for the first plastic package body 10a, and thus, delamination is not easy to occur in the later use process, the plastic package body 10 comprises the first plastic package body 10a, the plastic package body 10 and the first plastic package body 10a are integrated (since the plastic package body 10 is encapsulated on the basis of the first plastic package body 10a, the first plastic package body 10a is contained in the plastic package body 10, no mark "10a" is shown in fig. 8, only mark "10"), and the rewiring layer 70, the recess table 71, the connecting piece 51 and the ear piece 52 are all located in the plastic package body 10.
Regarding step S8: and (5) stripping the carrier plate.
Referring to fig. 9, fig. 9 is a schematic view of a state structure of the carrier after being peeled.
The carrier b used in step S1 is peeled off, and the peeling process is a technology mature and common process of technical disclosure in the field, and is not described in detail here. After the peeling, the leads 40 are exposed to form external leads.
A packaging structure for preventing layering is obtained through the packaging technology.
[ example two ]
A packaging technology for preventing layered packaging structure comprises the following steps:
the steps S1, S2, S3, S4, S5, S7 and S8 are the same as those in the first embodiment, and the following is specific for the step S6:
referring to fig. 11 and 12 in combination with fig. 1 to 10, fig. 11 is a schematic structural diagram of an electroplating state in a packaging process of a packaging structure for preventing delamination in a second embodiment, and fig. 12 is a top view of fig. 11.
Regarding step S6: electroplating.
In this embodiment, the flow and method of electroplating are the same as in embodiment one, except that: the ear pieces 52 on the two adjacent connecting pieces 51 are mutually connected to form a whole, electroplating operation is convenient, and the contact area between the base island 30 and the plastic package body 10 is further increased by increasing the area of the ear pieces 52, so that the layering probability among the base island, the chip and the plastic package body is greatly reduced.
A packaging structure for preventing layering is obtained through the packaging technology.
[ example III ]
A packaging technology for preventing layered packaging structure comprises the following steps:
the steps S1, S2, S3, S4, S7, and S8 are the same as those in the first embodiment, and the steps S5 and S6 are specifically as follows:
referring to fig. 13 and 14, and referring to fig. 1 to 10, fig. 13 is a schematic structural diagram of an electroplating state in a packaging process of a packaging structure for preventing delamination in a third embodiment; fig. 14 is a top view of fig. 13.
Regarding step S5: drilling.
In this embodiment, the flow and method of drilling are the same as those of the embodiment, except that the shape of the delamination preventing keyhole c is designed into a plurality of aligned pinholes, which are perpendicular to the surface of the island 30.
Regarding step S6: electroplating.
In this embodiment, the flow and method of electroplating are the same as in embodiment one, except that: in combination with step S5 in this embodiment, the pinhole-shaped delamination preventing keyhole c is electroplated, and is filled with an electroplated layer to form a rod-shaped connecting member 51, one end of the connecting member 51 is fixed on the base island 30, the other end continues to be electroplated to form a circular ear member 52, one end of the connecting member 51 far away from the base island 30 is connected with the central position of the ear member 52, the rod-shaped connecting member 51 and the circular ear member 52 are combined with each other to form a rivet structure, and in other embodiments, one end of the connecting member 51 far away from the base island 30 is connected with any position of the ear member 52, and two adjacent ear members 52 are not contacted.
In this embodiment, the plurality of the connecting members 51 and the ear members 52 are uniformly distributed in a rivet structure, and in other embodiments, the distribution may be performed in other forms.
A packaging structure for preventing layering is obtained through the packaging technology.
[ example IV ]
A packaging technology for preventing layered packaging structure comprises the following steps:
the steps S1, S2, S3, S4, S5, S7 and S8 are the same as those in the first embodiment, and the following is specific for the step S6:
referring to fig. 15 and 16, and referring to fig. 1 to 10, fig. 15 is a schematic structural diagram of a plating state in a packaging process of a layered packaging structure according to a fourth embodiment; fig. 16 is a top view of fig. 15.
Regarding step S6: electroplating.
In this embodiment, the flow and method of electroplating are the same as in the third embodiment, except that: the ear pieces 52 on the two adjacent connecting pieces 51 are mutually connected to form a whole, electroplating operation is convenient, and the contact area between the base island 30 and the plastic package body 10 is further increased by increasing the area of the ear pieces 52, so that the layering probability among the base island, the chip and the plastic package body is greatly reduced.
A packaging structure for preventing layering is obtained through the packaging technology.
[ example five ]
A packaging technology for preventing layered packaging structure comprises the following steps:
the steps S1, S2, S3, S4, S7, and S8 are the same as those in the first embodiment, and the steps S5 and S6 are specifically as follows:
referring to fig. 17 and 18, and referring to fig. 1 to 10, fig. 17 is a schematic structural diagram of a plating state in a packaging process of a layered packaging structure according to a fifth embodiment; fig. 18 is a top view of fig. 17.
Regarding step S5: drilling.
In this embodiment, the first plastic package body 10a is drilled by laser, mechanical or etching to form a waved delamination preventing keyhole c, the structure of the delamination preventing keyhole c in this embodiment is a waved surface with continuous waves, the wave crests between adjacent waved surfaces are smoothly connected, the subsequent continuous electroplating operation is facilitated, and each wave trough on the delamination preventing keyhole c is exposed with a base island 30 below.
Regarding step S6: electroplating.
In this embodiment, the flow and method of electroplating are the same as in embodiment one, except that: in combination with step S5 in this embodiment, a wavy electroplated layer is electroplated on the outer wall of the wavy anti-delamination keyhole c, and the thickness of the electroplated layer is uniform.
The electroplated layer in this embodiment corresponds to the connecting piece 51 in the first embodiment, and is located at each trough of the delamination preventing keyhole c, and is fixedly connected with the base island 30 below the trough of the delamination preventing keyhole c, so that the contact area between the base island 30 and the first plastic package body 10a is increased, the adhesion degree is improved, and the delamination phenomenon is avoided.
In addition, in the process flow adopted in the embodiment, in the steps S5 and S6, the production efficiency is high, the operation is simple and convenient, the wavy electroplated layer connecting piece 51 is connected with the first plastic package body 10a on a plurality of vertical surfaces in the vertical direction, and is connected with the first plastic package body 10a on a whole surface in the horizontal direction, so that the contact area between the base island 30 and the first plastic package body 10a is maximized, and on the basis, the operation efficiency is simple and convenient.
A packaging structure for preventing layering is obtained through the packaging technology.
Based on the five package structures obtained in the above five embodiments, the main difference is that the package structures with five different structures are brought by drilling and electroplating processes, and in other embodiments, at least one of the package structures with five different structures can be selected on the same package structure to perform the packaging process, so as to form a new package structure.
Compared with the prior art, the invention has the following beneficial effects:
according to the layered packaging structure, the fastening piece is adopted to be in plastic packaging in the plastic packaging body, the fastening piece is fixedly connected with the base island, so that the contact area between the base island and the plastic packaging body is increased, the bonding degree between the plastic packaging body and the base island can be greatly improved, the fastening piece is designed into a structure of the connecting piece and the ear piece, the base island and the ear piece are connected through the connecting piece, the plastic packaging body is tightly clamped and fixed in the plastic packaging body by the ear piece, due to the effect of the connecting piece, the base island at the back of a chip or the frame adopted by the base island is tightly locked with the plastic packaging body in the actual use, the layered separation between the chip and the frame or between the base island is effectively prevented, the layered separation between the plastic packaging body and the base island or the frame is also prevented, in the structure, the fastening piece can be installed at any place on the base island without influencing other electronic components, the position can be flexibly adjusted, the structure is suitable for all packaging sizes in the chip packaging field and chips with different sizes, the island contact area between the base island and the plastic packaging body is increased, due to the effect of the fastening piece, the island heat on the base island can be further improved, the thermal conductivity of the base island can be more evenly increased, the thermal conductivity of the chip can be greatly improved, the thermal insulation coefficient can be greatly, the thermal insulation coefficient can be effectively improved, the thermal insulation coefficient can not be effectively expanded, and the thermal insulation phenomenon can be effectively prevented from the thermal insulation phenomenon can be caused, and the thermal insulation phenomenon can not be effectively spread to the thermal insulation phenomenon between the chip and the thermal insulation can be effectively spread to the thermal insulation, and the thermal insulation can be effectively, and has different thermal insulation performance.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (5)
1. The packaging technology of the packaging structure for preventing layering is characterized by comprising the following steps of: the method comprises the following steps:
step one: preparing a substrate, namely placing the back surface of the substrate (a) on a carrier plate (b), wherein the carrier plate (b) has supporting and protecting functions, pins (40) on the substrate (a) are exposed on the back surface of the substrate (a), and a base island (30) protruding out of the surface of the substrate (a) and a gasket (60) which is not contacted with the base island (30) are arranged on one surface of the substrate (a) away from the carrier plate (b), wherein the base island (30) and the gasket (60) are respectively electrically connected with the two pins (40);
step two: chip mounting, namely loading the back surface of a chip (21) which is subjected to the BUMP process on one surface, far away from a substrate (a), of a base island (30), wherein the chip (21) and the base island (30) are mutually attached, a copper BUMP (21 a) is arranged on the active surface of the chip (21) which is subjected to the BUMP process, and the active surface of the chip (21) faces away from the substrate (a);
step three: performing first encapsulation on a carrier plate (b) to form a first plastic package body (10 a), wherein the base island (30), the gasket (60), the pins (40), the chip (21) and the copper bumps (21 a) are all molded in the first plastic package body (10 a);
step four: exposing the copper bump, and operating the first plastic package body (10 a) in a grinding, etching or laser drilling mode, so that the copper bump (21 a) on the active surface of the chip (21) is exposed on the outer surface of the first plastic package body (10 a);
step five: drilling, namely drilling on one surface of the first plastic package body (10 a) which is exposed with the copper bump (21 a), wherein the drilling is divided into two types, namely an anti-layering lock hole (c) and a functional via hole (d), wherein the bottom of the anti-layering lock hole (c) extends to the surface of the base island (30), part of the outer surface of the base island (30) is exposed at the bottom of the anti-layering lock hole (c), the bottom of the functional via hole (d) extends to the surface of the gasket (60), and the outer surface of the gasket (60) is exposed at the bottom of the functional via hole (d);
step six: electroplating, wherein the electroplating comprises two parts, one part is used for electroplating a rerouting layer (70) and the other part is used for electroplating a connecting piece (51);
electroplating the rewiring layer (70): the copper bump (21 a) of the chip (21) is connected with the gasket (60) through metal plating, a re-wiring layer (70) is formed, one end of the re-wiring layer (70) is fixedly connected with the copper bump (21 a) of the chip (21), the other end of the re-wiring layer extends to the functional via hole (d) along with the outer surface of the first plastic package body (10 a) and extends along with the hole wall of the functional via hole (d), the re-wiring layer is fixedly connected with the gasket (60) exposed at the bottom of the functional via hole (d), the hole wall of the functional via hole (d) is covered with a layer of electroplated layer, and a metal concave table (71) with a hat-shaped section is formed;
electroplating the connecting piece (51): electroplating is carried out in each layering preventing lock hole (c) to form a connecting piece (51), the bottom end of the connecting piece (51) is fixedly connected with the base island (30), and the connecting piece (51) formed by electroplating is filled with the whole layering preventing lock hole (c) or covers the inner wall of the whole layering preventing lock hole (c);
step seven: the second encapsulation is carried out on the basis of the first plastic package body (10 a) formed by the first encapsulation, so that the plastic package body (10) is formed, the plastic package body (10) comprises the first plastic package body (10 a), and the rewiring layer (70), the concave table (71) and the connecting piece (51) are all positioned in the plastic package body (10);
step eight: stripping the carrier plate, namely stripping the carrier plate (b) used in the first step, exposing the pins (40) after stripping, and forming outer pins;
in the sixth step, the method further comprises electroplating the ear piece (52), electroplating is performed at one end, far away from the base island (30), of the connecting piece (51) to form the ear piece (52), the ear piece (52) is attached to the surface of the first plastic package body (10 a), the thickness of the ear piece (52) is the same as that of the rewiring layer (70), the ear piece (52) is parallel to the base island (30), the ear piece (52) and the connecting piece (51) are integrated, and after the second encapsulation in the seventh step, the ear piece (52) is integrally positioned in the plastic package body (10).
2. The packaging process of claim 1, wherein in the first step, the material of the carrier (b) includes at least one of a metal plate, BT material, FR-4 material, silicon-based material, EMC material, glass material, or film material.
3. The packaging process of the layered packaging structure according to claim 1, wherein in the second step, the chip (21) and the island (30) are in transitional connection by providing a metal transition layer, and the material of the metal transition layer comprises at least one of TiNiAg, tiAu or TiCu.
4. The packaging process of claim 1, wherein in step five, the drilling method comprises laser drilling, mechanical drilling or etching.
5. The packaging process of the packaging structure for preventing layering according to claim 1, wherein in the fifth step, a plurality of layering preventing lock holes (c) which are uniformly distributed are formed on one surface of the first plastic packaging body (10 a) and are positioned on the surface of the first plastic packaging body where the copper bumps (21 a) are exposed.
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| CN114361045A (en) * | 2022-03-16 | 2022-04-15 | 合肥矽迈微电子科技有限公司 | Deep hole processing method based on semiconductor packaging |
| CN115954284A (en) * | 2023-03-15 | 2023-04-11 | 合肥矽迈微电子科技有限公司 | Packaging process of MOSFET chip |
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| CN207217519U (en) * | 2017-10-09 | 2018-04-10 | 浙江东和电子科技有限公司 | A kind of encapsulating lead |
| CN207883687U (en) * | 2018-02-01 | 2018-09-18 | 福建福顺半导体制造有限公司 | SOP-8 encapsulating leads |
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| JPH05251618A (en) * | 1991-10-16 | 1993-09-28 | Oki Electric Ind Co Ltd | Resin seal semiconductor device |
| CN207217519U (en) * | 2017-10-09 | 2018-04-10 | 浙江东和电子科技有限公司 | A kind of encapsulating lead |
| CN207883687U (en) * | 2018-02-01 | 2018-09-18 | 福建福顺半导体制造有限公司 | SOP-8 encapsulating leads |
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