CN110365565A - A kind of high fault-tolerant system of bus and recognition methods - Google Patents
A kind of high fault-tolerant system of bus and recognition methods Download PDFInfo
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- CN110365565A CN110365565A CN201910560157.2A CN201910560157A CN110365565A CN 110365565 A CN110365565 A CN 110365565A CN 201910560157 A CN201910560157 A CN 201910560157A CN 110365565 A CN110365565 A CN 110365565A
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- bus
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- bus signal
- differential bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
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- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The present invention relates to a kind of high fault-tolerant system of bus and recognition methods, according to the edge of identification input bus signal, the method that sampling is counted using fixed point, for standard, and there are the bus signals of deformation, realize the effect normally identified, entire identification process is convenient and simple, it is easy to modify and transplant, debugging being capable of stable operation after passing through, and it can effectively solve the problem that the mistake occurred often in bus signals resolving, and the use for passing through this method, when receiving bus signals devious, also correct data can accurately be parsed, opposite error resilience performance increases, and in practical application, under the bus environment of different rates, the value of counter need to only be adjusted, and the clock frequency of controller operation, it is convenient and simple, operation is easy；Designed method is the innovative technology of avionics bus application field, has method simple, the low feature of cost of implementation, while can be promoted the use of in the application of other similar avionics bus.
Description
Technical field
The present invention relates to a kind of high fault-tolerant system of bus and recognition methods, belong to avionics bussing technique field.
Background technique
Avionics bus is a kind of Ditital multichannel transfer bus, be US military be military aircraft intraconnection specify it is total
Line standard.It is widely applied currently, being achieved in fields such as space flight, aviations.
It is nearly all using state in use due to the complexity of its agreement and falling behind relatively for domestic overall technology level
Outer protocol chip, it is contemplated that the feasibility that the high cost and hardware logic of chip inlet are realized, using programmable logic device
The bottom encoding and decoding and protocol processes of part realization bus signals.But when bottom is decoded bus message data, often
Bus message or identification bus message mistake cannot be normally recognized since bus signals are interfered by extraneous factor.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of high fault-tolerant systems of bus, by between design module
Mutual calling, being capable of effectively criterion of identification and the bus message signal that is interfered.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme: it is fault-tolerant that the present invention devises a kind of bus height
Identifying system, for for deviation be no more than bus frequency 1/4 differential bus signal identified, including control module, with
And sampling module, counter t1, counter t2, the cache module, parsing module being connected respectively with control module；
Wherein, sampling module is used to be scanned according to timing, for differential bus signal, and according to timing, acquisition
Sampled data on differential bus signal, and by scanning result or sampled data upload control module；
Counter t1, counter t2 carry out counting or zero setting according to the control of control module respectively；
Cache module is used to receive the sampled data from control module forwarding, and is cached；
The sampled data that parsing module is used to be directed in cache module is identified, the target in differential bus signal is obtained
Data.
Technical problem to be solved by the invention is to provide a kind of recognition methods of the high fault-tolerant system of bus, pass through letter
It is single, conveniently, transplantable decoding process, being capable of effectively criterion of identification and the bus message signal being interfered.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme: it is fault-tolerant that the present invention devises a kind of bus height
The recognition methods of identifying system, the differential bus signal for being no more than bus frequency 1/4 for deviation identified, including such as
Lower step:
Step A. sampling module chronologically, for differential bus signal is scanned according to its sample frequency, if in discovery
Edge is risen, then enters step B, otherwise continues to execute the scan operation of this step；
Step B. start counter t1 by corresponding to it pre-set count values, start successively to count, while sampling module by
Differential bus signal current location continues chronologically, for differential bus signal to be scanned, according to its sample frequency wait count
Number device t1, which is counted, to be completed, then is directed to counter t1 zero setting, and enter step C；
Step C. start counter t2 by corresponding to it pre-set count values, start successively to count, while sampling module by
Differential bus signal current location is risen, and according to its sample frequency, chronologically, for differential bus signal is carried out data sampling, is obtained
Sampled data is obtained, and is stored in cache module through control module, and enter step D；
Step D. judges whether sampling module finds the rising edge on differential bus signal, is, sets for counter t2
Zero, while sampling module stops acquiring the data of differential bus signal, and return step B；Otherwise E is entered step；
Step E. judges whether counter t2 counts completion, is then and the return step C for counter t2 zero setting, otherwise
Counter t2 continuation successively count, while sampling module continue according to its sample frequency, chronologically, for differential bus signal into
Row sampling, obtains sampled data, and continues on through in control module deposit cache module, and return step D；
Execute step C to step E while, when sampling module recognize differential bus signal in-phase end and reverse side it is same
When to be low, and 2 times of the duration corresponding to counter t2 that has been delayed then are directed to counter t2 zero setting, while sampling module stops
To the acquisition of the data of differential bus signal, sampled data output in cache module, by parsing module for the sampled data into
Row identification, obtains the target data in differential bus signal.
As a preferred technical solution of the present invention: the corresponding pre-set count values of the counter t1 are equal to, and difference is total
1/4 duration of line signal period divided by sampling module sample frequency eligible result integer part.
As a preferred technical solution of the present invention: the corresponding pre-set count values of the counter t2 are equal to, and difference is total
1/2 duration of line signal period divided by sampling module sample frequency eligible result integer part.
A kind of high fault-tolerant system of bus of the present invention and recognition methods, using above technical scheme and the prior art
It compares, has following technical effect that
The high fault-tolerant system of bus designed by the present invention and recognition methods, according to identification input bus signal edge,
The method for counting sampling using fixed point for standard and has the bus signals of deformation, realizes the effect normally identified, entirely
Identification process is convenient and simple, is easy to modify and transplant, debugging pass through after can stable operation, and can effectively solve the problem that bus signals
The mistake occurred often in resolving, and by the use of this method, when receiving bus signals devious, also can
Enough accurately to parse correct data, opposite error resilience performance increases, and in practical application, in the bus ring of different rates
Under border, the value of counter and the clock frequency of controller operation need to be only adjusted, convenient and simple, operation is easy；It is designed
Method is the innovative technology of avionics bus application field, has method simple, the low feature of cost of implementation, while can be at other
It is promoted the use of in similar avionics bus application.
Detailed description of the invention
Fig. 1 is the practical deviation schematic diagram for receiving waveform and signals specification waveform of existing bus signals；
Fig. 2 is the practical schematic diagram that present invention design is applied to 1MHz rate bus signals；
Fig. 3 is the practical schematic diagram that present invention design is applied to 10MHz rate 1553B bus signals；
Fig. 4 is the practical schematic diagram that present invention design is applied to 20MHz rate 1553B bus signals.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawings of the specification.
Since bus signals are influenced by hardware impact or extraneous other factors, the waveform of input can be changed, high level
Time and low level time length are uneven, and the bus signals being an actually-received and the bus signals of specification is caused to have deviation, but
Deviation does not exceed the 1/4 of bus frequency, otherwise it is assumed that bus signals are abnormal, waveform and specification waveform such as Fig. 1 institute on practical line
Show.
The present invention devises a kind of high fault-tolerant system of bus, for being no more than the difference of bus frequency 1/4 for deviation
Point bus signals are identified, the sampling module that is connected including control module and respectively with control module, counter t1,
Counter t2, cache module, parsing module.
Wherein, sampling module is used to be scanned according to timing, for differential bus signal, and according to timing, acquisition
Sampled data on differential bus signal, and by scanning result or sampled data upload control module；Counter t1, counter t2
Counting or zero setting are carried out according to the control of control module respectively；Cache module is used to receive the sampling from control module forwarding
Data, and cached；The sampled data that parsing module is used to be directed in cache module is identified, differential bus signal is obtained
In target data.
Based on the high fault-tolerant system of bus described above, the present invention devises the recognition methods based on this system, is used for
The differential bus signal for being no more than bus frequency 1/4 for deviation is identified, as shown in Fig. 2, including the following steps.
Step A. sampling module chronologically, for differential bus signal is scanned according to its sample frequency, if in discovery
Edge is risen, then enters step B, otherwise continues to execute the scan operation of this step.
Step B. start counter t1 by corresponding to it pre-set count values, start successively to count, while sampling module by
Differential bus signal current location continues chronologically, for differential bus signal to be scanned, according to its sample frequency wait count
Number device t1, which is counted, to be completed, then is directed to counter t1 zero setting, and enter step C.
In practical application, the corresponding pre-set count values of counter t1 are equal to, 1/4 duration of differential bus signal period divided by
The integer part of sampling module sample frequency eligible result can ensure that sampled point is fallen on waveform active position in this way.
Step C. start counter t2 by corresponding to it pre-set count values, start successively to count, while sampling module by
Differential bus signal current location is risen, and according to its sample frequency, chronologically, for differential bus signal is carried out data sampling, is obtained
Sampled data is obtained, and is stored in cache module through control module, and enter step D.
In practical application, the corresponding pre-set count values of counter t2 are equal to, 1/2 duration of differential bus signal period divided by
The integer part of sampling module sample frequency eligible result can ensure that sampled point is fallen on the active position of waveform in this way.
Step D. judges whether sampling module finds the rising edge on differential bus signal, is, sets for counter t2
Zero, while sampling module stops acquiring the data of differential bus signal, and return step B；Otherwise E is entered step.
Step E. judges whether counter t2 counts completion, is then and the return step C for counter t2 zero setting, otherwise
Counter t2 continuation successively count, while sampling module continue according to its sample frequency, chronologically, for differential bus signal into
Row sampling, obtains sampled data, and continues on through in control module deposit cache module, and return step D.
Execute step C to step E while, when sampling module recognize differential bus signal in-phase end and reverse side it is same
When to be low, and 2 times of the duration corresponding to counter t2 that has been delayed then are directed to counter t2 zero setting, while sampling module stops
To the acquisition of the data of differential bus signal, sampled data output in cache module, by parsing module for the sampled data into
Row identification, obtains the target data in differential bus signal.
The above-mentioned designed high fault-tolerant system of bus is applied in reality, if the waveform in Fig. 2 is bus in 1MHz
Waveform under mode, the synchronous head time of 1MHz bus signals are 3us, and code bit time span is 1us, according to side of the invention
Method, the time span of sample counter t1 are 0.25us, and the time span of t2 counter is 0.5us, when sample frequency is
When 100MHz, the value of t1 counter is that the value of 25, t2 counter is 50.
When Bus Speed is in 10MHz mode, as shown in figure 3, synchronous head time span is 300ns, code bit time span
For 100ns, according to method of the invention, the time span of sample counter t1 is 20ns, and the time span of t2 counter is
50ns, when sample frequency is 100MHz, the value of t1 counter is that the value of 2, t2 counter is 5.
As shown in figure 4, synchronous head time span is 150ns, code bit time span when Bus Speed is in 20MHz mode
For 50ns, according to method of the invention, the time span of sample counter t1 is 10ns, and the time span of t2 counter is
25ns, when sample frequency is 200MHz, the value of t1 counter is that the value of 2, t2 counter is 5.
The high fault-tolerant system of bus designed by above-mentioned technical proposal and recognition methods, according to identification input bus signal
Edge, the method for counting sampling using fixed point for standard and have the bus signals of deformation, realize the effect normally identified,
Entire identification process is convenient and simple, is easy to modify and transplant, debugging pass through after can stable operation, and can effectively solve the problem that bus
The mistake occurred often during signal resolution, and by the use of this method, when receiving bus signals devious,
Also correct data can be accurately parsed, opposite error resilience performance increases, and in practical application, in the total of different rates
Under thread environment, the value of counter and the clock frequency of controller operation need to be only adjusted, convenient and simple, operation is easy；Institute
Design method is the innovative technology of avionics bus application field, has method simple, the low feature of cost of implementation, while can be
It is promoted the use of in other similar avionics bus application.
Embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementations
Mode within the knowledge of a person skilled in the art can also be without departing from the purpose of the present invention
It makes a variety of changes.
Claims (4)
1. a kind of high fault-tolerant system of bus, the differential bus signal for being no more than bus frequency 1/4 for deviation is carried out
Identification, it is characterised in that: the sampling module that is connected including control module and respectively with control module, counts counter t1
Device t2, cache module, parsing module；
Wherein, sampling module is used to be scanned according to timing, for differential bus signal, and according to timing, acquisition difference
Sampled data on bus signals, and by scanning result or sampled data upload control module；
Counter t1, counter t2 carry out counting or zero setting according to the control of control module respectively；
Cache module is used to receive the sampled data from control module forwarding, and is cached；
The sampled data that parsing module is used to be directed in cache module is identified, the number of targets in differential bus signal is obtained
According to.
2. a kind of recognition methods based on a kind of high fault-tolerant system of bus described in claim 1, for not surpassing for deviation
The differential bus signal for crossing bus frequency 1/4 is identified, which comprises the steps of:
Step A. sampling module chronologically, for differential bus signal is scanned according to its sample frequency, if discovery rises
Edge, then enter step B, otherwise continues to execute the scan operation of this step；
Step B. start counter t1 by corresponding to it pre-set count values, start successively to count, while sampling module is by difference
Bus signals current location continues chronologically, for differential bus signal to be scanned, device to be counted according to its sample frequency
T1, which is counted, to be completed, then is directed to counter t1 zero setting, and enter step C；
Step C. start counter t2 by corresponding to it pre-set count values, start successively to count, while sampling module is by difference
Bus signals current location is risen, and according to its sample frequency, chronologically, for differential bus signal is carried out data sampling, is adopted
Sample data, and be stored in cache module through control module, and enter step D；
Step D. judges whether sampling module finds the rising edge on differential bus signal, is then for counter t2 zero setting, together
When sampling module stop acquiring the data of differential bus signal, and return step B；Otherwise E is entered step；
Step E. judges whether counter t2 counts completion, is then and the return step C for counter t2 zero setting, otherwise counts
Device t2 continuation successively counts, while sampling module continues chronologically, for differential bus signal to be adopted according to its sample frequency
Sample obtains sampled data, and continues on through in control module deposit cache module, and return step D；
While executing step C to step E, when sampling module recognizes the in-phase end of differential bus signal and reverse side while being
It is low, and 2 times of the duration corresponding to counter t2 that has been delayed, then it is directed to counter t2 zero setting, while sampling module stops to difference
Divide the data acquisition of bus signals, the sampled data output in cache module is known by parsing module for the sampled data
Not, the target data in differential bus signal is obtained.
3. the recognition methods of the high fault-tolerant system of a kind of bus according to claim 2, it is characterised in that: the counter
The corresponding pre-set count values of t1 are equal to, and 1/4 duration of differential bus signal period is divided by sampling module sample frequency eligible result
Integer part.
4. the recognition methods of the high fault-tolerant system of a kind of bus according to claim 2, it is characterised in that: the counter
The corresponding pre-set count values of t2 are equal to, and 1/2 duration of differential bus signal period is divided by sampling module sample frequency eligible result
Integer part.
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Cited By (1)
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