CN1545349A - A bit synchronizer for difference offset four-phase keying demodulator - Google Patents

Abstract

The invention relates to a bit synchronous device used in difference bias four-phase key control demodulator, applied to PHS and PCS systems. It makes diversity combination on multiple antenna received signals in an intelligent antenna system, using the obtained signal as the input of a synchronous error detecting/comparing device, adopting a completely new bit synchronous error detecting/comparing device whose input mainly depends on signal phase information instead of signal amplitude information; enhancing performance and reliability of a bit synchronous device in wireless fading channel; overcoming the problem of distortion sensitivity; saving extra circuit and simplifying the bit synchronous control operation; also containing DA/NDA mode switching mechanism, further enhancing performance and making it flexible to implement; because of the introduction of error pre-detecting mechanism, enhancing the ability of resisting input interference and avoiding the problem of synchronous loop suspension.

Description

A kind of bit synchronizer that is used for differential offset quadriphase keying demodulator

Technical field

The present invention relates to moving communicating field, relate in particular to the bit synchronizer of a kind of Pi/4 of being used for DQPSK (differential offset quadriphase keying) demodulator, be applicable to PHS and PCS mobile communication system.

Background technology

PHS (Nippon Standard) and PCS (Unite States Standard) mobile communication system adopt the mode of time division multiplexing (TDMA), and each channel is used (multiplexing) by a plurality of users in the different moment.PHS and pcs system have all adopted the high high-order modulating of spectrum efficiency: Pi/4 DQPSK modulation system for the channel speed that is respectively 300kHz (PHS) and 30kHz (PCS) at frequency range is respectively the information of 384kb/s (PHS) and 48.6kb/s (PCS).Pi/4 DQPSK modulation system is compared with other high-order modulating, except the high advantage of spectrum efficiency, also has following characteristics:

1) be fit to adopt coherent demodulation mode, differential ference spiral mode and frequency discrimination to add the mode of integrator.For back two kinds of demodulation modes, their biggest advantage then is simple in structure.

2) for the coherent demodulation mode, owing to need carrier recovery circuit, so structure is complicated, verified simultaneously, to the residing fast fading channel of mobile communication system, the error rate of coherent demodulation will be higher than the non-coherent demodulation mode.

3) because the constellation space of Pi/4 DQPSK modulation has 8 constellation point, not by initial point, so the envelope of Pi/4 DQPSK signal rises and falls less than other high-order modulating, as QPSK, this linearity to power amplifier requires and can reduce during the signal constellation point conversion.

In order further to improve the performance of Pi/4 DQPSK modulation system under mobile communication environment,, adopted following technology as the message transmission rate and the network coverage:

1) need carry out shaping to signal spectrum at transmitting terminal, to reduce interference (CCI) to adjacent channel signal, simultaneously, by the matched filter that is complementary with the transmitting terminal transmitting filter is set in the demodulator of receiving terminal, can reduce intersymbol interference (ISI), it is the root raised cosine filter (RRCF) of 0.5 (the PHS system is 0.3 to pcs system) that the sending and receiving filter adopts roll-off factor.

2) intelligent antenna technology, intelligent antenna technology adds array signal process technique by a plurality of antenna receiving signals, can reduce the influence of interference signal, improves communication quality and system and covers.

The channel of mobile communication is a bandwidth efficient channel, so, transmit by after the Channel Transmission, can cause intersymbol interference at receiving terminal, the method that reduces intersymbol interference is to adopt the pulse-shaping filter, and PHS and pcs system all adopt raised cosine filter, and in real system, raised cosine filter is divided into two root raised cosine filters, and one is positioned at transmitting terminal, and one is positioned at receiving terminal.Oversampled signals (nyquist sampling signal) is through behind the root raised cosine filter, and in the sampling instant of the best, intersymbol interference is zero.

In addition, in mobile communication system, transmitting arrives receiving terminal in the space through a plurality of paths, because the length difference in each path, and the equal reason of the reflection/diffraction mechanism of signal experience, the asynchronism(-nization) that causes a plurality of signals to arrive, this phenomenon is called multidiameter delay and scatters.Multidiameter delay scatters and also causes intersymbol interference, and to general mobile communication system, the influence of multidiameter delay is eliminated by equalizer is set in the demodulator.But,, then need not to be provided with equalizer if multidiameter delay can be accepted the influence of transfer of data in the PHS system.

The intersymbol interference of above-mentioned two kinds of situations has only the selection by the optimum sampling moment to reduce in the PHS system, and optimum sampling estimation constantly is first task of synchro system, is called bit synchronization.

The transmitter and receiver operating frequency of mobile communication system can not be identical, and the frequency difference between the transmitting-receiving becomes frequency deviation, and frequency deviation causes following influence to Pi/4 DQPSK communication system:

1) signal constellation which of Jie Shouing is owing to frequency deviation rotates;

2) because the rotation of planisphere causes signal constellation point to pass through decision region when signal to noise ratio is low, the error rate of demodulator rises.

Receiver must be estimated and compensating for frequency offset for correct restituted signal.So, frequency offset estimating and second task that is compensated for as the receiver synchro system.

The detection of bit synchronization error (being also referred to as sampling error) is divided into two big classes according to the method that adopts, and a class is called non-data auxiliary type (Non_data_aided is called for short NDA), the another kind of data auxiliary type (Data_Aided is called for short DA) that is called.Both differences are whether utilize known transmitting, although known transmitting may be for receiving terminal be known, as lead code; Or receiving terminal the unknown, as the signal of judgement.

Although DA method performance is better than the NDA method theoretically, the DA method has error accumulation, convergence rate is slow, and implements complicated shortcoming.

In the NDA algorithm, be generally random signal owing to transmit, so, generally do not comprise that frequency is the spectral component of symbol period inverse in transmitting,, carry out nonlinear transformation usually to received signal in order to obtain this spectral component, to produce required spectrum component, and then utilize narrow band pass filter, as phase-locked loop, obtain sampling clock.

The sampling error testing circuit is mainly used in and produces optimum sampling produces sampling instant constantly with local sample circuit error signal, and common method has Mueller and Muller (M﹠amp; M) method, Gardner method, and adverse modulation loop etc. method, referring to " Guo ladder cloud, Liu Zengji, Wang Xinhai etc., communication engineering book series---transfer of data, Beijing, People's Telecon Publishing House, 1986 ".

In above-mentioned several sampling error testing circuits, have only the Gardner method can be operated in before frequency offset estimating/compensation, being operated in frequency offset estimating/compensation its design of circuit before can accomplish very flexible, but the Gardner method is suitable for psk modulation signal, produces because the Gardner method utilizes the following characteristic of psk signal to make the sampling error signal:

1) envelope has zero crossing;

2) the regular characteristics of waveform, promptly at adjacent optimum sampling constantly, signal amplitude is identical.

But for Pi/4 shifted DQPSK modulation signal, because signal envelope do not have zero crossing, signal envelope distorts, and distorts based on the sampling error testing circuit detection characteristic of Gardner method, has influenced the performance of testing circuit.

Whether bit synchronization method exists loop according to its structure, is divided into forward direction (Feed Forwards) and back again to structure (Back Forwards), referring to " digital communication, John G.Proakis work, Electronic Industry Press ".Because in the forward direction structure, the bit synchronization sampling instant that often is otherwise known as is estimated, so the bit synchronization error is called the sampling instant error again herein.

Under the rapid fading environment of mobile communication, because signal amplitude fluctuates on a large scale, above-mentioned bit synchronization performance will descend.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of bit synchronizer of the Pi/4 of being used for DQPSK demodulator, to solve the following problems that existing Pi/4 DQPSK demodulator bit synchronization method exists:

1) wireless communication system rapid fading environmental performance variation, reliability low problem;

2) bit synchronization method (as the Gardner method) is subjected to the problem of Pi/4 DQPSK signal amplitude envelope distortion degradation.

Core of the present invention is: at first utilize in the antenna system many antenna receiving signals to make diversity and merge (geometric ratio merging), with the input of this signal as bit synchronization error-detecting/comparator unit; Next adopts a kind of brand-new bit synchronization error-detecting/comparator, and the input of this circuit depends primarily on phase of input signals information but not amplitude information.

The present invention is achieved in that

A kind of bit synchronizer that is used for differential offset quadriphase keying demodulator is characterized in that described device comprises:

Calculus of differences unit, geometric ratio merge cells, up-sampling processing unit, bit synchronization error-detecting/comparator unit, loop filter unit, voltage control oscillator unit, N select Unit 1, judgement/output unit;

, entered the calculus of differences unit and do respectively to become differential signal behind the calculus of differences as input signal by the multichannel over-sampling baseband signal of intelligent antenna channel output, the baseband signal that participates in calculus of differences is a symbol period at interval;

The multichannel differential signal is merged into one road differential signal after by the geometric ratio merge cells;

The supreme sample processing unit of differential signal after synthetic, the differential signal sample rate of handling through up-sampling reaches sample/symbol N time;

The up-sampling signal is admitted to bit synchronization error-detecting/comparator unit, at first finish M power operation, through M power operation back modulation symbol bit synchronous influence is eliminated, the output of M power is re-used as an input of sampling error comparator in bit synchronization error-detecting/comparator unit, another of sampling error comparator is input as the output signal of local voltage controlled oscillator in bit synchronization error-detecting/comparator unit, determine optimum sampling estimated value constantly in N the sampling of every symbol by bit synchronization error-detecting/comparator unit, rising edge or trailing edge with the voltage controlled oscillator output waveform compares then, to produce the sampling error signal;

The sampling error signal is sent into loop filter unit, after the loop filter Filtering Processing, send into voltage control oscillator unit, the phase of output signal of control voltage control oscillator unit is done in advance/lags behind to move, the output signal driving N of voltage control oscillator unit is selected Unit 1, from N the sampling of every symbol of geometric ratio merge cells, select best sampled value and send into judgement/output unit, from judgement/output unit output modulation signal.

Described up-sampling unit adopts zero padding to add the filtering interpolation device and realizes.

Described bit synchronization error-detecting/comparator unit:

By two squarers, make nonlinear operation, the optimum sampling moment and frequency offset estimating are by asking following formula to minimize acquisition:

$\underset{\{t_j,\mathrm{\δ\θ}}{\min }\underset{i=1}{\overset{M}{\mathrm{\Σ}}}{(\mathrm{\δ\θ}*M-M\×\mathrm{\Δ}{\mathrm{\ψ}}^e\left(t_j\right))}^2;$

Described nonlinear operation comprises: to merging into the phase place rotation of one tunnel differential signal work-π/4 behind the geometric ratio merge cells, the postrotational signal of phase place is done the computing of M power;

Seek the sampled point of signal phase minimum, realize by signal phase being done differential/Sign (x) computing, with the rising edge of sampling clock/or trailing edge lock onto the sampled point of signal phase minimum, it is synchronous to get final product completion bit, through the output signal after differential/Sign (x) computing is two level logic signals with rising edge and trailing edge, the zero crossing of differential value promptly corresponding rising edge and trailing edge, Sign (x) then is the symbolic operation of getting to variable x, and its output makes signal x become two level signals.

Constitute bit synchronous loop by sampling error comparator, loop filter, voltage controlled oscillator, make loop converge to optimum sampling automatically constantly, loop convergence is to the optimum sampling moment, and frequency offset estimating/compensation is carried out on optimum sampling sample of signal constantly;

Described sampling error comparator is used for the phase place of comparator input signal and the phase place of voltage controlled oscillator output signal, phase of input signals is the rising edge or the trailing edge of two level signals of differentiator/Sign (x) output herein, the sampling error comparator produces the error signal that reflects this relation according to both phase relations, the error signal that produces is by after the loop filter filtering, the phase place of control voltage controlled oscillator is done the lead-lag adjustment, adjust sampling instant according to this, the sampling instant signal controlling N of voltage controlled oscillator output selects a unit, from the differential output signal of every symbol N sampling, select optimum sampling point to send decision unit, finish signal demodulation output.

Described sampling error comparator realized by register FIFO1 and FIFO2, receives the phase place of the output signal of the phase place of two level signals of differentiator/Sign (x) output and voltage controlled oscillator respectively.

Described loop filter is realized by logical block, logical block with the output of the rising edge of two level signals of differentiator/Sign (x) output or trailing edge, voltage controlled oscillator output signal sum counter as input signal, error controling signal after the generation Filtering Processing, the error controling signal after the Filtering Processing is controlled voltage controlled oscillator.

Described voltage controlled oscillator is made up of shift register, adder unit and register cell;

Shift register is that the clock of N times of symbol rate (NFs) drives and to make cyclic shift by frequency, the first value initialization of shift register, and promptly the 1st is that N position, 1, the N/2+1 position to the is 0 to the N/2 position;

The accumulator of the output signal of described logical block by being made up of adder and register, the output of a certain position of circulating register as voltage controlled oscillator is selected in output control N Unit 1 of accumulator.

Described logical block realizes sampling error comparison and loop filtering;

At first in the output signal of register FIFO1, judge whether exist in the signal rising edge and and trailing edge, do different processing for rising edge and trailing edge;

Secondly, logical block will judge whether rising edge or the trailing edge among the register FIFO1 meets the demands, to guarantee that the input signal that meets the demands enters the sampling error comparator, whether keep constant certain time span that reaches at this simultaneously by the front and back level of judging rising edge or trailing edge, eliminate the influence of disturbing whereby, prevent that loop from hanging;

Sampling error by sign (FIFO1-FIFO2) and-sign (FIFO1-FIFO2) unit finishes, error signal when corresponding respectively to rising edge and trailing edge, it is output as: be output as 1 when the rising edge of signal among the leading FIFO2 of the rising edge of signal among the FIFO1, otherwise be 0;

Sampling error is output as one by 0 and 1 sequence of forming, this sequence enters the shift register in the logical block, the degree of depth of this shift register is n (n is an odd number), and the output E of the value C1C2C3...Cn sum counter of shift register is obtained the output of logical block by the truth table of ROM as the address.

The truth table of described ROM is used to realize the function of loop filter, loop filter be input as signal C1C2C3...Cn, logical block is output as B1B0, the output signal E of counter is used for changing the bandwidth of loop filter;

When E=0 and E=1, ROM table adopts different logical relations that the output signal B1B0 of input signal C1C2C3...Cn and filter is shone upon, its logical relation is: when E=1, if judge among the input signal C1C2C3...Cn that leading number of times is more than the number of times that lags behind, promptly 1 number is greater than 0 number, then filter is output as to lag behind and adjusts, be that output valve is B1=1, B0=1, wherein represent to do the lead-lag operation during B0=1, and representing not do the lead-lag operation during B0=0, B1=1 represents to do hysteretic operation, and B1=0 represents to do leading operation;

Otherwise if judge among the input signal C1C2C3...Cn that leading number of times is less than the number of times of hysteresis, promptly 1 number is less than 0 number, and then filter is output as leading adjustment, and promptly output valve is B1=0, B0=1;

When E=0, have only all to be judged as in advance, promptly complete 1 among the input signal C1C2C3...Cn, then filter output is done to lag behind and is adjusted, and promptly exports B1=1, B0=1;

Otherwise, have only all to be judged as hysteresis among the input signal C1C2C3...Cn, promptly complete 0, then leading the adjustment done in filter output, promptly exports B1=0, B0=1;

Lead-lag adjustment, i.e. B0=0 are not made in all the other situation filter outputs;

The output B1B0 of logical block sends to the sampling instant phase place adjustment that voltage controlled oscillator removes to control voltage controlled oscillator.

Effect of the present invention is:

Handle because a plurality of passage baseband signals of antenna system are made diversity in the mode of geometric ratio merging, improved the Performance And Reliability of bit synchronizer in wireless fading channel greatly;

Adopted a kind of new, operate based on signal phase, NDA class bit synchronization error-detecting/comparator in the bit synchronizer, overcome based on signal amplitude class bit synchronization error-detector circuit (as the Gardner method), to Pi/4 DQPSK signal amplitude distortion sensitive issue;

The required additional circuit of DA method symbol aligned has also been saved in the employing of NDA class bit synchronization error-detecting/comparator, makes the simplified control of bit synchronization control circuit;

Device of the present invention has also comprised the handover mechanism of DA/NDA mode, makes the detection of sampling error both can be operated in the NDA mode, can be operated in the DA mode again, with further raising performance, makes simultaneously and realizes having more flexibility;

At last, because the introducing of sampling error pre-detection mechanism strengthens the resistivity that input is disturbed, prevented that simultaneously synchronization loop from hanging the problem of (Hang Up).

Description of drawings

The structured flowchart of Fig. 1 bit synchronizer of the present invention;

The structural representation of Fig. 2 calculus of differences of the present invention unit, geometric ratio merge cells and up-sampling processing unit;

Realize the structural representation of nonlinear operation and the minimum sampled point of searching signal phase in Fig. 3 bit synchronization error-detecting/comparator unit of the present invention;

Fig. 4 structural representation of forming Bit-synchronous Circle by sampling error comparator, loop filter, NCO of the present invention;

A specific implementation schematic diagram of Fig. 5 NCO of the present invention unit;

A specific implementation schematic diagram of logical block in Fig. 6 loop filter unit of the present invention.

Embodiment

Pi/4 DQPSK demodulator bit synchronizer of the present invention is made of 1 following plurality of units) the calculus of differences unit; 2) geometric ratio merge cells; 3) up-sampling processing unit; 4) bit synchronization error-detecting/comparator unit; 5) loop filter unit; 6) NCO unit; 7) N selects a unit; 8) judgement/output unit.

The input signal of demodulator bit synchronizer is the multichannel over-sampling baseband signal of many antennas (smart antenna) passage output, this multichannel over-sampling baseband signal at first enters the calculus of differences unit and does respectively to become differential signal behind the calculus of differences, participates in symbol period in baseband signal interval of calculus of differences;

The multichannel differential signal is merged into one road differential signal after by the geometric ratio merge cells, and geometric ratio merges a kind of mode of handling as diversity, has improved the Performance And Reliability of bit synchronization in wireless fading channel greatly;

Differential signal after synthetic is through the up-sampling processing unit, and the differential signal sample rate of process up-sampling reaches sample/symbol N time, has improved bit synchronous precision;

The up-sampling signal is at first finished M power operation after being admitted to bit synchronization error-detecting/comparator unit, through M power operation back modulation symbol bit synchronous influence is eliminated, the output of M power is re-used as an input of sampling error comparator in bit synchronization error-detecting/comparator unit, another of sampling error comparator is input as the output signal of local NCO in bit synchronization error-detecting/comparator unit, bit synchronization error-detecting/comparator unit is determined (in N the sampling of every symbol) optimum sampling estimated value constantly, rising edge or trailing edge with the NCO output waveform compares then, to produce the sampling error signal;

The sampling error signal is sent into loop filter unit, after the loop filter Filtering Processing, send into the NCO unit, the phase of output signal of control NCO unit is done in advance/lags behind to move, the output signal driving N of NCO unit is selected a unit, from N the sampling of every symbol of geometric ratio merge cells, select best sampled value and send into decision unit, export user's modulation signal from decision unit, thereby finish the bit synchronous operation of Pi/4 DQPSK demodulator.

Below in conjunction with accompanying drawing concrete an enforcement of the present invention is described in further detail:

Suppose that demodulator adopts the antenna system of 4 antennas, the over-sampling baseband signal of 4 receive path outputs is respectively z ₁, z ₂, z ₃, z ₄, for convenience, be 1 at this hypothesis over-sampling rate.Baseband signal { z then _i, i=1,2,3,4} can be expressed as follows:

z _i(k)＝c _i(k)exp(j*2πΔfkT+θ _k+θ _0，i)???????????????????(1)

C in the formula _i(k) be i antenna baseband signal amplitude, Δ f is the transmitting-receiving frequency deviation, and T is a symbol period, θ _kBe k modulating signal phase, θ _{0, i}It is the signal first phase of i passage.

Signal z _iBe output as u through behind the difference unit _i, then calculus of differences is shown below:

$u_i\left(k\right)=z_i\left((k+1)T\right)\×{z_i}^{*}\left(\mathrm{kT}\right)$

${=|z}_i(k+1)z_i\left(k\right)|\exp$ $(j*2\mathrm{\π\ΔfT}+j*{\mathrm{\Φ}}_k+j*{\mathrm{\Θ}}_{n,i})-------\left(2\right)$

Φ in the formula _k=θ _K+1-θ _kBe the differential modulation phase place, and Φ is arranged _k∈ [π/4,3 π/4 ,-π/4 ,-3 π/4], Θ _{N, i}Be noise phase.

For mobile communication system, since the rapid fading of wireless channel, signal z _iAmplitude take place to change on a large scale.For multiaerial system, as long as spacing d 〉=λ/2 between the antenna, (λ is a wavelength), the decline of space generation receives the signal that comes to a plurality of antennas and can not produce identical influence like this, fading characteristic separately is separate, improves signal quality so the signal that can utilize a plurality of antennas to receive carries out space diversity.At this, the mode that adopts the geometric ratio in the space diversity reception to communicate to merge.That is:

$u\left(k\right)=\underset{i=1}{\overset{4}{\mathrm{\Σ}}}{u}_i\left(k\right)------\left(3\right)$

The mode that adopts geometric ratio to merge can improve the receiver bit synchronizer in the performance of fading channel and the reliability of work.

Signal u (k) after geometric ratio merges enters the up-sampling unit, and the up-sampling unit is brought up to sample/symbol N time with the sample rate of signal u (k).The sample rate height can improve the precision that sampling instant is estimated, reduces sampling instant shake (Jitter), at this N=50.In concrete implementation process, the up-sampling unit can adopt zero padding to add the filtering interpolation device and realize, as cic filter, as shown in Figure 2.The output of up-sampling unit is represented with u (m).

The output u (m) of up-sampling unit enters bit synchronization error-detecting/comparator unit, in order from u (m), to obtain optimum sampling estimated value constantly, at this described method of Sandeep Chennnakeshu article is improved (Sandeep Chennnakeshu, Differential Detection ofpi/4 shifted DQPSK for Digital Cellular Radio, IEEE Transactionon Vehicular Technology, vol.42, No.1,1993, pp.46-57).SandeepChennnakeshu obtains the optimum sampling moment and frequency offset estimating by the following expression formula of minimization:

$\underset{\{t_j,\mathrm{\δ\θ}}{\min }\underset{i=1}{\overset{M}{\mathrm{\Σ}}}{({\mathrm{\Φ}}_i+\mathrm{\δ\θ}-{\mathrm{\Δ\φ}}_i^e\left(t_j\right))}^2-------\left(4\right)$

In the formula: t _jOptimum sampling in=each symbol constantly;

Φ _i=the i differential modulation phase place;

The phase error that the frequency deviation of δ θ=one a mark space correspondence causes;

M=lead code symbol numbers.

Adopt M known lead code (Φ in the article of Sandeep Chennnakeshu _iKnown) add bidimensional search finding (4) formula, obviously, the method for Sandeep Chennnakeshu belongs to DA method/forward direction structure, because it will utilize known preamble information.Consider that the SandeepChennnakeshu method need align with lead code,, need bidimensional search consuming time simultaneously,, this method is improved at this so need extra synchronism link.Improved first is that method with (4) formula changes the NDA method into from the DA method, second is to change search for constantly based on the optimum sampling consuming time of forward direction structure as loop processed into, and this loop makes loop converge to optimum sampling automatically constantly by error-detecting/comparing element, loop filter, voltage controlled oscillator NCO.In case loop convergence to optimum sampling constantly, then frequency offset estimating/compensation is carried out on optimum sampling sample of signal constantly, has reduced operand, makes that FPGA/DSP realizes simplifying.

Adopt the new method after improving, except having eliminated DA method complex structure, need outside the shortcoming of additional synchronization link, it is very easy that simultaneous operation also becomes, in case promptly the demodulator error rate surpasses certain thresholding, then can start synchronism link, not need the SandeepChennnakeshu method must during preamble sequence, realize synchronous condition in any position of transmission data.

The DA method is become the NDA method to be finished by following nonlinear operation:

1) phase place of (3) formula work-π/4 is rotated;

2) the postrotational signal of phase place is done the computing of M=4 power;

Because Φ _i∈ [π/4,3 π/4 ,-π/4 ,-3 π/4] then passes through the operation of above-mentioned (1) and (2) two steps, and the differential modulation phase place becomes 4 * (Φ _i-π/4) ∈ [0,2 π ,-2 π ,-4 π] is so the differential modulation phase effect is removed by above-mentioned two steps.

The impact analysis that the differential modulation phase place has been removed in M power operation is as follows, establishes signal u (m) through behind the nonlinear operation of above-mentioned two steps, and signal is designated as v (m), then the phase place of v (m) Can be expressed as:

Differential phase Δ φ in the formula _i ^e(t _j) be differential modulation phase place Φ _iWith to Φ _iDepart from phase delta ψ ^e(t _j) two parts composition, promptly

Δφ _i ^e(t _j)＝Φ _i+Δψ ^e(t _j)????????????????????????(6)

So, Can further be expressed as follows:

And M* Φ _iSince be change 0 after two top nonlinear operation steps, so have:

Sampling instant estimation and frequency offset estimating then become the minimized process of following formula of asking:

$\underset{\{t_j,\mathrm{\δ\θ}}{\min }\underset{i=1}{\overset{M}{\mathrm{\Σ}}}{(\mathrm{\δ\θ}*M-M{\×\mathrm{\Δ\ψ}}^e\left(t_j\right))}^2------\left(9\right)$

Minimized target function in the formula, the present invention adopts loop fashion to realize.In order to realize the minimized target of following formula, in N=50 each symbol sampler cycle doubly, seek the sampled point of signal v (m) phase place minimum, with the rising edge of sampling clock/or trailing edge to lock onto this (signal v (m) phase place minimum) sampled point can completion bit synchronous.The sampled point of seeking signal v (m) phase place minimum is by doing differential/Sign (x) computing to signal v (m) phase place, and this operation can be expressed as follows:

z(m)=sign{y(m+1)-y(m)}????????????????????????(10)

Sign in the formula (x) is for getting symbolic operation.Like this, be two level logic signals through the output signal after differential/Sign (x) computing with rising edge and trailing edge, the zero crossing of differential value promptly corresponding rising edge and trailing edge.

Because a slot length of PHS system is 120 symbols, during this period, frequency shift (FS) can be thought and not change, so the phase place δ θ that is caused by frequency deviation is a constant.Obviously, by 9 formulas as seen, phase place δ θ can not exert an influence to the minimization of 9 formulas, so above-mentioned bit synchronization error detector can be operated in before the compensate of frequency deviation as the Gardner method.

Fig. 3 is the schematic diagram of realizing nonlinear operation and seeking the minimum sampled point of signal v (m) phase place, among the figure squarer 1 and squarer 2 combine realize above-mentioned 1) and 2) nonlinear operation, simultaneously, among the figure preamble signal and remainder signal have been made differentiated treatment.Because the PHS system pilot code adopts 0110 repetitive sequence, then differential phase presents cornerwise arrangement, i.e. Φ on planisphere _i∈ [3 π/4 ,-π/4] obviously need not to do the operation of M=4 power this moment, and the operation that only need carry out M=2 power gets final product.The switching of M=2 power of M=4 sum of powers cooperates 2 to select 1 device to finish by the counter among Fig. 3.Because lead code has 32 symbols, in case 32 lead code sign-offs, the output control 2 of counter selects 1 device that M=2 power is switched to power M=4 time.

Fig. 4 is the realization schematic diagram of Bit-synchronous Circle.Bit-synchronous Circle mainly comprises following three parts:

1) sampling error comparator;

2) loop filter;

3)NCO。

The course of work of Bit-synchronous Circle is: the sampling error comparator is used for the phase place of comparator input signal and the phase place of NCO output signal, and phase of input signals is the rising edge or the trailing edge of two level signals of differentiator/Sign (x) output herein.Error comparator produces the error signal that reflects this relation according to both phase relations, the error signal that produces is by after the loop filter filtering, send into the NCO unit and do the lead-lag adjustment with the phase place of control NCO, adjust sampling instant according to this, the sampling instant signal controlling N of NCO output selects a unit, from the differential output signal of every symbol N sampling, select optimum sampling point to send decision unit, finish signal demodulation output.

An output signal that input signal is a differentiator among Fig. 3 of sampling error comparator is designated as z (m).Another input signal is the output signal of NCO.

The output signal of signal z (m) and NCO is sent among register FIFO1 and the FIFO2 respectively, logical block with the output of these two signal sum counters as input signal, error controling signal after the generation Filtering Processing, the error controling signal after the Filtering Processing is controlled NCO.

Fig. 5 is that of NCO unit realizes schematic diagram, and NCO is by shift register, and N selects Unit 1, and adder unit and register cell are formed.Shift register is that the clock of N times of symbol rate (NFs) drives and to make cyclic shift by frequency, and the initial value of shift register is by illustrated pattern initialization, and promptly when N=50, then the 1st～25 is 1, and the 26th～50 be 0.The accumulator of the output signal of logical block by being made up of adder and register, the output control N of accumulator select Unit 1 to select the output of a certain position of circulating register as NCO.

Fig. 6 is the realization schematic diagram of logical block.Logical block is mainly finished the function of sampling error comparison and loop filter.

Logical block at first in the output signal of FIFO1, judge whether exist in the signal rising edge and and trailing edge, do different processing for rising edge and trailing edge.Secondly, logical block will judge whether rising edge or the trailing edge among the FIFO1 meets the demands, this is a kind of error signal pre-detection mechanism, to guarantee that the input signal that meets the demands enters error comparator, whether keep constant certain time span (as length=20) that reaches at this simultaneously by the front and back level of judging rising edge or trailing edge, eliminate the influence of disturbing whereby, prevent that loop from hanging (Hang up).Sampling error by sign (FIFO1-FIFO2) and-error signal when corresponding respectively to rising edge and trailing edge is finished in sign (FIFO1-FIFO2) unit.It is output as: be output as 1 when the rising edge of signal among the leading FIFO2 of the rising edge of signal among the FIFO1, otherwise be 0.Sampling error is output as one by 0 and 1 sequence of forming, this sequence enters a shift register, the degree of depth of this register is n (n is an odd number), the output E of the value C1C2C3...Cn sum counter of shift register obtains the output B1B0 of logical block as the address by the truth table of following ROM, and n selects 3 in following table.

ROM table is used for realizing the function of loop filter at this, loop filter be input as signal C1C2C3...Cn, be output as B1B0.Wherein the output signal E of counter is used for changing the bandwidth of loop filter, concretely, when E=0 and E=1, ROM table adopts different logical relations that the output signal B1B0 of input signal C1C2C3...Cn and filter is shone upon, its logical relation is: when E=1, if judge among the input signal C1C2C3...Cn that leading number of times is more than the number of times that lags behind, promptly 1 number is greater than 0 number, then filter is output as to lag behind and adjusts, and promptly output valve is B1=1, B0=1, wherein represent to do the lead-lag operation during B0=1, and representing not do the lead-lag operation during B0=0, B1=1 represents to do hysteretic operation, and B1=0 represents to do leading operation; Otherwise if judge among the input signal C1C2C3...Cn that leading number of times is less than the number of times of hysteresis, promptly 1 number is less than 0 number, and then filter is output as leading adjustment, and promptly output valve is B1=0, B0=1.And when E=0, have only all to be judged as in advance, promptly complete 1 among the input signal C1C2C3...Cn, then filter output is done to lag behind and is adjusted, and promptly exports B1=1, B0=1; Otherwise, have only all to be judged as hysteresis among the input signal C1C2C3...Cn, promptly complete 0, then leading the adjustment done in filter output, promptly exports B1=0, B0=1; Lead-lag adjustment, i.e. B0=0 are not made in all the other situation filter outputs.

The output B1B0 of logical block sends to the sampling instant phase place adjustment that NCO removes to control NCO.

The ROM table

????E	????C3	????C2	????C1	?Sign?Bit ????B1	??Bit?val ????B0
						????0	????0	????0	????0	????1	????1
????0	????0	????0	????1	????0	????0
						????0	????0	????1	????0	????0	????0
????0	????0	????1	????1	????0	????0
						????0	????1	????0	????0	????0	????0
????0	????1	????0	????1	????0	????0
						????0	????1	????1	????0	????0	????0
????0	????1	????1	????1	????0	????1
						????1	????0	????0	????0	????1	????1
????1	????0	????0	????1	????1	????1
						????1	????0	????1	????0	????1	????1
????1	????0	????1	????1	????0	????1
						????1	????1	????0	????0	????1	????1
????1	????1	????0	????1	????0	????1
						????1	????1	????1	????0	????0	????1
????1	????1	????1	????1	????0	????1

Claims (9)

1, a kind of bit synchronizer that is used for differential offset quadriphase keying demodulator is characterized in that described device comprises:

Calculus of differences unit, geometric ratio merge cells, up-sampling processing unit, bit synchronization error-detecting/comparator unit, loop filter unit, voltage control oscillator unit, N select Unit 1, judgement/output unit;

, entered the calculus of differences unit and do respectively to become differential signal behind the calculus of differences as input signal by the multichannel over-sampling baseband signal of intelligent antenna channel output, the baseband signal that participates in calculus of differences is a symbol period at interval;

The multichannel differential signal is merged into one road differential signal after by the geometric ratio merge cells;

The supreme sample processing unit of differential signal after synthetic, the differential signal sample rate of handling through up-sampling reaches sample/symbol N time;

The up-sampling signal is admitted to bit synchronization error-detecting/comparator unit, at first finish M power operation, through M power operation back modulation symbol bit synchronous influence is eliminated, the output of M power is re-used as an input of sampling error comparator in bit synchronization error-detecting/comparator unit, another of sampling error comparator is input as the output signal of local voltage controlled oscillator in bit synchronization error-detecting/comparator unit, determine optimum sampling estimated value constantly in N the sampling of every symbol by bit synchronization error-detecting/comparator unit, rising edge or trailing edge with the voltage controlled oscillator output waveform compares then, to produce the sampling error signal;

The sampling error signal is sent into loop filter unit, after the loop filter Filtering Processing, send into voltage control oscillator unit, the phase of output signal of control voltage control oscillator unit is done in advance/lags behind to move, the output signal driving N of voltage control oscillator unit is selected Unit 1, from N the sampling of every symbol of geometric ratio merge cells, select best sampled value and send into judgement/output unit, from judgement/output unit output modulation signal.

2, be used for the bit synchronizer of differential offset quadriphase keying demodulator according to claim 1, it is characterized in that:

Described up-sampling unit adopts zero padding to add the filtering interpolation device and realizes.

3, the bit synchronizer that is used for differential offset quadriphase keying demodulator according to claim 1 is characterized in that described bit synchronization error-detecting/comparator unit:

By two squarers, make nonlinear operation, the optimum sampling moment and frequency offset estimating are by asking following formula to minimize acquisition:

$\underset{\{t_j,\mathrm{\δ\θ}}{\min }\underset{i=1}{\overset{M}{\mathrm{\Σ}}}{(\mathrm{\δ\θ}*M-M{\×\mathrm{\Δ\ψ}}^e\left(t_j\right))}^2;$

Described nonlinear operation comprises: to merging into the phase place rotation of one tunnel differential signal work-π/4 behind the geometric ratio merge cells, the postrotational signal of phase place is done the computing of M power;

Seek the sampled point of signal phase minimum, realize by signal phase being done differential/Sign (x) computing, with the rising edge of sampling clock/or trailing edge lock onto the sampled point of signal phase minimum, it is synchronous to get final product completion bit, through the output signal after differential/Sign (x) computing is two level logic signals with rising edge and trailing edge, the zero crossing of differential value promptly corresponding rising edge and trailing edge, Sign (x) then is the symbolic operation of getting to variable x, and its output makes signal x become two level signals.

4, be used for the bit synchronizer of differential offset quadriphase keying demodulator according to claim 1, it is characterized in that:

Constitute bit synchronous loop by sampling error comparator, loop filter, voltage controlled oscillator, make loop converge to optimum sampling automatically constantly, loop convergence is to the optimum sampling moment, and frequency offset estimating/compensation is carried out on optimum sampling sample of signal constantly;

Described sampling error comparator is used for the phase place of comparator input signal and the phase place of voltage controlled oscillator output signal, phase of input signals is the rising edge or the trailing edge of two level signals of differentiator/Sign (x) output herein, the sampling error comparator produces the error signal that reflects this relation according to both phase relations, the error signal that produces is by after the loop filter filtering, the phase place of control voltage controlled oscillator is done the lead-lag adjustment, adjust sampling instant according to this, the sampling instant signal controlling N of voltage controlled oscillator output selects a unit, from the differential output signal of every symbol N sampling, select optimum sampling point to send decision unit, finish signal demodulation output.

5, be used for the bit synchronizer of differential offset quadriphase keying demodulator according to claim 1, it is characterized in that:

Described sampling error comparator realized by register FIFO1 and FIFO2, receives the phase place of the output signal of the phase place of two level signals of differentiator/Sign (x) output and voltage controlled oscillator respectively.

6, be used for the bit synchronizer of differential offset quadriphase keying demodulator according to claim 1, it is characterized in that:

Described loop filter is realized by logical block, logical block with the output of the rising edge of two level signals of differentiator/Sign (x) output or trailing edge, voltage controlled oscillator output signal sum counter as input signal, error controling signal after the generation Filtering Processing, the error controling signal after the Filtering Processing is controlled voltage controlled oscillator.

7, be used for the bit synchronizer of differential offset quadriphase keying demodulator according to claim 1, it is characterized in that:

Described voltage controlled oscillator is made up of shift register, adder unit and register cell;

Shift register is that the clock of N times of symbol rate (NFs) drives and to make cyclic shift by frequency, the first value initialization of shift register, and promptly the 1st is that N position, 1, the N/2+1 position to the is 0 to the N/2 position;

The accumulator of the output signal of described logical block by being made up of adder and register, the output of a certain position of circulating register as voltage controlled oscillator is selected in output control N Unit 1 of accumulator.

8, as being used for the bit synchronizer of differential offset quadriphase keying demodulator as described in the claim 6, it is characterized in that:

Described logical block realizes sampling error comparison and loop filtering;

At first in the output signal of register FIFO1, judge whether exist in the signal rising edge and and trailing edge, do different processing for rising edge and trailing edge;

Secondly, logical block will judge whether rising edge or the trailing edge among the register FIFO1 meets the demands, to guarantee that the input signal that meets the demands enters the sampling error comparator, whether keep constant certain time span that reaches at this simultaneously by the front and back level of judging rising edge or trailing edge, eliminate the influence of disturbing whereby, prevent that loop from hanging;

Sampling error by sign (FIFO1-FIFO2) and-sign (FIFO1-FIFO2) unit finishes, error signal when corresponding respectively to rising edge and trailing edge, it is output as: be output as 1 when the rising edge of signal among the leading FIFO2 of the rising edge of signal among the FIFO1, otherwise be 0;

Sampling error is output as one by 0 and 1 sequence of forming, this sequence enters the shift register in the logical block, the degree of depth of this shift register is n (n is an odd number), and the output E of the value C1C2C3...Cn sum counter of shift register is obtained the output of logical block by the truth table of ROM as the address.

9, as being used for the bit synchronizer of differential offset quadriphase keying demodulator as described in the claim 8, it is characterized in that:

The truth table of described ROM is used to realize the function of loop filter, loop filter be input as signal C1C2C3...Cn, logical block is output as B1B0, the output signal E of counter is used for changing the bandwidth of loop filter;

When E=0 and E=1, ROM table adopts different logical relations that the output signal B1B0 of input signal C1C2C3...Cn and filter is shone upon, its logical relation is: when E=1, if judge among the input signal C1C2C3...Cn that leading number of times is more than the number of times that lags behind, promptly 1 number is greater than 0 number, then filter is output as to lag behind and adjusts, be that output valve is B1=1, B0=1, wherein represent to do the lead-lag operation during B0=1, and representing not do the lead-lag operation during B0=0, B1=1 represents to do hysteretic operation, and B1=0 represents to do leading operation;

Otherwise if judge among the input signal C1C2C3...Cn that leading number of times is less than the number of times of hysteresis, promptly 1 number is less than 0 number, and then filter is output as leading adjustment, and promptly output valve is B1=0, B0=1;

When E=0, have only all to be judged as in advance, promptly complete 1 among the input signal C1C2C3...Cn, then filter output is done to lag behind and is adjusted, and promptly exports B1=1, B0=1;

Otherwise, have only all to be judged as hysteresis among the input signal C1C2C3...Cn, promptly complete 0, then leading the adjustment done in filter output, promptly exports B1=0, B0=1;

Lead-lag adjustment, i.e. B0=0 are not made in all the other situation filter outputs;

The output B1B0 of logical block sends to the sampling instant phase place adjustment that voltage controlled oscillator removes to control voltage controlled oscillator.

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