CN107831696B

CN107831696B - IRIG-B direct current code decoding method

Info

Publication number: CN107831696B
Application number: CN201711131469.9A
Authority: CN
Inventors: 汪战魁; 刘永祥; 耿紫妍; 王洪亮; 李绪勇; 韩学军; 陈龙兴; 张瑞杰; 朱宁超; 成印沙; 汪相坤
Original assignee: Xuchang Intelligent Relay Co ltd
Current assignee: Xuchang Intelligent Relay Co ltd
Priority date: 2017-11-15
Filing date: 2017-11-15
Publication date: 2020-07-28
Anticipated expiration: 2037-11-15
Also published as: CN107831696A

Abstract

The invention relates to an IRIG-B direct current code decoding method, which comprises the following steps: the method comprises the following steps: capturing an IRIG-B direct current code pulse rising edge, and starting delay timing; step two: delaying for 3ms for three times continuously, reading the input state of the IO port once every time of delaying, and recording the value of 1 or 0; step three: judging which code element is '000' is code element 0, '100' is code element 1 and '110' is code element P according to the three recorded values in the step two; step four: delaying for 4ms, reading the input state of the IO port once, and recording the value 1 or 0; delaying for 3ms, reading the input state of the IO port once, and recording the value 1 or 0; delaying for 3ms again, reading the input state of the IO port once, and recording the value 1 or 0; step five: judging which code element is '000' is code element 0, '100' is code element 1 and '110' is code element P according to the three recorded values in the fourth step; step six: and repeating the fourth step and the fifth step in sequence to judge which code element the subsequent code element is.

Description

IRIG-B direct current code decoding method

Technical Field

The invention belongs to the field of synchronous time service of B codes, and particularly relates to an IRIG-B direct-current code decoding method.

Background

The IRIG-B code is called B code for short, loads time synchronization signals and time code information such as second, minute, time, day and the like into a signal carrier, has the characteristics of universal world, standardized interface, suitability for remote transmission, easy realization and the like, and is widely applied to the fields of industrial control, communication, power system measurement and protection and the like in China.

The B-code signal is a time-series code of one frame per second, the basic code elements are "0" code element, "1" code element and "P" code element, each code element occupies 10ms of time, one frame of the series code contains 100 code elements, the pulse widths corresponding to the code elements "0" and "1" are 2 ms and 5ms, the "P" code element is a position code element, the corresponding pulse width is 8 ms, and the schematic diagram of the basic code elements of the B-code information is shown in fig. 1.

At present, the domestic B code decoding mainly has the following two modes:

1. respectively triggering external interruption through the rising edge and the falling edge of the B code signal to calculate the time of the high level of the B code signal, namely the pulse width, so as to judge which code element is;

2. continuously sampling a large number of B code signals at a certain frequency, counting the number of the B code signals collected when the signals are at high level, and judging which code element is by distinguishing the number of the high level.

Both of the two methods have great defects, the first method can generate 2 external interrupts per symbol, and then one frame of symbols generates 200 external interrupts per second, which is a great burden for CPU operation and even causes system crash; the second mode can be realized by adopting high-performance chips such as an FPGA (field programmable gate array), and the like, so that the method is high in cost, complex in algorithm, high in resource consumption, low in synchronization precision, very weak in anti-interference capability at the rising edge or the falling edge of a code element, easy to cause misjudgment and poor in stability.

Disclosure of Invention

The invention overcomes the defects of the prior art, provides the IRIG-B direct current code decoding method, and has the advantages of simple algorithm, strong anti-interference capability, extremely low requirement on CPU performance, high time service precision, stability, reliability and the like.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows: an IRIG-B direct current code decoding method is characterized in that: the method comprises the following steps:

the method comprises the following steps: capturing an IRIG-B direct current code pulse rising edge, and starting delay timing;

step two: after delaying for 3ms for the first time, reading the input state of an IO port once, and recording the

value

1 or 0; after delaying for 3ms for the second time, reading the input state of the IO port for one time, and recording the

value

1 or 0; after delaying for 3ms for the third time, reading the input state of the IO port once, and recording the

value

1 or 0;

step three: judging which code element is '000' is code element 0, '100' is code element 1 and '110' is code element P according to the three recorded values in the step two;

step four: delaying for 4ms, reading the input state of the IO port once, and recording the

value

1 or 0; delaying for 3ms, reading the input state of the IO port once, and recording the

value

1 or 0; delaying for 3ms again, reading the input state of the IO port once, and recording the

value

1 or 0;

step five: judging which code element is '000' is code element 0, '100' is code element 1 and '110' is code element P according to the three recorded values in the fourth step;

step six: and repeating the fourth step and the fifth step in sequence to judge which code element the subsequent code element is.

Compared with the prior art, the invention has the following characteristics and advantages: the decoding method has extremely low requirement on the performance of a CPU (Central processing Unit), an ordinary IO port can read the IO state every 3ms without interruption, the influence on the operation of the CPU is extremely low, as can be easily seen from figure 2, the method has the advantages that the time interval of at least 1ms from the rising edge or the falling edge is used for reading the state of any code element, the signal stability during reading is ensured, the anti-interference capability is high, the correct judgment can be made only by identifying the first two values of the code element codes, the algorithm is simple, and the realization is easy.

Drawings

Fig. 1 is a schematic diagram of a B-code symbol.

Fig. 2 is a schematic diagram of a symbol sample of the present invention.

Detailed Description

For a better understanding of the present invention, reference will now be made to the following examples.

Referring to fig. 1-2, for the feature of 10ms of each symbol, the IO port input state is read once every 3ms, i.e., 3ms, 6ms, and 9ms of each symbol, and the symbols can be distinguished according to their values, where symbol 0 is "000", symbol 1 is "100", and symbol P is "110".

Since the remainder of 10 to 3 is 1, to ensure that the IO port input state can be read at 3ms, 6ms, and 9ms of each symbol, 1ms is delayed after the 3 rd reading of each symbol is completed, and then the reading of the next symbol is started, that is, the time interval for reading the IO state from the first symbol is sequentially: 3ms, 4ms, 3ms … ….

Taking the most common 51 singlechips as an example, the specific implementation method comprises the following steps:

1. triggering external interruption by the rising edge of any IRIG-B direct current code pulse, entering interruption to start a timer, exiting interruption, and starting delay timing;

2. delaying for 3ms, reading an IO pin state register of the single chip microcomputer once, and writing a

register value

1 or 0 into a first bit of a cache array;

3. delaying for 3ms again, reading the IO pin state register of the single chip microcomputer once, and writing the

register value

1 or 0 into the second bit of the cache array;

4. delaying for 3ms again, reading the IO pin state register of the single chip microcomputer once, and writing the

register value

1 or 0 into the third bit of the cache array;

5. judging which code element is '000' being code element 0, '100' being code element 1 and '110' being code element P according to the three-bit value of the buffer array;

6. delaying for 4ms, reading an IO pin state register of the single chip microcomputer once, and writing a

register value

1 or 0 into a first bit of a cache array;

7. delaying for 3ms, reading an IO pin state register of the single chip microcomputer once, and writing a

register value

1 or 0 into a second bit of the cache array;

8. delaying for 3ms again, reading the IO pin state register of the single chip microcomputer once, and writing the

register value

1 or 0 into the third bit of the cache array;

9. judging which code element is '000' being code element 0, '100' being code element 1 and '110' being code element P according to the three-bit value of the buffer array;

10. and 6, repeating the steps 6-9 in sequence, and judging which code element the subsequent code element is.

The decoding method has extremely low requirement on the performance of a CPU (Central processing Unit), an ordinary IO port can read the IO state every 3ms without interruption, the influence on the operation of the CPU is extremely low, as can be easily seen from figure 2, the method has the advantages that the time interval of at least 1ms from the rising edge or the falling edge is used for reading the state of any code element, the signal stability during reading is ensured, the anti-interference capability is high, the correct judgment can be made only by identifying the first two values of the code element codes, the algorithm is simple, and the realization is easy.

It should be noted that, for those skilled in the art, many changes and modifications can be made without departing from the spirit and scope of the invention, and the invention is not to be considered limited to the embodiments illustrated in the above description.

Claims

1. An IRIG-B direct current code decoding method is characterized in that: the method comprises the following steps:

step two: after delaying for 3ms for the first time, reading the input state of an IO port once, and recording the value 1 or 0; after delaying for 3ms for the second time, reading the input state of the IO port for one time, and recording the value 1 or 0; after delaying for 3ms for the third time, reading the input state of the IO port once, and recording the value 1 or 0;

step four: delaying for 4ms, reading the input state of the IO port once, and recording the value 1 or 0; delaying for 3ms, reading the input state of the IO port once, and recording the value 1 or 0; delaying for 3ms again, reading the input state of the IO port once, and recording the value 1 or 0;