CN111049718B

CN111049718B - CAN bus simulation monitoring method

Info

Publication number: CN111049718B
Application number: CN201911391307.8A
Authority: CN
Inventors: 张榕; 孙笠森; 孟琪; 安鹏伟; 刘冬; 李世峰; 康建涛; 王欣; 吕方雷; 柴振达
Original assignee: Beijing Jinghang Computing Communication Research Institute
Current assignee: Beijing Jinghang Computing Communication Research Institute
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2021-07-20
Anticipated expiration: 2039-12-30
Also published as: CN111049718A

Abstract

The invention belongs to the technical field of CAN bus communication engineering, and particularly relates to a CAN bus simulation monitoring method. Compared with the prior art, the CAN bus simulation monitoring scheme designed by the invention improves the real-time performance of data transmission by utilizing the advantages of a hardware scheme and a logic architecture; in addition, the functions of triggering control data to be transmitted and received, setting timing time to finish data transmission, setting data shielding reception and the like are added. The adaptability of the CAN bus in different industrial applications is improved, and various use requirements are met.

Description

CAN bus simulation monitoring method

Technical Field

The invention belongs to the technical field of CAN bus communication engineering, and particularly relates to a CAN bus simulation monitoring method.

Background

With the rapid development of information technology, the real-time requirement of users on communication based on the CAN bus is higher and higher. Meanwhile, more use requirements are provided for functions of receiving and sending data at fixed time, triggering control of receiving and sending data and the like, and particularly in industries with higher requirements on reliability and safety. However, most of the mature CAN communication modules or boards are in ms level in real time, and do not have the functions of regularly receiving and sending data or triggering control data receiving and sending and the like, so that the product performance of the CAN bus communication industry is limited.

The CAN communication module or board card which is the mainstream in the market has the following defects:

1) the real-time performance is poor. The CAN communication module or the CAN card has low working frequency and complex protocol analysis and data processing steps, and after receiving a sending instruction, the CAN communication module or the CAN card cannot send data to the CAN bus within 10us, so that each CAN node in the same CAN bus network is correspondingly asynchronous, uncertain time delay is generated, and logic judgment and control based on the CAN bus in the whole network are influenced.

2) The trigger control data transceiving function is insufficient. At present, most CAN communication modules or CAN cards have only one triggering source and single triggering condition, are simple in object-oriented, are triggered by external interruption, do not have a triggering and sending function, or have a single function of triggering and controlling data sending, only CAN determine whether data is sent or not through a triggering signal, and cannot selectively control and send a certain type or types of data through the triggering signal.

3) It has no timing transmission function. At present, most CAN communication modules or CAN cards only have the most basic data receiving or data sending function, do not consider complex industrial control scenes, do not have a timing sending function, and cannot set a certain future time point, namely when the time point arrives, the automatic data sending cannot be finished.

4) The data mask receiving function is insufficient. Most of the existing CAN communication modules or CAN cards have insufficient data shielding and receiving functions, CAN only perform shielding and receiving according to frame types and frame IDs, and do not have the function of selecting whether to perform shielding and receiving on frame formats or frame contents.

Disclosure of Invention

Technical problem to be solved

The technical problem to be solved by the invention is as follows: the problems that the real-time performance of the current CAN communication module or CAN card is poor, the receiving and sending functions of trigger control data are insufficient, the function of timing sending is not achieved, the function of data shielding and receiving is insufficient and the like are solved, the functions of the CAN communication module or CAN card are perfected, the adaptability of a CAN bus in different industry applications is improved, and various use requirements are met.

(II) technical scheme

In order to solve the above technical problem, the present invention provides a CAN bus simulation monitoring method, which is implemented based on a CAN bus simulation monitoring system, and the CAN bus simulation monitoring system includes: the device comprises a CAN bus transceiver, a reset timer, a reset module, a setting module, a clock calibration module, a timer reset module, a cache module, an extraction module, a data storage module to be sent, an analysis module, a time point updating module and a monitoring module; the data storage module to be sent comprises a first sending buffer area, a second sending buffer area and a third sending buffer area;

specifically, the CAN bus simulation monitoring method comprises the following steps:

step 1: electrifying a CAN bus simulation monitoring system;

step 2: the reset module resets; starting a reset timer from a first effective clock, and after the reset timing time is finished, finishing the reset by a reset module; in the process, each module in the CAN bus simulation monitoring system is restored to an initial state;

and step 3: the setting module sets the working mode, the local ID number, the target ID number, the ID number to be shielded and the baud rate of the CAN bus transceiver;

and 4, step 4: the calibration clock module sends out calibration clock pulses, the timer zero clearing module takes the pulses as a reference, the arrival time of the pulses is zero time, the zero clearing timer 1, the zero clearing timer 2 and the zero clearing timer 3 are reset, and the three timers are reset;

and 5: the CAN bus transceiver receives data and instructions of an upper computer, stores the data and the instructions while receiving the data and the instructions, and respectively stores the data and the instructions into a cache of a specified address of a cache module;

step 6: the extraction module takes out the first frame data from the cache of the cache module and stores the first frame data in a first sending buffer area of a data storage module to be sent;

and 7: the extraction module reads a first frame instruction from the cache of the cache module;

and 8: the analysis module analyzes the first frame instruction;

and step 9: the time point updating module updates the analyzed time point to the timer 1 in the step 4 according to the sending time point containing the data in the instruction;

step 10: the extraction module takes out the second frame data from the cache of the cache module and stores the second frame data in a second sending buffer area of the data storage module to be sent;

step 1: the extracting module reads the second frame instruction from the cache of the cache module;

step 12: the analysis module analyzes the second frame instruction;

step 13: the time point updating module updates the analyzed time point to the timer 2 in the step 4 according to the sending time point containing the data in the instruction;

step 14: the extracting module takes out the third frame data from the cache of the cache module and stores the third frame data in a third sending buffer area of the data storage module to be sent;

step 15: the extracting module reads a third frame instruction from the cache of the cache module;

step 16: the analysis module analyzes the third frame instruction;

and step 17: the time point updating module updates the analyzed time point to the timer 3 in the step 4 according to the sending time point containing the data in the instruction;

step 18: the CAN bus transceiver waits for the timer 1 to finish timing time;

step 19: when the time of the timer 1 is up, the CAN bus transceiver sends a local ID number, a target ID number and first buffer data according to a set working mode and a baud rate;

step 20: the method specifically comprises the following steps:

step 201, the CAN bus transceiver waits for the timer 2 to time;

step 202, a monitoring module monitors whether the data transmission of the first buffer area is finished; if the data transmission of the first buffer area is finished, the extraction module reads fourth frame data from the buffer of the buffer module and writes the fourth frame data into the first buffer area, otherwise, the monitoring module continues to monitor;

step 21: the method specifically comprises the following steps:

step 211, when the time of the timer 2 is up, the CAN bus transceiver sends a local ID number and a target ID number and sends second buffer data according to a set working mode and a baud rate;

step 212, the extracting module reads a fourth frame instruction from the cache of the cache module, the analyzing module analyzes the instruction to analyze a fourth frame data sending time point, and the time point updating module updates the time point to the timer 1;

step 22: the method specifically comprises the following steps:

step 221, the CAN bus transceiver waits for the timer 3 to finish timing time;

step 222, the monitoring module monitors whether the data transmission of the second buffer area is completed; if the data transmission of the second buffer area is finished, the extraction module reads the fifth frame data from the buffer module in a cache manner and writes the fifth frame data into the second buffer area, otherwise, the monitoring module continues to monitor;

step 23: the method specifically comprises the following steps:

231, the CAN bus transceiver and the like send the local ID number and the target ID number and send the data of the third buffer area when the timer 3 is up according to the set working mode and baud rate;

step 232, the extracting module reads a fifth frame instruction from the cache of the cache module, the analyzing module analyzes the instruction to analyze a fifth frame data sending time point, and the time point updating module updates the time point to the timer 2;

step 24: the method specifically comprises the following steps:

step 241, the monitoring module monitors whether the data transmission of the third buffer area is finished; if the data transmission of the third buffer area is finished, the extraction module reads sixth frame data from the buffer of the buffer module and writes the sixth frame data into the third buffer area, otherwise, the monitoring module continues to monitor;

step 242, the CAN bus transceiver waits for the timer 2 to time;

step 25: and jumping to step 18 until all data is sent.

(III) advantageous effects

By adopting the technical scheme, the invention CAN effectively solve the problems of single function, insufficient performance, poor adaptability and the like of the existing CAN communication module or board card.

Specifically, the method comprises the following steps:

(1) the technical scheme adopts a new hardware scheme and a logic architecture design, improves the real-time performance of data receiving and sending, ensures that data is sent to the CAN bus within 10us after a sending instruction is received, ensures the time synchronization of the whole network where the current CAN node is located, reduces the delay error and improves the accuracy of the control based on the current CAN bus.

(2) The technical scheme adds the function of triggering and controlling data receiving and sending so as to meet the requirement that various measurement and control industries send various instructions through triggering signals to control a single system or the whole system to execute and complete certain actions.

(3) The technical scheme is added with a timing sending function, and the data command can be sent at a certain future time by setting the timing time to control the actuator to complete the action.

(4) According to the technical scheme, the data shielding and receiving functions are added, the frame type, the frame ID, the frame content and the like are set through the upper computer, the parameters are issued to the CAN bus simulation monitoring system, and the CAN bus data CAN be selectively shielded and received.

Compared with the prior art, the CAN bus simulation monitoring scheme designed by the invention improves the real-time performance of data transmission by utilizing the advantages of a hardware scheme and a logic architecture; in addition, the functions of triggering control data to be transmitted and received, setting timing time to finish data transmission, setting data shielding reception and the like are added. The adaptability of the CAN bus in different industrial applications is improved, and various use requirements are met.

Drawings

Fig. 1 is a schematic structural diagram of a system according to the present invention;

FIG. 2 is a circuit diagram of the core hardware provided in the present invention;

FIG. 3 is a top level logical relationship diagram provided by the present invention;

fig. 4 is a schematic diagram of the technical scheme of the invention.

Detailed Description

In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

In order to solve the problem of the prior art, the present invention provides a CAN bus simulation monitoring method, as shown in fig. 4, the CAN bus simulation monitoring method is implemented based on a CAN bus simulation monitoring system, and the CAN bus simulation monitoring system includes: the device comprises a CAN bus transceiver, a reset timer, a reset module, a setting module, a clock calibration module, a timer reset module, a cache module, an extraction module, a data storage module to be sent, an analysis module, a time point updating module and a monitoring module; the data storage module to be sent comprises a first sending buffer area, a second sending buffer area and a third sending buffer area;

step 1: electrifying a CAN bus simulation monitoring system;

and 8: the analysis module analyzes the first frame instruction;

step 12: the analysis module analyzes the second frame instruction;

step 16: the analysis module analyzes the third frame instruction;

step 18: the CAN bus transceiver waits for the timer 1 to finish timing time;

step 20: the method specifically comprises the following steps:

step 201, the CAN bus transceiver waits for the timer 2 to time;

step 21: the method specifically comprises the following steps:

step 22: the method specifically comprises the following steps:

step 221, the CAN bus transceiver waits for the timer 3 to finish timing time;

step 23: the method specifically comprises the following steps:

step 24: the method specifically comprises the following steps:

step 242, the CAN bus transceiver waits for the timer 2 to time;

step 25: and jumping to step 18 until all data is sent.

All the above steps are performed by the master controller, and all the logic of the master controller is described. In practical applications, the buffer module to be transmitted (including the first, second, and third transmission buffers) is mostly inside the CAN bus transceiver. The CAN bus controller is only passively set by the main controller or is written in and read out by the main controller. The main controller suggests adopting FPGA, and the CAN bus controller suggests adopting MCP 2515.

Example 1

In order to solve the problems of poor real-time performance, insufficient triggering control data transceiving function, no timing transmission function, insufficient data shielding receiving function and the like of the current CAN communication module or CAN card, the embodiment provides a set of design scheme for CAN bus data transceiving, and the design scheme is an FPGA logic design as shown in fig. 1:

the innovation points are as follows:

1. the MCP2515 is provided with three data buffer areas, and data to be sent is written into the three buffer areas firstly in the initialization process after power-on; during the transmission process, the states of the three buffers are monitored all the time, and after the data in any buffer is read out, new data is written into the buffer immediately (while the data is written into the buffer, any one of the other two buffers is in the state of transmitting the data). This feature can be implemented depending on the fact that the MCP2515 has three relatively independent buffers and the FPGA can operate in parallel. This is an innovation because it greatly reduces the frame-to-frame transmission interval on the CAN bus, and for the use conditions with strict time accuracy, the method basically reduces the interval between CAN bus data frames to the minimum (basically no interval, the interval is in the nanosecond range).

2. The high-precision timing transmission of CAN bus data is realized by utilizing the high precision of the FPGA and the three relatively independent buffer areas of the MCP2515, and firstly, if the measurement is started by using the first bit of a data frame on the CAN bus, the precision is in ns level. The principle is as follows: the whole system firstly corrects the time with the external system (FPAG clock 200MHz, clock precision 5 ns; the external clock precision is not less than 5ns, the clock precision of the whole system is 5 ns). Next, it is set that the first frame data is transmitted at the time t0+ t1 after the start time t0, the second frame data is transmitted at the time t0+ t2, the third frame data is transmitted at the time t0+ t3, and so on. And the time intervals t1, t2, t3... the like are stored in the FPGA in advance and analyzed, a counter is started at the time t0, when the time t0+ t1, t0+ t2, t0+ t3... the like is counted, the data of the buffer area of the MACP2515 is sent immediately, the delay of the FPGA and the delay (inherent delay of hardware in the province) of the MCP2515 in data sending are taken into consideration, and the time precision can reach the ns level and is lower than 1 us.

The FPGA logic is mainly divided into the following unit modules:

reset unit (Reset), simulation data storage management unit (Mem _ size _ ctl), monitoring data storage management unit (Mem _ monitor _ ctl), CAN bus controller communication unit (MCP2515_ ctl), PCI bus communication management unit (PCI _ ctl), and command parsing unit (Analyze _ cmd).

The design top level logical relationship flow is shown in FIG. 2.

After receiving and analyzing the data of the upper computer, the PCI bus communication unit respectively transmits the data to the transmission simulation data storage management unit and the command analysis unit;

the simulation data storage management unit sends data according to the analyzed upper computer command;

the monitoring data storage management unit monitors and receives data fed back by the lower computer and transmits the data to the received data buffer area;

and the received data buffer area sends the monitoring data to an upper computer.

Specific unit responsibilities:

and a Reset unit (Reset) for resetting all logic units except the Reset unit in the FPGA logic. The reset occurs in one of four cases: 1. powering on the board card; 2. a reset key is pressed; 3. the phase-locked loop is not configured completely, and the locked _ pll is at a low level; 4. and monitoring a reset instruction of the upper computer. The reset unit comprises a power-on reset module, a key reset module, a phase-locked loop unfinished reset module and an instruction reset module which respectively correspond to the four conditions. After the board card is powered on, the power-on reset module starts to time, the output of the module is low before the time is timed, and the indication logic needs to be kept reset all the time. And when the timing time is up, the reset is pulled high, and the reset under the condition is indicated to be finished. The timing time is set to 10ms, so that the circuit is in a stable state after the FPGA passes the period of time. After the FPGA is electrified, the internal phase-locked loop unit starts to be configured, and the configuration time is less than 10ms, so that the module can be reset before the power-on reset is finished. When the board reset button is pressed down, the key reset module starts to work, and the reset is finished after the duration of 10 ms. When a reset instruction of the upper computer is monitored, the instruction reset module starts to work, and the reset is finished after the instruction reset module lasts for 10 ms.

The PCI bus communication management unit identifies that the data issued by the upper computer is the simulation data through the address and then forwards the data to the simulation data storage management unit. The emulation data storage management unit buffers all data in the DDR2 waiting for a data read command from the CAN bus controller communication unit. And after monitoring the reading instruction, the simulation data storage management unit reads a frame of data from the memory, sends the frame of data to the CAN bus controller communication unit, configures the data to the CAN controller sending buffer, and waits for the sending of the data. And the simulation data storage management unit sequentially stores the simulation data into the DDR according to the protocol format except the frame header. When the simulation data is stored in the DDR, the frame counting is monitored in real time, and the current upper computer can know the total number of frames of data sent to the board card. After the upper computer finishes sending all the simulation data, the upper computer configures a 'sending enable' effective signal to the board card to indicate that all the simulation data are sent completely, and the upper computer prepares to send the simulation data at any time (when a trigger signal is monitored, a sending timing is started, and when sending timestamp information of the frame is timed, the simulation data are sent immediately). And after the first frame of simulation data is stored, sending information to the CAN bus controller communication unit to inform that the first frame of data is stored. After the CAN bus controller communication unit completes the basic configuration (baud rate, a shielding register, a filtering register, interrupt enable and the like) of the CAN controller, a data reading instruction is sent to the simulation data storage management unit, the first frame data is read, and the first frame data is loaded to a sending buffer area of the CAN controller. If the emulation data is greater than 3 frames, the first three frames are loaded into the transmit buffer. When reading data, the simulation data storage management unit reads the data in sequence according to a protocol format, firstly reads the data length, and then reads the channel number, the frame count, the timestamp, the frame structure, the frame ID, the frame type and the frame data in sequence. And determining the end address of the DDR reading according to the data length (the number of effective data bytes).

And the monitoring data storage management unit (Mem _ monitor _ ctl) generates corresponding interrupt (corresponding to different data receiving cache regions) after the data receiving cache region of the CAN controller receives the data, and informs the monitoring data storage management unit. And the monitoring data storage management unit reads the frame ID, the effective data length, the frame structure, the frame type and the frame data in sequence and buffers the frame ID, the effective data length, the frame structure, the frame type and the frame data into the DDR. The data storage format is unified, and the storage management is convenient. The valid data written each time when data is stored in the DDR is 8 bytes, and if the valid data length is less than 8 bytes, the high byte is valid and the low byte is invalid. In order to match the data length of the PCI bus, the written data is in units of DWORD (32 bit). And when the PCI bus is idle, the PCI bus communication management unit monitors that the technical value is greater than 0, reads data from the monitoring data storage management unit, updates frame counting (decrementing) and sends the data PCI bus to an upper computer.

The CAN bus controller communication unit (MCP2515_ ctl) is responsible for configuring the CAN controller, including setting baud rate, checking and accepting a mask register, checking and accepting a filter register, and the like. By setting the shielding register and the filtering register, whether to receive the current data CAN be determined according to the frame type and the frame ID of the CAN data on the CAN bus. While loading data into the transmit buffer of the CAN controller and reading data from the receive data buffer. When the board card is in a bus simulation state, if the sending buffer area is monitored to be empty, data are immediately loaded to the sending buffer area, and when the sending time is up, the data are immediately sent to the CAN bus. When the board card is in a bus monitoring state, when the monitoring data receiving buffer area has data, the data is read out and stored in the DDR, and when the PCI bus is idle, the data is uploaded to the upper computer.

And the PCI bus communication management unit is responsible for data interaction between the FPGA and the PCI9054 bridge chip. The integrated circuit board communicates with the upper computer through a PCI bus, and the specific connection mode is as follows: the FPGA is connected with a Local end of the PCI9054, and the PCI end of the PCI9054 is connected with the upper computer through a PCI slot. In FPGA logic, different mapping spaces are allocated to all commands, parameters and data, the addresses of the spaces are unique, and parameter configuration, command issuing and data receiving and sending of the logic are completed through the access to the addresses. The PCI bus communication management unit receives the configuration information in the following sequence:

(1) resetting the board card (completing the resetting of the board card);

(2) selecting (gating) the board card;

(3) trigger source selection (backplane hard trigger or soft trigger of logic signal);

(4) trigger mode selection (rising edge, falling edge, high level, low level);

(5) selecting the data flow direction of the trigger signal (only aiming at the triggering of the backboard hardware, selecting a backboard interface to receive an external trigger signal or generating a trigger signal to send to other boards);

(6) selecting a hardware trigger channel (only selecting backboard hardware trigger aiming at a trigger source, wherein the backboard trigger interface has 10 trigger pins in total, and one or more of the pins are allocated and selected);

(7) the backboard triggers and enables (the trigger signal received after enabling is effective);

(8) hardware trigger signal filtering enabling (only selecting back panel hardware trigger aiming at a trigger source, and filtering out an interference signal on a trigger pin);

(9) setting the filtering time of a trigger signal (only selecting backboard hardware for triggering aiming at a trigger source, and setting the filtering time according to the external electromagnetic environment);

(10) CAN bus channel selection (each path of CAN bus channel is gated, and bus simulation and data monitoring CAN be performed after the gating);

(11) matched resistance enable (select whether to configure the terminal matched resistance);

(12) setting the baud rate (the baud rate of each CAN bus is selected according to a preset value and cannot be set randomly temporarily);

(13) send enable (send command is valid after send enable is valid);

(14) transmission mode selection (either single transmission or round robin transmission is selected).

And the command analysis unit receives and analyzes the command sent by the upper computer. And selecting a trigger source, a trigger mode, a CAN bus communication rate, a CAN communication channel, terminal resistance matching and acquiring trigger time according to the analyzed instruction. The configuration information sent by the upper computer is firstly sent to the PCI bus communication management unit and then forwarded to the command analysis unit. And after the command analysis unit completes parameter analysis, the parameters are sent to other modules, and the other modules complete the configuration of the whole board card according to the parameters.

The command analysis unit (Analyze _ cmd) analyzes the functions of CAN bus baud rate, CAN bus communication channel selection, terminal matching resistance selection, trigger type selection, trigger time acquisition, sending timing and the like. When the board card is set to the data simulation mode, the FPGA acquires a simulation data packet from the DDR 2. The simulation data packet includes information such as simulation data and attribute parameters thereof, including transmission time information. The transmission time information is a relative time value, and if the transmission event information is T and the trigger signal generation time is T0, the analog data indicating the current packet is to be transmitted to the CAN bus at time T0+ T. The CAN bus of any channel is subjected to CAN bus data receiving and sending by a CAN controller, and the CAN controller has three sending buffer areas, so that before a trigger signal is effective, three packets of analog data are read firstly, the data are loaded to a CAN bus transceiver, sending time information is analyzed, and the time information is sent to a sending timing module. When the trigger signal is effective, the sending timing module starts to operate, and when the timing time reaches the analyzed sending time, a sending instruction is generated to inform the CAN controller of immediately sending the data of the buffer area. And meanwhile, the timing module is cleared and re-times until the time of the sending timestamp of the next frame data is counted, and the next frame data is sent. When the sending time of the current frame to be sent is timed, if other frames except the current frame are sent, the CAN bus controller communication unit continues to read the loading data and updates the timestamp information to be sent of the next frame to the command analysis unit, so that the sending time of the next frame CAN be immediately timed when the current frame is timed. The CAN buses for sending the adjacent frames have a sequence, so that a plurality of frame data cannot be sent in parallel at the same time. And a certain time Ttx (no higher than 30us when the baud rate is 1 Mhz) is required for the CAN controller to issue a transmission instruction (or by pulling down the transmission pin) until all data is completely transmitted from the transmission buffer to the CAN bus, so when the timestamp information of a certain frame is less than Ttx (or an adjacent frame is expected to be transmitted simultaneously), the command parsing unit sets the relative time of the certain frame to Ttx.

The flow of the working process state of the CAN controller is shown in figure 3:

a state machine 1:

(1) an initial state;

(2) resetting;

(3) shooting a working mode;

(4) setting a receiving cache register;

(5) setting a sending cache register;

(6) setting a receiving control register;

(7) setting a transmission control register;

(8) setting an interrupt;

(9) setting a baud rate;

(10) and (3) reading and writing judgment:

and if the CAN bus data is received and the loading of the last frame of data from the CAN controller to the FPGA is finished, receiving new data.

Data is ready (i.e., data is loaded into the buffer to be sent), the send register is empty (i.e., there is no data that is not sent at present), and there is no data currently being received (i.e., the data in the receive register is read by the currently unoccupied SPI bus)

And (3) state machine 2:

(1) an initial state;

(2) analyzing the time instruction;

(3) judging a trigger condition;

(4) data transmission is performed.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. A CAN bus simulation monitoring method is characterized in that the CAN bus simulation monitoring method is implemented based on a CAN bus simulation monitoring system, and the CAN bus simulation monitoring system comprises: the device comprises a CAN bus transceiver, a reset timer, a reset module, a setting module, a clock calibration module, a timer reset module, a cache module, an extraction module, a data storage module to be sent, an analysis module, a time point updating module and a monitoring module; the data storage module to be sent comprises a first sending buffer area, a second sending buffer area and a third sending buffer area;

step 1: electrifying a CAN bus simulation monitoring system;

and 8: the analysis module analyzes the first frame instruction;

step 12: the analysis module analyzes the second frame instruction;

step 16: the analysis module analyzes the third frame instruction;

step 18: the CAN bus transceiver waits for the timer 1 to finish timing time;

step 20: the method specifically comprises the following steps:

step 201, the CAN bus transceiver waits for the timer 2 to time;

step 202, a monitoring module monitors whether data transmission of a first transmission buffer area is finished; if the data transmission of the first sending buffer area is finished, the extracting module reads fourth frame data from the buffer of the buffer module and writes the fourth frame data into the first sending buffer area, otherwise, the monitoring module continues to monitor;

step 21: the method specifically comprises the following steps:

step 211, when the time of the timer 2 is up, the CAN bus transceiver sends a local ID number and a target ID number and sends second sending buffer data according to the set working mode and baud rate;

step 22: the method specifically comprises the following steps:

step 221, the CAN bus transceiver waits for the timer 3 to finish timing time;

step 222, the monitoring module monitors whether the data transmission of the second transmission buffer area is completed; if the data transmission of the second sending buffer area is finished, the extraction module reads the fifth frame data from the buffer of the buffer module and writes the fifth frame data into the second sending buffer area, otherwise, the monitoring module continues to monitor;

step 23: the method specifically comprises the following steps:

231, the CAN bus transceiver and the like send the local ID number and the target ID number and send the data of the third sending buffer area when the timer 3 is up according to the set working mode and baud rate;

step 24: the method specifically comprises the following steps:

step 241, the monitoring module monitors whether the data transmission of the third transmission buffer area is finished; if the data transmission of the third sending buffer zone is finished, the extracting module reads sixth frame data from the buffer of the buffer module and writes the sixth frame data into the third sending buffer zone, otherwise, the monitoring module continues to monitor;

step 242, the CAN bus transceiver waits for the timer 2 to time;

step 25: and jumping to step 18 until all data is sent.