CN109543811B - Counting circuit, counting method and chip - Google Patents
Counting circuit, counting method and chip Download PDFInfo
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- CN109543811B CN109543811B CN201811291858.2A CN201811291858A CN109543811B CN 109543811 B CN109543811 B CN 109543811B CN 201811291858 A CN201811291858 A CN 201811291858A CN 109543811 B CN109543811 B CN 109543811B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M1/00—Design features of general application
- G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a counting circuit, a counting method and a chip, wherein the counting circuit comprises: the multi-path latch pulse input unit, the multi-path latch control logic unit, the latch unit and the counter; the output end of the multi-path latch pulse input unit is connected with the input end of the multi-path latch control logic unit, the output end of the multi-path latch control logic unit is connected with the counter, and the counter is connected with the latch unit; after the multi-path latch pulse input unit receives multi-path pulse signals, the multi-path latch control logic unit carries out logic judgment on the multi-path pulse signals according to the setting logic circuit and gathers the multi-path pulse signals, the multi-path latch control logic unit sends trigger signals to the counters according to the gathered multi-path pulse signals, and the counters trigger the latch unit to latch the current count value of the counters after receiving the trigger signals.
Description
Technical Field
The invention relates to the technical field of electronic circuit structures, in particular to a counting circuit, a counting method and a chip.
Background
The counting circuit is a function commonly used in a computer or a signal processing system, and is used for periodically counting by utilizing a system working clock to finish a hardware or software timing function and simultaneously has a counting and latching function, but does not support a multi-path external triggering function, and cannot meet a system with a plurality of external triggering and latching requirements, for example, one path of pulse signals with accurate counting are used for adjusting the other path or paths of pulses with low accuracy, or one path of pulse signals with accurate counting are used for synchronizing the other path or paths of pulse signals, so that the traditional implementation needs to be provided with a plurality of counters to solve synchronous error measurement or multi-path pulse width synchronous adjustment, and meanwhile, the system implementation cost is high.
Disclosure of Invention
The embodiment of the invention aims to provide a counting circuit, a counting method and a chip, which are used for solving the technical problem that a plurality of counters are required to be arranged in the existing system to solve synchronous error measurement or multi-path pulse width synchronous adjustment.
To achieve the above object, an embodiment of the present invention provides a counting circuit, including: the multi-path latch pulse input unit, the multi-path latch control logic unit, the latch unit and the counter; the output end of the multi-path latch pulse input unit is connected with the input end of the multi-path latch control logic unit, the output end of the multi-path latch control logic unit is connected with the counter, and the counter is connected with the latch unit; after the multi-path latch pulse input unit receives multi-path pulse signals, the multi-path latch control logic unit carries out logic judgment on the multi-path pulse signals according to a setting logic circuit and collects the multi-path pulse signals, the multi-path latch control logic unit sends trigger signals to the counter according to the collected multi-path pulse signals, and the counter triggers the latch unit to latch the current count value of the counter after receiving the trigger signals.
Preferably, the setting logic circuit is designed according to input states of the multi-path pulse signal, the input states including: the combination logic of the multipath pulse signals accords with the condition for triggering the latch unit to latch the current count value of the counter, wherein any path of pulse signals or at least one path of pulse signals in the multipath pulse signals accord with the condition for triggering the latch unit to latch the current count value of the counter.
Preferably, the count value register is connected with the latch unit, and the count value register is used for storing the mapping relation between the count value and each path of pulse signal identifier corresponding to the count value.
Preferably, the counter is a 32-bit or more cycle counter.
Preferably, a first host data exchange interface is arranged on the counter, and the first host data exchange interface is an interface for the counter to communicate with the CPU.
Preferably, the counter is connected with the counting control logic unit, and the counting control logic unit is used for controlling the counter to set an initial count value, start counting and end counting.
Preferably, the system further comprises a pulse signal input state register, wherein the pulse signal input state register can be accessed by the CPU through the second host data exchange interface, and the pulse signal input state register acquires and stores the input states of the multiple paths of pulse signals and the identifiers corresponding to each path of pulse signals.
Preferably, the method further comprises: the digital phase-locked loop circuit is connected with the clock unit and is used for adjusting the frequency of signals input by the clock unit into the multi-path latch pulse input unit, the multi-path latch control logic unit, the latch unit, the counter, the count value register, the CPU, the count control logic unit and the pulse signal input state register.
In another aspect, an embodiment of the present invention provides a counting method, including:
receiving a plurality of pulse signals; logic judgment is carried out on the multipath pulse signals according to a set logic circuit, and the multipath pulse signals are collected; and sending a trigger signal to a counter according to the collected multipath pulse signals, and triggering a latch unit to latch the current count value of the counter after the counter receives the trigger signal.
In another aspect, an embodiment of the present invention provides a chip including a counting circuit as described above.
The embodiment of the invention has the following advantages:
the technical scheme disclosed by the embodiment of the invention can reduce the number of counters in the counting circuit for adjusting the other path or paths of pulses with low accuracy by using one path of pulse signals with accurate counting or synchronizing the other path or paths of pulse signals by using one path of pulse signals with accurate counting, and a plurality of counters are needed to realize the functions in the prior art.
Drawings
Fig. 1 is a schematic diagram of a counting circuit according to an embodiment of the invention.
Fig. 2 is a schematic flow chart of a counting method according to an embodiment of the invention.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1, an embodiment of the present invention provides a schematic diagram of a counting circuit structure.
The counting circuit disclosed by the embodiment of the invention comprises: the multi-path latch pulse input unit 01, the multi-path latch control logic unit 02, the latch unit 06 and the counter 04, wherein the output end of the multi-path latch pulse input unit 01 is connected with the input end of the multi-path latch control logic unit 02, the output end of the multi-path latch control logic unit 02 is connected with the counter 04, and the counter 04 is connected with the latch unit 06.
The system further comprises a count value register 07, wherein the count value register 07 is connected with the latch unit 06, the count value register 07 is used for storing the mapping relation between the count value and each path of pulse signal identification in the multipath pulse signals corresponding to the count value, and each path of pulse signal identification can be customized according to the system and then distributed to each path of corresponding pulse signal.
The digital phase-locked loop circuit 09 is connected with the clock unit 08, and the digital phase-locked loop circuit 09 is used for adjusting the frequency of signals input by the clock unit 08 into the multi-path latch pulse input unit 01, the multi-path latch control logic unit 02, the latch unit 06, the counter 04, the count value register 07, the CPU10, the count control logic unit 05 and the pulse signal input state register 03, and the clock unit 08 is the working basis of all functional units related to the invention.
The counter 04 is a cycle counter of 32 bits or more, and the counter 04 can adjust the length of the counter 04 as required.
Further comprises: the counter 04 is connected with the counting control logic unit 05, and the counting control logic unit 05 is used for controlling the counter 04 to set an initial count value, start counting and end counting.
A Central Processing Unit (CPU) 10 is arranged in the counting circuit, a first host data exchange interface is arranged on the counter 04, and the first host data exchange interface is an interface for the counter 04 to communicate with the CPU 10.
The CPU10 can obtain the corresponding identifier of each pulse signal in the multiple paths of pulse signals stored on the pulse signal input state register 03 through the second host data exchange interface, and the CPU10 can obtain the mapping relation between the count value and the corresponding identifier of each path of pulse signal through accessing the count value register 07.
The embodiment of the invention sets the pulse signal input state register 03, so that the flexibility of realizing the system function to be realized by using the embodiment of the invention can be increased, when circuit design is started, if multiple paths of pulse signals exist, if a logic judgment circuit is simply carried out on hardware design, the complexity of the hardware design can be reduced by increasing the pulse signal input state register 03, the task of sharing a part of the pulse signal input state register 03 can be carried out, the CPU10 accesses the data on the pulse signal input state register 03 through the second host data exchange interface, and the logic judgment and arbitration of the multiple paths of pulse signals can be completed by matching software and hardware, so that the flexibility of realizing the system function to be realized by using the embodiment of the invention is increased.
In the embodiment disclosed by the invention, a multi-path latch pulse input unit 01 is used for receiving the input of multi-path pulse signals; the multi-path latch control logic unit 02 is used for coordinating the multi-path latch pulse input unit 01 to complete the arbitration judgment of the input multi-path pulse signals and prevent the loss of the multi-path pulse signals; the latch unit 06 is used for latching the current count value of the counter 04 triggered by the multipath pulse signals;
the counter 04 is used for counting the system clock unit 08, and in the embodiment disclosed by the invention, the requirement of all systems can be met by only setting one counter 04, so that the complexity of circuit design is simplified, and the technical problem of synchronous error measurement or multi-path pulse width synchronous adjustment which is needed to be solved by setting a plurality of counters is solved.
In the embodiment of the invention, after the multi-path latch pulse input unit 01 receives the multi-path pulse signals, the multi-path latch control logic unit 02 carries out logic judgment on the multi-path pulse signals according to the set logic circuit and gathers the multi-path pulse signals, the multi-path latch control logic unit 02 sends a trigger signal to the counter 04 according to the gathered multi-path pulse signals, and the counter 04 triggers the latch unit 06 to latch the current count value of the counter 04 after receiving the trigger signal.
The setting logic circuit is designed according to the input states of the multipath pulse signals, wherein the input states comprise:
the combination logic of the multiple pulse signals accords with the condition for triggering the latch unit to latch the current count value of the counter 04, wherein any pulse signal or at least one pulse signal in the multiple pulse signals accords with the condition for triggering the latch unit 06 to latch the current count value of the counter 04.
The setting logic circuit performs combination logic judgment according to a preset function and determines the type of the count value latch.
The invention discloses a counting circuit mainly comprising: a clock unit 08, a multi-path latch pulse input unit 01, a multi-path latch control logic unit 02, a counter 04 with a length of more than 32 bits, a count control logic unit 05 and a host data exchange interface; the clock unit 08 receives a crystal oscillator or a system clock input as a working basis of the counter 04, and if necessary, can increase the frequency of the clock input by a digital phase-locked loop circuit 09 (DPLL) to improve the counting accuracy. The multiple latch pulse input unit 01 is a circuit capable of receiving a plurality of external multiple pulse signals for triggering input, and cooperates with the multiple latch control logic unit 02 to complete arbitration and judgment of input signals and prevent loss of multiple pulse signals, and stores the latched count value in the count value register 07, and the central processing unit CPU10 can obtain the values through the data channel of the counter 04, and access and utilize the data according to design requirements. The counter 04 with the length of more than 32 bits and the counting control logic are universal cycle counters, the length of the counter can be adjusted according to the needs, the design scheme of the counter is adjusted accordingly, and the current count value is latched according to the trigger signals provided by the multi-path latch pulse input unit 01. The host data exchange interface is an interface in communication with the CPU10, using a suitable access bus according to the integrated form of the present counting circuit in the overall system, but it must be ensured that the data acquisition time is within acceptable limits, in a System On Chip (SOC) it may be a data access bus, in a separate system it may be a parallel or serial bus.
The embodiment of the invention discloses a counting circuit, wherein a plurality of paths of latch control logic units 02 are added, the plurality of paths of latch control logic units 02 can carry out logic judgment and arbitration on a plurality of paths of pulse signals, a counter 04 receives pulse signal triggering conforming to conditions and triggers a latch unit 06 to latch the current count value of the counter 04.
In another aspect, as shown in fig. 2, an embodiment of the present invention discloses a counting method:
it should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
The invention discloses a counting method which comprises the following steps:
step S1, receiving a plurality of pulse signals;
it should be noted that, in the embodiment of the disclosure, a plurality of external pulse signal inputs may be received through the multi-path latch pulse input unit 01.
Step S2, carrying out logic judgment on the multipath pulse signals according to a set logic circuit and collecting the multipath pulse signals;
the multi-path latch control logic unit 02 performs logic judgment on the multi-path pulse signals according to the setting logic circuit, and gathers the multi-path pulse signals, and specifically performs combinational logic judgment through a preset function, and determines a count value for latching.
And step S3, sending a trigger signal to a counter according to the collected multipath pulse signals, and triggering a latch unit to latch the current count value of the counter after the counter receives the trigger signal.
In another aspect, the embodiment of the invention also discloses a chip, which comprises the counting circuit;
the structure of the specific counting circuit is the same as that of the above embodiment, and will not be described in detail here.
The technical scheme disclosed by the embodiment of the invention can reduce the number of counters in the counting circuit for adjusting the other path or paths of pulses with low accuracy by using one path of pulse signals with accurate counting or synchronizing the other path or paths of pulse signals by using one path of pulse signals with accurate counting, and a plurality of counters are needed to realize the functions in the prior art.
While the invention has been described in detail in terms of its general description and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (8)
1. A counting circuit, comprising: the multi-path latch pulse input unit, the multi-path latch control logic unit, the latch unit and the counter;
the output end of the multi-path latch pulse input unit is connected with the input end of the multi-path latch control logic unit, the output end of the multi-path latch control logic unit is connected with the counter, and the counter is connected with the latch unit;
after the multi-path latch pulse input unit receives multi-path pulse signals, the multi-path latch control logic unit carries out logic judgment on the multi-path pulse signals according to a setting logic circuit and gathers the multi-path pulse signals, the multi-path latch control logic unit sends trigger signals to the counter according to the gathered multi-path pulse signals, the counter triggers the latch unit to latch the current count value of the counter after receiving the trigger signals, and the counter is used for counting the system clock unit;
the setting logic circuit is designed according to the input states of the multipath pulse signals, wherein the input states comprise:
the combination logic of the multipath pulse signals accords with the condition for triggering the latch unit to latch the current count value of the counter, wherein any path of pulse signals or at least one path of pulse signals in the multipath pulse signals accord with the condition for triggering the latch unit to latch the current count value of the counter;
the digital phase-locked loop circuit is connected with the clock unit and is used for adjusting the frequency of signals input by the clock unit into the multi-path latch pulse input unit, the multi-path latch control logic unit, the latch unit, the counter, the count value register, the CPU, the count control logic unit and the pulse signal input state register.
2. A counting circuit according to claim 1, further comprising: the count value register is connected with the latch unit and is used for storing the count value and the mapping relation of the identifiers of each path of pulse signals corresponding to the count value.
3. A counting circuit according to claim 1, wherein the counter is a 32-bit or more cycle counter.
4. A counter circuit according to claim 1, wherein the counter is provided with a first host data exchange interface, the first host data exchange interface being an interface through which the counter communicates with the CPU.
5. A counting circuit according to claim 1, further comprising: the counting control logic unit is connected with the counter and used for controlling the counter to set an initial count value, start counting and end counting.
6. The counting circuit of claim 1, further comprising a pulse signal input status register, one end of the pulse signal input status register being connected to the CPU to be accessed by the CPU, the other end of the pulse signal input status register being connected to the multi-path latch pulse input unit to acquire and store an input status of the multi-path pulse signal and an identification of each path pulse signal.
7. A counting method, characterized in that it is applied to the counting circuit according to any one of claims 1 to 6, the method comprising:
receiving a plurality of pulse signals;
logic judgment is carried out on the multipath pulse signals according to a set logic circuit, and the multipath pulse signals are collected;
and sending a trigger signal to a counter according to the collected multipath pulse signals, and triggering a latch unit to latch the current count value of the counter after the counter receives the trigger signal.
8. A chip comprising a counting circuit according to any one of claims 1 to 6.
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| CN113377045A (en) * | 2021-06-08 | 2021-09-10 | 广东三姆森科技股份有限公司 | Multi-path position comparison output device based on FPGA |
| CN114118337B (en) * | 2021-11-19 | 2023-08-18 | 深圳诺博医疗科技有限公司 | Batch medicine bottle classifying and counting method and device |
| CN114951046A (en) * | 2022-05-10 | 2022-08-30 | 苏州天准科技股份有限公司 | Latch counting trigger equipment and system |
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