CN110192284B - 半导体装置和电力变换装置 - Google Patents

半导体装置和电力变换装置 Download PDF

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CN110192284B
CN110192284B CN201780083838.3A CN201780083838A CN110192284B CN 110192284 B CN110192284 B CN 110192284B CN 201780083838 A CN201780083838 A CN 201780083838A CN 110192284 B CN110192284 B CN 110192284B
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gate
semiconductor device
gate wiring
emitter electrode
power
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CN110192284A (zh
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古川智康
白石正树
守田俊章
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Hitachi Power Semiconductor Device Ltd
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Hitachi Power Semiconductor Device Ltd
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Abstract

提供一种半导体装置，其在将作为导电部件的金属板烧结接合在IGBT那样的具有栅极构造的半导体芯片上时，即使在烧结接合过程中进行加压，也难以在半导体芯片的栅极配线部产生过剩的应力，从而减少了特性不良。本发明的半导体装置的特征在于，具备以IGBT为代表的具有栅极构造的半导体芯片(105)，并具有在半导体芯片表面形成的第一栅极配线(206)和第二栅极配线(202)，并且具有以覆盖第一栅极配线的方式配置的发射极电极(205)和在发射极电极上方配置的烧结层，在半导体芯片表面，在包含发射极电极连接触点(506)以及栅极配线区域(503、504)的整个范围内连续存在至少包含发射极电极和烧结层而成的多层构造。

Description

半导体装置和电力变换装置
技术领域
本发明涉及一种在电子部件中的电气接合部(例如半导体元件与电路部件的接合部)的接合层中具有特征的半导体装置，特别是涉及一种具有烧结接合层的半导体装置以及使用该半导体装置的电力变换装置。
背景技术
半导体装置在***LSI(大规模集成电路)、电力变换装置、混合动力汽车等的控制装置等广泛的领域中被使用。作为该半导体装置，例如在电子部件的电极端子与电路基板上的电路图案的电极端子的电气接合处使用包含铅的“焊锡”、“焊锡合金”曾经是主流。
但是，从保护地球环境的观点出发，严格限制铅的使用，正在开发在有限的范围内使用铅，或使用不含铅的材料进行半导体装置的电极等的接合。特别是关于“高温焊锡”，还没有找到作为其替代的有效材料。在半导体的安装中，使用“分层焊锡”是必不可少的，因此希望出现代替该“高温焊锡”的材料。
从这样的背景出发，以往提出了以下的接合技术：作为代替“高温焊锡”的材料，使用金属颗粒与有机化合物的复合材料作为接合材料来对电极进行接合。
例如，作为能够得到对于镍(以下记载为“镍”)或铜(以下记载为“Cu”)的电极来说优良的接合强度的接合技术，在专利文献1中记载了以下的方法：使用包含由氧化铜(CuO)颗粒与有机物构成的还原剂的接合材料，在还原气氛下进行接合。该方法是在加热还原时生成100nm以下的铜颗粒，将铜颗粒彼此烧结来进行接合的方法。在该文献中，还记载了作为将半导体芯片与金属板进行接合的接合材料，使用含有烧结性的银微颗粒的材料。
另外，在专利文献2中，作为提高配线连接的可靠性的技术，记载了以下的从应力缓冲的观点出发的解决方法，即使用具有配线部件与半导体芯片的中间的热膨胀系数的金属板来去除热膨胀系数差大的连接部。
现有技术文献
专利文献
专利文献1：日本特开2008-244242号公报
专利文献2：日本特开2012-28674号公报
发明内容
发明要解决的课题
专利文献1记载的使用了氧化铜(CuO)颗粒的接合技术与现有的纳米颗粒接合相比，能够改善针对镍、Cu的接合性，能够期待作为镍电极或铜电极用接合材料。例如，能够经由铜烧结层构成的接合层将连接端子与电力变换装置的逆变器中使用的IGBT(绝缘栅双极晶体管)、续流二极管等功率半导体芯片的镍电极电连接。
将硅(以下记载为“Si”)、碳化硅(以下记载为“SiC”)构成的半导体芯片的主电极通过由铜或铝等构成的电线、条带等配线材料与其他芯片、电极连接。存在以下的问题，当半导体芯片的动作温度变高时，由于半导体芯片与配线材料存在热膨胀系数的差，在重复进行开关动作(通电的接通和切断的切换动作)的过程中，在接合部由于热疲劳而产生不良。
因此，作为提高配线连接的可靠性的技术，如专利文献2所记载的那样，提出了以下的从应力缓冲的观点出发的解决方法，即使用配线部件与半导体芯片的中间的热膨胀系数的金属板来去除热膨胀系数差大的连接部。
但是，存在以下的问题：当在IGBT那样的具有栅极构造的半导体芯片上烧结接合金属板(导电部件)时，由于烧结接合过程中的加压，在半导体芯片的栅极配线部产生过剩的应力从而产生裂纹。关于产生的裂纹，存在以下的问题：例如有时产生栅极与作为主电极的发射极之间的短路不良、发射极与集电极之间的主耐压下降不良等。
鉴于这样的情况，本发明的课题在于，提供一种能够降低由于烧结接合过程中的加压而导致的特性不良的半导体装置、该半导体装置的制造方法以及使用了该半导体装置的电力变换装置。
解决课题的手段
为了解决上述课题，本发明的半导体装置的特征在于，具备半导体芯片、在上述半导体芯片的表面形成的第一栅极配线和第二栅极配线、以覆盖上述第一栅极配线的方式配置的发射极电极、配置在上述发射极电极上方的烧结层，在上述半导体芯片的表面，在包含发射极电极连接触点和栅极配线区域的整个范围内，连续地存在至少包含上述发射极电极和上述烧结层而构成的多层构造。
另外，本发明的电力变换装置从外部输入直流电力，将输入的上述直流电力变换为交流电力并输出，该电力变换装置的特征在于：具备用于输入上述直流电力的一对直流端子、用于输出上述交流电力且与上述交流电力的交流相数相同数量的交流端子，该电力变换装置还具有以下的结构：对于上述相数的上述交流端子中的各个交流端子，在上述一对直流端子中的一个直流端子和另一个直流端子之间连接将两个并联电路串联连接的结构的串联电路，并且将构成上述串联电路的两个上述并联电路的相互连接点与该串联电路所对应的相的上述交流端子连接，上述并联电路是将开关元件和极性与该开关元件相反的二极管相互并联连接而成的并联电路，上述并联电路由本发明的半导体装置构成。
发明效果
根据本发明，能够提供一种使特性不良降低的半导体装置，其能够抑制由于在IGBT那样的具有栅极构造的半导体芯片上烧结接合金属板(导电部件)时的加压而对栅极配线部施加过剩应力的情况，并且能够通过发射极电极保护栅极电极，因此即使在烧结接合过程中进行加压也难以产生裂纹。
附图说明
图1是本发明的实施例1的半导体装置的俯视图。
图2是表示本发明的实施例1的半导体装置的IGBT芯片的部分的安装形式的俯视图。
图3是本发明的实施例1的半导体装置的IGBT芯片的部分的俯视图。
图4是本发明的实施例1的半导体装置的图1的A-A`的截面图。
图5是本发明的实施例1的半导体装置的IGBT芯片的部分的主要部分布局图。
图6是本发明的实施例1的半导体装置的图5的B区域的鸟瞰图。
图7是本发明的实施例1的半导体装置的图5的C区域的鸟瞰图。
图8是现有技术的半导体装置的IGBT芯片的部分的俯视图。
图9是现有技术的半导体装置的IGBT芯片的部分的截面图。
图10是现有技术的半导体装置的IGBT芯片的部分的主要部分布局图。
图11是现有技术的半导体装置的图10的D区域的鸟瞰图。
图12是本发明的实施例2的半导体装置的IGBT芯片的部分的主要部分布局图。
图13是本发明的实施例2的图12的E区域的鸟瞰图。
图14是本发明的实施例3的半导体装置的IGBT芯片的部分的主要部分布局图。
图15是本发明的实施例3的图14的F区域的鸟瞰图。
图16是本发明的实施例4的电力变换装置的电路框图。
具体实施方式
本发明的半导体装置的特征在于：具备以IGBT为代表的具有栅极构造的半导体芯片(105)，该半导体装置具有在半导体芯片表面上形成的第一栅极配线(206)和第二栅极配线(202)，并具备以覆盖第一栅极配线的方式配置的发射极电极(205)以及配置在发射极电极上方的烧结层，在半导体芯片表面，在包含发射极电极连接触点(506)和栅极配线区域(503、504)的整个范围内连续地存在至少包含发射极电极和烧结层而构成的多层构造(层数为2以上的层构造)。
在本发明的上述结构中，还可以构成为降低有源部内栅极配线(504)与发射极电极(205)之间的阶梯差。由此，能够降低通过烧结层将导电部件(107)与IGBT芯片相互连接时的压力的偏向。
另外，在本发明的上述结构中，还可以构成为通过发射极电极和镀镍来机械地保护栅极配线。由此，能够降低裂纹的产生。
以下，参照附图详细说明本发明的实施方式。
在各图中，参照编号相同的部分表示同一构成要件或具有类似的功能的构成要件。另外，p-、p、p+表示半导体层的导电类型是p型，并且相对杂质浓度按照该顺序变高。并且，n-、n、n+表示半导体层的导电类型是n型，并且相对杂质浓度按照该顺序变高。
(实施例1)
图1是本发明的第一实施方式的实施例1的半导体装置的俯视图。另外，图2是表示图1的半导体装置中的IGBT芯片的部分的安装形式的俯视图。另外，图3是图1的半导体装置中的IGBT芯片的部分的俯视图。另外，图4是表示图1的A-A`线的半导体装置的截面结构的截面图。
本实施例的半导体装置是应用于IGBT模块时的例子。此外，在本例子中，说明将IGBT芯片与续流二极管芯片被安装在共同的陶瓷衬底上的集电极配线上的模块作为半导体装置的结构，但本发明并不限于此。例如，在将MOSFET(金属氧化物半导体场效应晶体管)芯片与续流二极管芯片一起安装的结构、或者安装MOSFET芯片但不安装续流二极管芯片，将MOSFET芯片的体二极管作为回流二极管使用的所谓的无二极管的结构中，也同样能够应用本发明的技术思想，因此这些结构也包含在本发明的技术范围内。
在陶瓷衬底101上，陶瓷衬底上的集电极配线103与IGBT105以及二极管芯片106通过之后在图4的说明中说明的下侧的烧结接合层(烧结层)401相互接合。在IGBT105和二极管芯片106的上方，通过上侧的烧结接合层(烧结层)401分别连接了独立的导电部件107，IGBT105的发射极与二极管芯片的阳极通过接合线(bonding wire)相互连接，并且分别通过独立的接合线与陶瓷衬底上的发射极配线104以及陶瓷衬底上的发射极感测配线109连接。如上述那样，烧结层401构成为包含下侧层和上侧层，另外该两者相互分离。
另外，IGBT芯片的栅极电极焊盘204通过接合线与陶瓷衬底上的栅极配线连接。
图2是表示本发明的半导体装置中的IGBT芯片的部分的安装形式的俯视图，IGBT芯片105由末端区域201及其内侧的元件有源区域构成，末端区域201将用于保持IGBT的耐压的铝场板(field plate)403以及PWEL405环状地配置在芯片外周，IGBT芯片105形成了发射极电极205和栅极电极焊盘204。在发射极电极上通过烧结接合层301连接了导电部件107，在导电部件107的外周部配置有第二栅极配线202。
图3是连接导电部件前的IGBT芯片的俯视图，在发射极电极下面形成有第一栅极配线，在外周部与第二栅极配线202连接，将通过栅极电极焊盘输入的信号分配到IGBT芯片内。
图4是通过图1、图2中的A-A`线将本发明的半导体装置切断时的半导体装置的截面图，该图也成为表示栅极配线部的截面的图。IGBT芯片在n-Si衬底408的背面形成了N缓冲层408和p+集电极层409，在背面电极410(例如AlSi/Ti/AlSi层叠构造)形成镀镍电极402，并通过烧结层(例如烧结Cu)与陶瓷衬底上的集电极配线101连接。在IGBT芯片的表面上形成的栅极配线为了通过绝缘氧化膜407进行电绝缘从而保持耐压，在栅极配线下面配置有PWEL405。栅极配线由第一栅极配线206和第二栅极配线202构成，例如第一栅极配线206由多晶硅形成，第二栅极配线由铝形成，第一栅极配线206与第二栅极配线202在有源区域的外周部通过触点(例如Ti/TiN/W)连接。在IGBT芯片最外周的区域中配置有铝场板403和PWEL405，它们起到保持耐压的作用。在有源区域中，配置有发射极电极205(例如AlSi/Ti/AlSi层叠构造)，与背面电极相同地形成了镀镍电极402，并通过烧结层(例如烧结Cu)与导电部件107连接。发射极电极、第二栅极配线202以及铝场板403通过聚酰亚胺406而被绝缘。在此，导电部件107被要求具有缓和由于半导体芯片与配线部件之间的热膨胀率差导致的热应力的作用以及对来自半导体芯片的热进行散热的作用。因此，作为导电板，优选使用具有半导体芯片与配线部件的中间的热膨胀率，并且热传导率为100W/mK以上的材料。并且，作为导电部件107，如果使用与半导体芯片的电极面平行的方向的热传导率比垂直方向的热传导率高的材料，则芯片的发热在传导到上部的接线、条带等配线之前，在导电板的沿着芯片面的面内进行热扩散，从容能够得到良好的均热效果，因此不会存在仅芯片的特定部分成为高温使得接线、条带剥离的情况，作为整个芯片，配线连接可靠性提高。例如，能够使用将具有在某个面为20W/mK，但在其垂直方向上为200W/mK这样的热传导各向异性的石墨纤维与金属(铜、铝等)进行复合后的材料。另外，优选使用将铜/因瓦合金/铜的包覆材料等的具有不同的热传导率的层进行层叠后的材料。其原因之一在于，因瓦合金(铁镍合金)的热传导率为13W/mK，比铜的400W/mK小，因此难以将半导体芯片的发热传导到上部，沿着芯片面热在铜内部传导从而均热化。另一个原因在于，能够通过铜(热膨胀率约为16ppm/K)与因瓦合金(约1ppm/K)的比例，将热膨胀率调整为Si、SiC(3～5ppm/K)与配线部件(铝约为23ppm/K，Cu约为16ppm/K)的中间的优选值，从而能够降低热应力。
关于导电部件107与IGBT芯片之间的通过烧结层的连接具有以下的方法等：使用在烧结材料涂覆部分开口的金属掩膜，只对需要的部分进行涂覆的方法；使用撒布器对需要的部分进行涂覆的方法；使用仅需要的部分开口的金属掩膜或网状掩膜来涂覆包含有机硅和氟等的防水树脂，或者在衬底或电子部件上涂覆具有感光性的防水树脂，通过曝光和显影来去除用于涂覆接合材料的部分，向该开口部涂覆用于接合的膏的方法；在向衬底或电子部件涂覆防水性树脂后，在通过激光去除了用于涂覆接合材料的部分后，向该开口部涂覆用于接合的膏的方法。能够根据进行接合的电极的面积、形状来组合这些涂覆方法。在本实施例中，在导电部件107下面印刷涂覆烧结层来进行接合。
在使用了本接合材料的接合中，优选在接合时通过金属颗粒前驱体生成颗粒直径为100nm以下的金属颗粒，一边排出接合层中的有机物，一边为了通过颗粒直径为100nm以下的金属颗粒的熔合进行金属结合而施加热和0.01～5MPa的压力。配置在第一栅极配线206上的发射极电极205和镀镍402起到如下效果：降低由于与导电部件107进行连接时的压力导致的过剩应力而引起的第一栅极配线206和Si衬底内的裂纹的产生。
接着，详细说明栅极配线区域与发射极电极区域的关系。
图5是半导体装置的IGBT芯片的部分的表面的主要部分布局图。本实施例的半导体装置是具备所谓的沟槽栅极型IGBT芯片的半导体装置，该沟槽栅极型IGBT芯片由栅极为侧栅极结构的一种的沟槽栅极501形成，但本发明并不限于沟槽栅极型。即，具备沟槽栅极型IGBT芯片的结构只不过是一个例子，具备具有其他栅极结构的半导体芯片的半导体装置也包含在本发明的技术范围内。另外，在图6和图7中分别表示图5中的B区域和C区域的鸟瞰图。栅极配线被大致分为有源部内栅极配线504和最外周栅极配线503。
在各栅极配线之间，以栅极配线正交的方式配置了沟槽栅极501，在沟槽栅极之间形成有表面n+层507、表面p+层508、表面p层509。表面n+层507是施加了栅极电压时的电子的来源，表面p层509起到决定施加栅极电压时的阈值电压的作用。表面p+层508向表面p层509施加电位，并且成为IGBT动作时的霍尔电流路径。表面p+层508和表面n+层507经由发射极电极连接触点506与发射极电极205连接。在发射极电极上形成了镀镍电极402，通过烧结层401与导电部件107连接。在此，在配置导电部件107的有源部内第一栅极配线206上至少形成有覆盖它的发射极电极205和烧结层401，并在此之上配置导电部件107。特别是在本实施例中，具有以下结构：在发射极电极205上形成有镀镍电极402，进而在其上形成烧结层401，即如上所述至少包含发射极电极205和烧结层401而构成的多层构造(即层数为2以上的层构造)在发射极电极205与烧结层401之间具备以镍为所含成分的电极层(例如镀镍电极402)，但本发明并不限于该结构，镀镍电极402并不是必需的构成要素。另外，上述的多层构造被配置为不仅连续存在于发射极引出区域(发射极电极连接触点506所在的区域)，还在包含发射极电极连接触点506和栅极配线区域(有源部内栅极配线504所在的区域以及最外周栅极配线503的一部分所在的区域)的整个广阔的范围内连续存在。即，本实施例的半导体装置是具备半导体芯片105、在半导体芯片105的表面形成的第一栅极配线206以及第二栅极配线202、以覆盖第一栅极配线206的方式配置的发射极电极205、在发射极电极205的上方配置的烧结层401的半导体装置，并且是在半导体芯片105的表面上，至少包含发射极电极205和烧结层401而构成的多层构造在包含发射极电极连接触点506以及栅极配线区域503、504的整个范围内连续存在的半导体装置。该多层构造起到主要保护栅极配线区域免受烧结接合时的压力的影响的作用，另外还起到保护Si衬底内的作用。
例如能够使第一栅极配线206为内嵌沟槽型栅极配线，但本发明并不限于该结构，也可以是形成了图6所示的非内嵌型等其他类型的栅极配线的结构。另外，最外周栅极配线区域通过最外周第二栅极配线触点701将第一栅极配线206与第二栅极配线202连接起来。
在第二栅极配线上形成有用于与发射极电极和末端部铝场板绝缘的聚酰亚胺406。优选栅极配线向IGBT芯片内分配通过栅极电极焊盘输入的信号，均等地分配栅极信号。关于栅极信号，根据由栅极配线电阻和栅极电容决定的CR时间常数而产生延迟。优选配置栅极配线，使得由于硅化而产生的低电阻化或由于芯片内分割配线而产生的CR时间常数的差变小。在图9、图10以及图11中，分别表示了现有技术的截面构造、IGBT芯片表面的主要部分布局以及鸟瞰图。当在有源部内第一栅极配线206上，经由有源部内第二栅极配线触点1002在有源部内设置了第二栅极配线801时，有源部内第二栅极配线与发射极电极205之间的阶梯差大，由于将导电部件107与IGBT芯片进行连接时的压力，无论压力是否均等，在第二栅极配线801和Si内部产生裂纹，产生栅极和作为主电极的发射极之间的短路不良。根据本发明的结构，能够减小有源部内第二栅极配线与发射极电极205之间的阶梯差，均等地施加压力，并且通过发射极电极和镀镍对于栅极配线的机械性的保护，能够减少裂纹的产生。
(实施例2)
图12是本发明的第二实施方式的实施例2的半导体装置的IGBT芯片的部分的主要部分布局图。另外，图13是图12的E区域的鸟瞰图。对于与实施例1相同的结构的部分赋予相同的附图标记，并省略重复地方的说明。
本实施例的特征点在于，由内嵌在沟槽部分的内嵌栅极配线1201形成了有源部内栅极配线504，该点与实施例1不同，但其他事项与实施例1相同。内嵌栅极配线1201与沟槽栅极501在同一工序中形成，将沟槽栅极501以及内嵌栅极配线1201在沟槽内连接。与实施例1相比，能够进一步降低有源部内栅极配线504与发射极电极205之间的阶梯差。能够更加均等地施加通过烧结层将导电部件107与IGBT芯片连接时的压力，并且通过发射极电极和镀镍对于栅极配线的机械性的保护，能够减少裂纹的发生。
(实施例3)
图14是本发明的第三实施方式的实施例3的半导体装置的IGBT芯片的部分的主要部分布局图。另外，图15是图14的F区域的鸟瞰图。对与实施例1和实施例2相同的结构的部分赋予相同的附图标记，并省略重复地方的说明。
在本实施例的半导体装置中，由作为侧栅极结构的一种的侧墙栅极1403构成栅极，有源部内栅极配线504由内嵌侧墙型栅极配线1402形成，并与侧墙栅极1403连接。本实施例以该点为特征，另外，该点与实施例1和实施例2不同，但其他事项与实施例1相同。
通过设置宽幅的沟槽1401，而删除浮动p层1202。由此，因浮动p层的影响导致的栅极的电位变动消失，dv/dt的控制性得到提高。并且，根据侧墙栅极1403结构，用厚的绝缘膜覆盖了沟槽栅极501的单侧。由此，降低了反馈电容，因此dv/dt的控制性得到提高。在设置在宽幅沟槽1401内的侧墙栅极1403之间，设置与发射极电极205连接的多晶硅场板1404。通过多晶硅场板1404来缓和在侧墙栅极1403的角部的电场，因此确保耐压。另外，通过多晶硅场板1404，缓和由于设置宽幅沟槽1401而产生的阶梯差。与实施例2同样地，能够通过内嵌侧墙型栅极配线1402，降低有源部内栅极配线504与发射极电极205之间的阶梯差，能够更均等地施加通过烧结层连接导电部件107和IGBT芯片时的压力，并且通过发射极电极和镀镍对于栅极配线的机械性保护，能够减少裂纹的发生。
(实施例4)
以下说明将本发明的半导体装置应用于电力变换装置的实施方式的一个例子的实施例4。
图16是表示将本发明的实施例1的半导体装置用作构成要素的电力变换装置600的电路框图。作为本发明的电力变换装置的一个例子，图16表示本实施例的电力变换装置600的电路结构以及直流电源与三相交流电动机(交流负载)的连接关系。
在本实施例的电力变换装置600中，将第一实施方式的半导体装置用作电力开关元件601～606。电力开关元件601～606例如是IGBT。
如图16所示，第四实施方式的电力变换装置600具备作为一对直流端子的P端子631和N端子632、作为与交流输出的相数相同数量的交流端子的U端子633、V端子634、W端子635。
另外，具备由一对电力开关元件601和602的串联连接构成，且以连接在其串联连接点的U端子633为输出的开关腿(switching leg)。另外，具备与之相同结构的由电力开关元件603和604的串联连接构成，并以连接在其串联连接点的V端子634为输出的开关腿。另外，具备与之相同结构的由电力开关元件605和606的串联连接构成，并以连接在其串联连接点的W端子635为输出的开关腿。
电力开关元件601～606例如是IGBT。
由电力开关元件601～606构成的3相的开关腿连接在P端子631、N端子632的直流端子之间，由未图示的直流电源供给直流电力。将电力变换装置600的3相的交流端子即U端子633、V端子634、W端子635作为三相交流电源与未图示的三相交流电动机连接。
电力开关元件601～606分别逆并联地连接了二极管621～626。在由IGBT构成的电力开关元件601～606各自的栅极的输入端子，通过栅极电路511～516进行控制。
即，本实施例的电力变换装置是从外部输入直流电力，将输入的上述直流电力变换为交流电力并输出的电力变换装置，其具备用于输入直流电力的一对直流端子(631、632)以及用于输出交流电力的交流端子即与该交流电力的交流相数相同数量的交流端子(633、634、635)，并且还具有以下结构：对于相数数量的交流端子(633、634、635)中的各个交流端子，在一对直流端子(631、632)中的一方(P端子)与另一方(N端子)之间连接了将两个并联电路(例如601和621的并联电路)串联连接的结构的串联电路(例如601和621的并联电路与602和622的并联电路的串联电路)，上述并联电路将开关元件(例如601)与极性与该开关元件相反的二极管(例如621)相互并联连接而成，构成该串联电路的2个并联电路的相互连接点连接在与该串联电路对应的相(例如U相)的交流端子(例如U端子633)。另外，该结构的并联电路由本发明的半导体装置(例如实施例1～3中的任意一个实施例的半导体装置)构成。
如上所述，将实施例1的半导体装置作为将IGBT芯片和续流二极管芯片安装在共同的陶瓷衬底上的集电极配线上的模块进行了说明，但本发明并不限于该结构，例如本发明的技术范围还包含将MOSFET芯片与续流二极管芯片一起安装的结构、或安装MOSFET芯片但不安装续流二极管芯片，将MOSFET芯片的体二极管作为回流二极管使用的所谓的无二极管的结构。由此可知，关于图16中的开关元件601、602、603、604、605、606以及二极管621、622、623、624、625、626之间的关系，当然也与之相同。即，在实施例1中说明的作为将IGBT芯片与续流二极管芯片安装在共同的陶瓷衬底上的集电极配线上的模块的半导体装置中，开关元件601、602、603、604、605、606由半导体芯片(例如IGBT芯片105)构成，另外，二极管621、622、623、624、625、626由二极管芯片106构成，该二极管芯片106通过与上侧的烧结层401分离的下侧的烧结层401与半导体芯片105一起与共同的陶瓷衬底101上的集电极配线103相接合，但本发明的电力变换装置并不限于此。
此外，通过综合控制电路(未图示)来综合控制栅极电路611～616的结构较为合适。
通过栅极电路611～616分别恰当地综合控制电力开关元件601～606，将直流电源Vcc的直流电力变换为三相交流电力，并从U端子、633、V端子634、W端子635输出。
通过将上述各实施方式的半导体装置应用于电力变换装置600，电力变换装置600的长期可靠性得到提高。另外，因为不使用焊料所以是无铅的，对环境具有良好的效果。另外，能够安装在高温环境的地方，并且即使不具有专用的冷却器也能够确保长期的可靠性。
如上所述，根据本发明的上述各实施例，能够提供一种半导体装置和使用该半导体装置的电力变换装置，该半导体装置在将金属板(导电部件)烧结接合在IGBT那样的具有栅极构造的半导体芯片上时，即使在烧结接合过程中进行加压，也难以在半导体芯片的栅极配线部产生过剩的应力，减少了栅极与作为主电极的发射极之间的短路不良、发射极-集电极之间的主耐压下降不良等特性不良。
由此，本发明与电子部件中的电气接合部(例如半导体元件与电路部件的接合部)的接合层有关，特别适合用于具有以下接合层的半导体装置，该接合层是使用以氧化铜颗粒作为主要材料的接合材料进行了接合的接合层。
此外，在本实施方式中，作为将本发明的半导体装置应用于电力变换装置的例子，说明了逆变器装置的情况，但并不限于此，也能够应用于直流-直流变换器、交流-直流变换器等其他的电力变换装置。
附图标记说明
101：陶瓷衬底；102：陶瓷衬底上栅极配线；103：陶瓷衬底上集电极配线；104：陶瓷衬底上发射极配线；105：IGBT芯片；106：二极管芯片；107：导电部件；108：接合线；109：陶瓷衬底上发射极感测配线；201：末端区域；202：第二栅极配线；204：第二栅极电极焊盘；205：发射极电极；206：第一栅极配线；401：烧结层；402：镀镍电极；403：末端部铝场板；404：触点；405：PWEL；406：聚酰亚胺；407：绝缘氧化膜；408N-Si基板；409：p+集电极层；410：背面集电极电极；411：N缓冲层；501：沟槽栅极；502：末端部铝场板触点；503：最外周栅极配线；504：有源部内栅极配线；505：第二栅极配线连接触点；506：发射极电极连接触点；507：表面n+区域；508：表面p+区域；509：表面p区域；510：栅极氧化膜；701：最外周第二栅极配线触点；801：有源部内第二栅极配线；1002：有源部内第二栅极配线触点；1201：内嵌栅极配线；1401：宽幅沟槽区域；1402：内嵌栅极配线；1403：侧墙栅极；1404：多晶硅场板；1405：多晶硅场板上发射极触点；600：电力变换装置；601～606：电力开关元件；621～626：二极管；611～616：栅极电路。

Claims (9)

1.一种半导体装置，其特征在于，具备：
半导体芯片；
在上述半导体芯片的表面形成的内嵌在沟槽内的内嵌型的栅极；
与上述内嵌型的栅极在同一层形成的内嵌型的第一栅极配线；
相对于上述内嵌型的第一栅极配线配置在上层的第二栅极配线；
与上述第二栅极配线形成在同一层，以覆盖上述第一栅极配线的方式配置的发射极电极；以及
配置在上述发射极电极上方的烧结层，
在上述半导体芯片的表面，在包含发射极电极连接触点和栅极配线区域的整个范围内连续存在至少包含上述发射极电极和上述烧结层而构成的多层构造。
2.根据权利要求1所述的半导体装置，其特征在于，
在上述发射极电极与上述烧结层之间具备以镍为所含成分的电极层来构成上述多层构造。
3.根据权利要求1所述的半导体装置，其特征在于，
上述栅极是侧栅极构造。
4.根据权利要求1所述的半导体装置，其特征在于，
上述第一栅极配线在上述沟槽内与上述栅极连接。
5.根据权利要求3所述的半导体装置，其特征在于，
上述侧栅极构造是上述栅极为侧墙栅极的侧墙栅极构造。
6.根据权利要求5所述的半导体装置，其特征在于，
上述第一栅极配线是与上述侧墙栅极连接的内嵌侧墙型栅极配线。
7.根据权利要求1～6中的任意一项所述的半导体装置，其特征在于，
上述半导体芯片通过与上述烧结层分离的其他烧结层与二极管芯片一起与共同的陶瓷衬底上的集电极配线相接合。
8.一种电力变换装置，其从外部输入直流电力，并将输入的上述直流电力变换为交流电力来输出，其特征在于，
上述电力变换装置具备：
一对直流端子，其用于输入上述直流电力；
交流端子，其用于输出上述交流电力，且该交流端子的数量与上述交流电力的交流相数相同，
上述电力变换装置还具有以下的结构：对于上述相数的上述交流端子中的各个交流端子，在上述一对直流端子中的一个直流端子与另一个直流端子之间连接将两个并联电路串联连接的结构的串联电路，并且将构成上述串联电路的两个上述并联电路的相互连接点与该串联电路所对应的相的上述交流端子连接，上述并联电路是将开关元件和极性与该开关元件相反的二极管相互并联连接而成的并联电路，
上述并联电路由权利要求1～6中的任意一项所述的半导体装置构成。
9.根据权利要求8所述的电力变换装置，其特征在于，
上述开关元件由上述半导体芯片构成，
上述二极管由二极管芯片构成，
上述二极管芯片通过与上述烧结层分离的其他烧结层与上述半导体芯片一起与共同的陶瓷衬底上的集电极配线相接合。
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