CN110098166A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN110098166A
CN110098166A CN201910039792.6A CN201910039792A CN110098166A CN 110098166 A CN110098166 A CN 110098166A CN 201910039792 A CN201910039792 A CN 201910039792A CN 110098166 A CN110098166 A CN 110098166A
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China
Prior art keywords
film
layer
solder layer
metal film
semiconductor devices
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CN201910039792.6A
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English (en)
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土屋秀昭
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN110098166A publication Critical patent/CN110098166A/zh
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Abstract

本公开总体涉及半导体器件及其制造方法。半导体器件包括形成在半导体衬底之上的焊盘电极，形成在焊盘电极上的导体柱，形成在导体柱上且由镍膜制成的盖帽膜，形成在布线板中的端子，形成在端子上并由包含磷的镍膜制成的金属膜，***在盖帽膜和金属膜之间且包含锡作为主要成分的焊料层，以及***在焊料层和金属膜之间且包含锡和铜的合金层。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求享有2018年1月30日提交的日本专利申请No.2018-013192的优先权，该申请在此通过全文引用的方式将其内容并入本申请。
技术领域
本发明涉及一种半导体器件及其制造方法，并且涉及例如一种可有效地可应用于使用具有阻挡金属规范的布线板的半导体器件及其制造方法。
背景技术
日本专利申请公开No.2013-211511(专利文献1)公开了一种其中半导体芯片SC的电极焊盘PAD与布线板INT的连接端子TER由Cu柱体PIL构成的凸块电极以及焊料层SOL连接的结构。进一步，专利文献1公开了Ni层NIL***在Cu柱体PIL和焊料层SOL之间以便于防止由于电迁移Cu从Cu柱体PIL扩散至Sn基焊料层SOL。
日本专利申请公开No.2014-053608(专利文献2)公开了一种具有使用电镀方法的阻挡金属规范的布线板。也即，布线板的电路图形(上述“连接端子”)的表面采用镍层/金层的堆叠膜或者镍层/钯层/金层的堆叠膜覆盖。此外，作为电镀方法，公开了无电金电镀系列的表面处理诸如ENIG(无电电镀镍沉浸金)或ENEPIG(无电电镀镍无电电镀钯沉浸金)。
发明内容
本发明的发明人已经研究了一种半导体器件，其中专利文献1的半导体芯片安装在专利文献2的布线板上。根据由本发明的发明人做出的研究，已经发现在这样的半导体器件中缩短了将半导体芯片的电极焊盘和布线板的连接端子连接的凸块电极的电迁移寿命。换言之，已经发现在半导体芯片和布线板之间的连接结构中缩短了电迁移寿命并且无法确保半导体器件的可靠性。
也即，在使用具有阻挡金属规范(barrier metal specification)的布线衬底的半导体器件中，需要改进可靠性。
本发明的其他问题和新颖特征将从本说明书和附图的描述而明显。
根据实施例的半导体器件包括：在半导体衬底之上形成的焊盘电极；在焊盘电极上形成的导体柱；在导体柱上形成并由镍膜支撑的盖帽膜；在布线板中形成的端子；在端子上形成并由包含磷的镍膜制成的金属膜；***在盖帽膜和金属膜之间并包含锡作为主要成分的焊料层；以及***在焊料层和金属膜之间并包含锡和铜的合金层。
根据实施例，能够改进半导体器件的可靠性。
附图说明
图1是根据本实施例的半导体器件的俯视图；
图2是根据本实施例的半导体器件的底视图；
图3是根据本实施例的半导体器件的局部剖视图；
图4是示出了根据本实施例的半导体器件的制造工艺的工艺流程图；
图5是在根据本实施例的半导体器件的制造工艺中主要部分的剖视图；
图6是示出了图5中部分A的配置的主要部分的剖视图；
图7是示出了根据本实施例的半导体芯片的配置的主要部分的剖视图；
图8是根据本实施例的半导体芯片的制造工艺中主要部分的剖视图；
图9是从图8继续的半导体芯片的制造工艺中主要部分的剖视图；
图10是从图9继续的半导体芯片的制造工艺中主要部分的剖视图；
图11是从图10继续的半导体芯片的制造工艺中主要部分的剖视图；
图12是根据本实施例的半导体器件的制造工艺中主要部分的剖视图；
图13是示出了图12中部分B的配置的主要部分的剖视图；
图14是根据本实施例的半导体器件的制造工艺中主要部分的剖视图；
图15是示出了图14中部分C的配置的主要部分的剖视图；
图16是根据本实施例的半导体器件的制造工艺中主要部分的剖视图；
图17是根据本实施例的半导体器件的制造工艺中主要部分的剖视图；
图18是示出了根据本实施例的半导体器件的效果的图；
图19是根据比较示例的半导体器件的主要部分的剖视图；
图20是示出了图19中部分D的配置的剖视图；
图21是根据第一修改例的半导体器件的制造工艺中主要部分的剖视图；
图22是根据第一修改例的半导体器件的制造工艺中主要部分的剖视图；
图23是根据第二修改例的半导体器件的制造工艺中主要部分的剖视图；
图24是根据第二修改例的半导体器件的制造工艺中主要部分的剖视图；以及
图25是根据第二修改例的半导体器件的制造工艺中主要部分的剖视图。
具体实施方式
在以下描述的实施例中，当为了方便起见需要时将在多个部分或实施例中描述本发明。然而，这些部分或实施例并非相互不相关除非另外说明，并且作为其修改示例、细节、或补充说明，一个与另一个的整体或一部分相关。
此外，在以下所述实施例中，当涉及元件的数目(包括块件的数目、数值、数量、范围等等)时，元件的数目不限于具体数目除非另外说明，或者除了其中数目明显原则上限定于具体数目的情形之外，并且大于或小于所规定数目的数目也是可应用的。
进一步，在以下所述的实施例中，构成元件(包括元件步骤)并非总是必不可缺的，除非另外说明，或者除了其中构成元件明显原则上必不可少的情形之外。
类似地，在以下所述的实施例中，当提到构成元件的形状、其位置关系等等时，其中包括了实质上近似和类似的形状等，除非另外说明，或者除了其中可以设想原则上明显地排除它们的情形之外。同理适用于上述数值和范围。
此外，遍及附图原则上由相同的参考符号标注相同的组件以用于描述实施例，并且将省略其重复性说明。注意，甚至在平视图中有时应用阴影以便于使得附图容易查看。
(实施例)
<半导体器件的结构>
图1是根据本发明一个实施例的半导体器件的俯视图。图2是根据本实施例的半导体器件的底视图。图3是根据本实施例的半导体器件的局部剖视图。
如图1中所示，根据本实施例的半导体器件SA包括方形布线板WB，并且矩形半导体芯片CHP经由密封材料(下填料)UF而被安装在布线板WB的主表面的中心上。如图1中所示，半导体芯片CHP的尺寸小于布线板WB。注意，布线板WB可以具有矩形形状且半导体芯片CHP可以具有方形形状。
接着，如图2中所示，多个焊料球SB以阵列设置在布线板WB的背表面上。图2示出了其中焊料球SB以四行沿着布线板WB的外侧周缘部分(外侧边缘部分)而设置的示例。这些焊料球SB用作用于将半导体器件SA连接至外部设备的外部连接端子。也即，当半导体器件SA安装在例如由母板所代表的电路板上时使用焊料球SB。焊料球SB也可以以矩阵图形设置在布线板WB的整个背表面之上。
图3是根据本实施例的半导体器件SA的局部剖视图。尽管布线板WB具有多层布线结构，但是图3仅示出了用于核心层CL的每个一层，在核心层CL的主表面侧上的布线WL1，以及在背表面侧上的布线WL2。布线WL1和WL2由铜(Cu)膜制成。在核心层CL的主表面侧上形成的布线WL1的上表面和侧表面由阻焊膜SR1覆盖。在布线WL1的一部分中形成的端子TA在阻焊膜SR1中所提供的开口处，从阻焊膜SR1暴露，并且连接至开口中的凸块电极BE2。在核心层CL的背表面侧上形成的布线WL2的下表面和侧表面由阻焊膜SR2覆盖。在布线WL2的一部分中形成的焊岛LND在提供于阻焊膜SR2中开口处从阻焊膜SR2暴露，并且焊料球SB连接至开口中的焊岛LND。主表面上布线WL1通过提供在穿透核心层CL的通孔中的布线WL3而连接至在背表面上的布线WL2。阻焊膜SR1和SR2是由绝缘树脂制成的绝缘膜，并且核心层CL由绝缘树脂衬底诸如玻璃环氧树脂制成。
半导体芯片CHP安装在布线板WB上，并且连接至在半导体芯片CHP的主表面上形成的焊盘电极PA的凸块电极BE2被连接至从阻焊膜SR1暴露的端子TA。进一步，密封材料(下填料)被注入以填充半导体芯片CHP和布线板WB之间的间隙。也即，半导体芯片CHP经由凸块电极BE2而安装在布线板WB的主表面上，从而半导体芯片CHP的主表面面对布线板WB的主表面。进一步，半导体芯片CHP的主表面和布线板WB的主表面之间的空间完全由密封材料UF填充，并且多个凸块电极BE2之间的空间也完全由密封材料UF填充。换言之，凸块电极BE2的侧壁(侧表面，正面)在整个周缘中与密封材料UF接触。密封材料UF例如被提供用于弱化施加至凸块电极BE2和端子TA之间接合部分的应力，并且由绝缘树脂膜诸如环氧树脂制成。
<半导体器件的制造方法>
接着，将参照图4至图17描述根据本实施例的半导体器件的制造方法。图4是示出了根据本实施例的半导体器件的制造工艺的工艺流程图。图5是根据本实施例的半导体器件的制造工艺中主要部分的剖视图，并且示出了半导体芯片的示意性剖视图。图6是示出了图5中部分A的配置的主要部分的剖视图，以及图7是示出了根据本实施例的半导体器件的配置的主要部分的剖视图。进一步，图8至图11是半导体芯片的制造工艺中主要部分的剖视图。图12是根据本发明的半导体器件的制造工艺中主要部分的剖视图，以及图13是示出了图12中部分B的配置的主要部分的剖视图。图14是在根据本实施例的半导体器件的制造工艺中主要部分的剖视图，以及图15是示出了图14中部分C的配置的主要部分的剖视图。图16和图17是根据本实施例的半导体器件的制造工艺中主要部分的剖视图。
如图4中所示，根据本实施例的半导体器件的制造方法包括半导体芯片制备步骤、布线板制备步骤、半导体芯片连接步骤、密封材料注入步骤以及焊料球形成步骤。进一步，在半导体芯片制备步骤和布线板制备步骤执行之后，可以顺序地执行半导体芯片连接步骤、密封材料注入步骤和焊料球形成步骤。
首先，执行图4中的半导体芯片制备步骤。如图5中所示，半导体芯片CHP包括多个焊盘电极PA以及在每个焊盘电极PA上形成的凸块电极BE1。如图6中所示，焊盘电极BE1具有其中种子层12、导体柱13、盖帽膜14、金属膜15以及焊料层16顺序堆叠的配置。在图6中，示出半导体芯片CHP以使得主表面朝下。
如图6中所示，焊盘电极PA被形成在半导体衬底1之上。由无机绝缘膜制成的表面保护膜(保护膜，绝缘膜)10被形成在半导体衬底1之上以便于覆盖焊盘电极PA。表面保护膜10由例如氧化硅膜和氮化硅膜之类的堆叠结构构成，并且机械地保护稍后所述的半导体元件和布线。此外，例如由聚酰亚胺树脂膜制成的保护膜(有机绝缘膜)11被形成在表面保护膜10上。表面保护膜10具有开口10a，并且焊盘电极PA从开口10a暴露。此外，保护膜11具有开口11a，其直径小于开口10a的直径，并且焊盘电极PA从开口11a暴露。进一步，凸块电极BE1通过开口11a连接至焊盘电极PA。
如图6中所示，因为保护膜11被***在凸块电极BE1和半导体芯片CHP之间，因此可以抑制施加至凸块电极BE1的应力传播至半导体芯片CHP，从而可以防止在半导体芯片CHP中出现裂缝。
如图7中所示，半导体芯片CHP包括被形成在半导体衬底1上的半导体元件，诸如n沟道MIS晶体管(Qn)和p沟道MIS晶体管(Qp)，以及形成在半导体衬底1之上的第一层Cu布线5、第二层Cu布线7和第三层Al布线9。
如图7中所示，p型阱区2P、n型阱区2N以及元件隔离沟槽3被形成在例如由p型单晶硅制成的半导体衬底1中，并且例如由氧化硅膜制成的元件隔离膜被掩埋在元件隔离沟槽3中。
n沟道MIS晶体管(Qn)形成在p型阱区2P中。n沟道MIS晶体管(Qn)形成在由元件隔离沟槽3所限定的有源区域中，并且包括形成在p型阱区2P中的源极区域ns和漏极区域nd、以及经由栅极绝缘膜ni而形成在p型阱区2P上的栅极电极ng。此外，p型沟道MIS晶体管(Qp)形成在n型阱区2N中，且p沟道MIS晶体管(Qp)包括源极区域ps和漏极区域pd、以及经由栅极绝缘膜pi而形成在n型阱区2N上的栅极电极pg。
由金属膜制成的用于连接这些半导体元件的布线形成在n沟道MIS晶体管(Qn)和p沟道MIS晶体管(Qp)之上。用于连接半导体元件的布线通常具有由三至十层构成的多层布线结构，尽管图7作为多层布线的示例而示出了在由包含铜合金作为主要成分的金属膜制成的两个层(第一层Cu布线5，第二层Cu布线7)中的布线层，以及在由包含Al合金作为主要成分的金属膜制成的一个层(第三层Al布线9)中的布线层。当共同地示出形成在各个布线层中多个布线时使用布线层。关于布线层的膜厚度，第二层中布线层比第一层中布线层更厚，且第三层中布线层比第二层中布线层更厚。
均由氧化硅膜等制成的层间绝缘膜4、6和8以及用于电连接三个层中的布线的插塞p1、p2和p3被分别形成在n沟道MIS晶体管(Qn)和p沟道MIS晶体管(Qp)之间、在第一层Cu布线5和第二层Cu布线7之间、以及在第二层Cu布线7和第三层Al布线9之间。
层间绝缘膜4形成在半导体衬底1之上以便于覆盖半导体元件，并且第一层Cu布线5形成在层间绝缘膜4上的绝缘膜5a中。第一层Cu布线5通过形成在层间绝缘膜4中的插塞p1而电连接至作为半导体元件的n沟道MIS晶体管(Qn)的源极区域ns、漏极区域nd、以及栅极电极ng。此外，第一层Cu布线5通过在层间绝缘膜4中形成的插塞p1而电连接至作为半导体元件的p沟道MIS晶体管(Qp)的源极区域ps、漏极区域pd、以及栅极电极pg。栅极电极ng和pg与第一层Cu布线5之间的连接未示出。插塞p1、p2和p3由金属膜例如W(钨)膜制成。第一层Cu布线5由大马士革方法形成在绝缘膜5a的布线沟槽中，并且第一层Cu布线5由堆叠结构构成，包括阻挡导体膜以及在其上层中包含铜作为主要成分的导体膜。阻挡导体膜由钽(Ta)、钛(Ti)、钌(Ru)、钨(W)、锰(Mn)、其氮化物、其氮硅化物、或其堆叠膜制成。包含铜作为主要成分的导体膜由铜(Cu)或铜合金(铜(Cu)与铝(Al)、镁(Mg)、钛(Ti)、锰(Mn)、铁(Fe)、锌(Zn)、锆(Zr)、铌(Nb)、钼(Mo)、钌(Ru)、钯(Pd)、银(Ag)、金(Au)、铟(In)、镧系金属、放射性金属等的合金)形成。
第二层Cu布线7通过例如形成在层间绝缘膜6中的插塞p2而电连接至第一层Cu布线5。第三层Al布线9通过例如形成在层间绝缘膜8中的插塞p3而电连接至第二层Cu布线7。插塞p3由金属膜例如W(钨)膜制成。
第二层Cu布线7与层间绝缘膜6中的插塞p2整体地形成，并且第二层Cu布线7与插塞p2由包括阻挡导体膜和在其上层中包含铜作为主要成分的导体膜的堆叠结构构成。此外，阻挡导体膜和包含铜作为主要成分的导体膜由与第一层Cu布线5相同的材料制成。
此外，用于防止铜扩散至层间绝缘膜6或8的阻挡绝缘膜优选地均被提供在第一层Cu布线5和层间绝缘膜6之间以及在第二层Cu布线7和层间绝缘膜8之间，并且SiCN膜或SiCN膜与SiCO膜的堆叠膜可以用作阻挡绝缘膜。
此外，第三层Al布线9由铝合金膜(例如Si和Cu添加至其中的Al膜)制成。备选地，第三层Al布线9可以是Cu布线。
进一步，层间绝缘膜4由氧化硅膜(SiO2)制成。备选地，层间绝缘膜4自然可以由包含碳的氧化硅膜(SiOC膜)、包含氮和碳的氧化硅膜(SiOCN膜)、和包含氟的氧化硅膜(SiOF膜)的单层膜或堆叠膜制成。
上述表面保护膜10形成在作为多层布线的最上层布线层的第三层Al布线9上。此外，作为在形成于表面保护膜10中的开口(焊盘开口)10a底部处暴露的最上层布线层的第三层Al布线9构成了焊盘电极(焊盘，电极焊盘)PA。
接着，将参照图8至图11描述凸块电极BE1的制造方法。
如图8中所示，具有暴露了焊盘电极PA的一部分的开口11a的保护膜11被形成在半导体衬底1之上。
随后，如图9中所示，由铜膜制成的种子层12被形成在保护膜11上。种子层12例如由溅射方法形成，并且具有100至500nm的膜厚度。种子层12在开口11a中与焊盘电极PA接触。注意，优选地在焊盘电极PA和种子层12之间***阻挡层，以便于防止焊盘电极PA和种子层12之间反应。例如，阻挡层被形成为具有钛(Ti)膜和氮化钛(TiN)膜的堆叠结构，并且其厚度分别为10nm和50nm。随后，抗蚀剂层PR被形成在种子层12上。抗蚀剂层PR在其中形成凸块电极BE1的区域处具有开口PRa。
接着，如图10中所示，导体柱13、盖帽膜14、金属膜15以及焊料层16通过电镀方法顺序地形成在开口PRa中。导体柱13例如由铜(Cu)膜制成，并且具有大约50μm的膜厚度。盖帽膜14例如由镍(Ni)膜制成，并且具有0.1至10μm的膜厚度。金属膜15由铜(Cu)膜制成并且具有大约3至5μm的膜厚度。作为种子层16，可以使用包含锡(Sn)作为主要成分的合金诸如Sn-Ag-Cu、Sn-Cu、Sn-Zn、Sn-Ag-Bi以及Sn-Ag-In，并且其膜厚度例如为5至20μm。
随后，如图11中所示，移除抗蚀剂层PR，并且移除在从导体柱13、盖帽膜14、金属膜15和焊料层16暴露的区域中的种子层12。接着，在高于其熔点的温度下对焊料层16应用热处理，从而焊料层16具有如图6中所示实质上半球形状。以该方式，如图6中所示，在焊盘电极PA上形成了由种子层12、导体柱13、盖帽膜14、金属膜15以及焊料层16构成的凸块电极BE1。
接着，执行图4中的布线板制备步骤。如图12中所示，制备具有在主表面侧上多个端子TA和在背表面侧上多个焊岛的布线板WB。如图13中所示，采用阻焊膜SR1覆盖由铜(Cu)膜制成的端子TA，但是端子TA的上表面的一部分从开口SR1a暴露。在根据本实施例的具有阻挡金属规范的布线板WB中，端子TA由开口SR1a中金属膜18和阻挡层19顺序覆盖，并且焊料层17形成在阻挡层19上。在此，金属膜18由通过无电电镀方法形成的Ni膜制成。由无电电镀方法形成的Ni膜包含磷(P)作为还原剂并且标记为Ni-P。金属膜18是包含磷(P)的镍(Ni)膜。阻挡层19被配置作为通过无电电镀方法形成的钯(Pd)膜与通过沉浸电镀方法形成的金(Au)膜的堆叠膜，或者通过沉浸电镀方法形成的金(Au)膜的单层膜。此外，焊料层17与上述焊料层16相同。尽管未示出，但是上述金属膜18和阻挡层19也形成在布线板WB的焊岛LND上。
随后，执行图4中的半导体芯片连接步骤。如图14中所示，将图6中所示的焊料层16与图13中所示的焊料层17接触，并且在高于焊料层16和17的熔点的温度(例如220至260℃)执行回流(加热处理)工艺。接着，熔化焊料层16和17并形成两者整体成型的焊料层20，由此电连接焊盘电极PA和端子TA。具体地，如图15中所示，通过将图6中所示焊料层16和图13中所示焊料层17整体成型而形成焊料层20。此外，金属膜15中包含的铜(Cu)在回流工艺中扩散至焊料层20中，以便在金属膜15和焊料层20之间的界面以及金属膜18和焊料层20之间的界面的每一个处形成由铜(Cu)和锡(Sn)制成的合金层21。注意，图13中所示的阻挡层19在回流工艺中扩散至焊料层20中，并且因此在图15中未示出。
注意，如图15中所示具有连接了焊盘电极PA和端子TA的堆叠结构的导体层称作凸块电极BE2。也即，凸块电极BE2顺序地由种子层12、导体柱13、盖帽膜14、金属膜15、合金层21、焊料层20、合金层21、以及金属膜18构成。在此，提供导体柱13以用于确保凸块电极BE2的高度，并且优选地将其膜厚度设置为大于构成了凸块电极BE2的其他导体膜的厚度。此外，盖帽膜14具有防止焊料层20在回流工艺中毛细吸上导体柱13侧壁的效果。
接着，执行图4中的密封材料注入步骤。如图16中所示，由绝缘树脂膜制成的密封材料UF被注入至半导体芯片CHP和布线板WB之间的间隙中，并且随后由加热处理固化密封材料UF。
随后，执行图4中的焊料球形成步骤。如图17中所示，焊料球SB焊接至布线板WB的焊岛LND。因此，本实施例的半导体器件SA完成。
在本实施例中，极为重要的是，由铜(Cu)和锡(Sn)制成的合金层21被形成在金属膜18和焊料层20之间的界面处，如图15中所示。通过在回流工艺中在金属膜18和焊料层20之间界面处提供合金层21，可以防止在半导体器件的操作期间镍(Ni)从金属膜18扩散至焊料层20。尽管稍后描述，其能够防止金属膜18中脆性(brittle)层22的形成，并且可以防止在端子TA和焊料层20之间出现断开。
将使用比较示例描述这点。图19是根据比较示例的半导体器件的主要部分的剖视图，以及图20是示出了图19中部分D的配置的剖视图。如图19中所示，根据比较示例，金属膜15并未形成在半导体器件中，不同于上述本发明的实施例。
当对根据比较示例的半导体器件执行操作加速测试时，已经发现，如图19中所示在端子TA和焊料层20之间的界面处形成脆性层22，并且在脆性层22中出现断裂，从而端子TA和焊盘电极PA断开。在操作加速测试中，已经发现，电流方向相关性存在于脆性层22的形成中，且仅当电流从焊盘电极PA流动至端子TA时形成脆性层22。
图20示出了在操作加速测试中具有不同操作时间的三个状态(a)至(c)。操作时间以状态(a)、(b)和(c)的顺序变得更长。已经发现，随着操作时间流逝，脆性层22被形成在金属膜18中，并且裂缝出现在金属膜18中。当电流从焊盘电极PA流至端子TA时，电子如图20中所示从端子TA流动至焊盘电极PA。在该时刻，由无电电镀Ni-P制成的金属膜18中的镍(Ni)通过电迁移而扩散至焊料层20中。在镍(Ni)离开的区域中，形成了由包含许多杂混空穴23的Ni3P层制成的脆性层22，并且在脆性层22和端子TA之间的界面处出现裂缝。注意，在其中电流从端子TA流至焊盘电极PA的情形中，上述脆性层22并未形成在盖帽膜14中。因为盖帽膜14是通过电镀形成的膜且并未包含P，因此可以说，即使在电迁移的应力下Ni扩散至焊料层20中，也并未形成由Ni3P层制成的脆性层。
与比较示例相对照，如图15中所示，在本实施例中半导体器件SA的制造工艺中在回流工艺中在金属膜18和焊料层20之间的界面处形成了合金层21。因此，可以防止在半导体器件SA操作期间镍(Ni)从金属膜18扩散至焊料层20。也即，能够防止图19中所示脆性层22的形成。
因此，优选的是，形成合金层21以便于在金属膜18和焊料层20之间界面处在开口SR1a的整个区域之上具有所希望的膜厚度或更大。如果在回流工艺之后在金属膜18和焊料层20之间的界面处形成具有所希望膜厚度的合金层21，则并非总是需要保留金属膜15。然而，为了在金属膜18和焊料层20之间的界面处形成具有所希望膜厚度的合金层21，优选地如图15中所示在回流工艺之后在盖帽膜14和合金层21之间保留金属膜15。这是因为，优选地由回流温度和回流时间控制形成在金属膜18和焊料层20之间界面处合金层21的膜厚度。也即，极为重要的是，金属膜15具有足够的膜厚度以在回流之后保留。为此目的，图11中金属膜15的膜厚度优选地为3μm或更大。此外，当金属膜15的膜厚度太大时，存在焊料层20在回流期间毛细吸上金属膜15的剩余膜的侧壁的可能性，因此变得难以控制凸块电极BE2的高度。考虑到这点，优选地，金属膜15的膜厚度为5μm或更小。
图18是示出了根据本实施例的半导体器件的效果的图。水平轴表示故障ttf，且垂直轴表示累积故障。图(A)对应于根据本实施例的半导体器件，且图(B)对应于根据比较示例的半导体器件。可以确认，与比较示例相比，在根据本实施例的半导体器件中t 0.1寿命(在0.1％的累积故障下EM(电迁移)寿命)提高了大约4倍。
<第一修改例>
图21和图22是根据第一修改例的半导体器件的制造工艺中主要部分的剖视图。对于与上述本实施例共同的配置给出相同符号。图21和图22分别对应于上述本实施例的图6和图15。
如图21中所示，金属膜15a的宽度W1小于盖帽膜14的宽度W2。也即，金属膜15a的侧壁在整个周缘中由焊料层16覆盖。进一步，如图22中所示，如在上述本实施例中的回流工艺之后，在金属膜15a和焊料层20之间的界面以及在金属膜18和焊料层20之间的界面中的每个界面处形成合金层21a。
采用该配置，如图22中所示能够减小焊料层20毛细吸上导体柱13侧壁的概率。在上述本实施例的图15的情形中，假设焊料层20毛细吸上金属膜15的侧壁，并且担心焊料层20进一步毛细吸上导体柱13的侧壁而越过盖帽膜14。在图22中，金属膜15a的端部位于盖帽膜14端部的内侧上，并且因此能够减小焊料层20毛细吸上导体柱13侧壁的概率。
<第二修改例>
图23至图25是根据第二修改例的在半导体器件的制造工艺中主要部分的剖视图。对于与上述本实施例共同的配置给出相同符号。分别地，图23对应于上述本实施例的图13，图24对应于上述本实施例的图6，以及图25对应于上述本实施例的图15。
如图23中所示，在布线板WB的端子TA上顺序形成金属膜18、阻挡层19、和金属膜15b，并且焊料层17形成在金属膜15b上。在此，金属膜15b由铜(Cu)膜制成。
如图24中所示，因为在第二修改例中金属膜15b被提供在更靠近布线板WB的侧面上，因此铜(Cu)膜制成的金属膜并未提供在更靠近半导体芯片CHP的侧面上盖帽膜14和焊料层16之间。焊料层16与盖帽膜14接触。接着，如图25中所示，在如上述本实施例中的回流工艺之后，合金层21b形成在盖帽膜14和焊料层20之间的界面以及金属膜15b和焊料层20之间的界面中的每个界面处。
因为形成了合金层21b，能够防止在半导体器件SA操作期间镍(Ni)从金属膜18扩散至焊料层20。也即，能够防止图19中所示脆性层22的形成。
在上文中，已经基于实施例具体描述了由本发明的发明人做出的本发明。然而，无需多言，本发明不限于前述实施例，并且可以在本发明的范围内做出各种修改。

Claims (13)

1.一种半导体器件，包括：
焊盘电极，在半导体衬底之上形成；
导体柱，在所述焊盘电极上形成；
盖帽膜，在所述导体柱上形成并且由镍膜制成；
端子，在布线板中形成；
第一金属膜，在所述端子上形成并且由包含磷的镍膜制成；
焊料层，被***在所述盖帽膜和所述第一金属膜之间并且包含锡作为主要成分；以及
第一合金层，被***在所述焊料层和所述第一金属膜之间并且包含锡和铜。
2.根据权利要求1所述的半导体器件，进一步包括：
第二金属膜，被***在所述盖帽膜和所述焊料层之间并且由铜膜制成。
3.根据权利要求2所述的半导体器件，进一步包括：
第二合金层，被***在所述第二金属膜和所述焊料层之间并且包含锡和铜。
4.根据权利要求2所述的半导体器件，
其中，所述第二金属膜的宽度小于所述盖帽膜的宽度。
5.根据权利要求1所述的半导体器件，进一步包括：
第三金属膜，被***在所述第一金属膜和所述第一合金层之间、并且由铜膜制成。
6.根据权利要求1所述的半导体器件，
其中所述导体柱的膜厚度大于所述焊料层的膜厚度。
7.一种半导体器件的制造方法，包括步骤：
(a)制备半导体芯片，所述半导体芯片包括在半导体衬底之上形成的焊盘电极、在所述焊盘电极上形成的导体柱，在所述导体柱上形成并且由镍膜制成的盖帽膜、在所述盖帽膜上形成并且由铜膜制成的第一金属膜、以及在所述第一金属膜上形成并且包含锡作为主要成分的第一焊料层；
(b)制备布线板，所述布线板包括端子、在所述端子上形成并且由包含磷的镍膜制成的第二金属膜、以及在所述第二金属膜上形成且包含锡作为主要成分的第二焊料层；以及
(c)在其中所述第一焊料层和所述第二焊料层相互接触的状态下，对所述半导体芯片和所述布线板执行热处理，由此熔化所述第一焊料层和所述第二焊料层以形成第三焊料层，
其中，在所述步骤(c)中，在所述第二金属膜和所述第三焊料层之间形成包含锡和铜的第一合金层。
8.根据权利要求7所述的半导体器件的制造方法，
其中，在所述步骤(c)中，在所述第一金属膜和所述第三焊料层之间形成包含锡和铜的第二合金层。
9.根据权利要求7所述的半导体器件的制造方法，
其中，在所述步骤(a)中，所述第一金属膜的宽度小于所述盖帽膜的宽度，以及
在所述步骤(c)中，所述第三焊料层被形成为覆盖所述第一金属膜的侧壁。
10.根据权利要求7所述的半导体器件的制造方法，进一步包括步骤：
(d)在所述半导体芯片和所述布线板之间注入密封材料，
其中所述密封材料覆盖所述第三焊料层、所述第一金属膜、所述盖帽膜和所述导体柱的侧壁。
11.根据权利要求7所述的半导体器件的制造方法，进一步包括步骤：
(e)连接焊料球至焊岛，所述焊岛被形成在与所述布线板的所述端子相对的表面上。
12.一种半导体器件的制造方法，包括步骤：
(a)制备半导体芯片，所述半导体芯片包括在半导体衬底之上形成的焊盘电极、在所述焊盘电极上形成的导体柱、在所述导体柱上形成并且由镍膜制成的盖帽膜、以及在所述盖帽膜上形成并且包含锡作为主要成分的第一焊料层；
(b)制备布线板，所述布线板包括端子、在所述端子上形成并且由包含磷的镍膜制成的第一金属膜、在所述第一金属膜上形成并且由铜膜制成的第二金属膜、以及在所述第二金属膜上形成并且包含锡作为主要成分的第二焊料层；以及
(c)在其中所述第一焊料层和所述第二焊料层相互接触的状态下，对所述半导体芯片和所述布线板执行热处理，由此熔化所述第一焊料层和所述第二焊料层以形成第三焊料层，
其中，在所述步骤(c)中，在所述第二金属膜和所述第三焊料层之间形成包含锡和铜的第一合金层。
13.根据权利要求12所述的半导体器件的制造方法，
其中，在所述步骤(c)中，在所述盖帽膜和所述第三焊料层之间形成包含锡和铜的第二合金层。
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