CN102142418A - 半导体结构及半导体装置的制造方法 - Google Patents

半导体结构及半导体装置的制造方法 Download PDF

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Publication number
CN102142418A
CN102142418A CN2010101699299A CN201010169929A CN102142418A CN 102142418 A CN102142418 A CN 102142418A CN 2010101699299 A CN2010101699299 A CN 2010101699299A CN 201010169929 A CN201010169929 A CN 201010169929A CN 102142418 A CN102142418 A CN 102142418A
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layer
trunk portion
substrate
mask pattern
scolder
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CN102142418B (zh
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庄曜群
郭正铮
萧景文
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种半导体结构及半导体装置的制造方法，所述半导体结构具有T型立柱(post)。T型立柱具有底层凸块金属化(under bump metallization，UBM)部及延伸自UBM部的一柱体部。UBM部及柱体部可由相同或不同的材料所构成。在一实施例中，一基底，例如芯片、晶片、印刷电路板、封装基底等等，具有T型立柱且与另一基底(例如，芯片、晶片、印刷电路板、封装基底等等)的接触窗接合。T型立柱可具有一焊料预先形成于柱体部上，使柱体部露出来或使焊料覆盖柱体部。在另一实施例中，T型立柱可形成于一基底上，而焊料则形成于另一基底上。本发明能够维持半导体装置的结构完整性，防止在凸块电极/立柱与焊球/凸块之间的接垫区域内形成裂缝。

Description

半导体结构及半导体装置的制造方法
技术领域
本发明涉及一种半导体装置，尤其涉及一种用于半导体装置的导电立柱(post)。
背景技术
过去几十年来电子及半导体封装所呈现出的许多变化已影响了整个半导体工业。首先介绍的表面贴装技术(surface mount technology，SMT)及球栅阵列(ball grid array，BGA)对于广泛的各种集成电路(integrated circuit，IC)装置的高产率组件(high-throughput assembly)来说是重要的技术手段，且同时其能够容许缩短印刷电路板上接垫的间距。传统上，封装集成电路的结构中通过位于芯片上金属接垫与延伸至模制树脂封装体外侧的电极之间的微细金线作为基本的内连接。双列直插式封装(dual inline package，DIP)或四方扁平封装(quad flat package，QFP)为现今IC封装的基础结构。然而，增加封装体周围引脚总数的设计及排列通常造成引脚导线的间距过短，而在封装芯片的插件装配中产生许多限制。
芯片级封装(chip scale/size packing，CSP)或球栅阵列(BGA)封装为一些解决之法，其能够使电极排列紧密而无需大幅增加封装体的尺寸。一些CSP技术具有额外的好处，其能够进行芯片级的晶片封装。CSP的封装尺寸通常在芯片尺寸的1.2倍以内，其大幅缩小由CSP材料所制成的装置的尺寸。
一些CSP或BGA封装通过焊料凸块(bump)作为芯片上的接触点与基底(如，封装基板或印刷电路板(printed circuit board，PCB))上的接触点之间的电性连接。其他CSP或BGA封装利用将一焊球或凸块放置于凸块电极或立柱(post)上，通过焊点接合维持结构完整性。组成内连接的不同膜层通常具有不同的热膨胀系数(coefficient of thermal expansion，CTE)。如此一来，时常在凸块电极/立柱与焊球/凸块之间的接垫区域内形成裂缝。
发明内容
为了解决上述问题，本发明揭示一种具有T型立柱的半导体装置及其制造方法。T型立柱具有底层凸块金属化(UBM)部及延伸自UBM部的一柱体部。UBM部及柱体部可由相同或不同的材料所构成。在一实施例中，一具有T型立柱的第一基底与一第二基底的接触窗接合。举例而言，第一基底可为芯片、晶片、印刷电路板、封装基底等等，且第二基底可为芯片、晶片、印刷电路板、封装基底等等。T型立柱可具有一焊料预先形成于柱体部上，使柱体部露出来或使焊料覆盖柱体部。在另一实施例中，T型立柱可形成于一基底上，而焊料则形成于另一基底上。
本发明也揭示其他的实施例。
本发明还揭示一种半导体装置的制造方法，包括：
提供一第一基底，其具有一接触窗；
在该第一基底上方形成一钝化层，而露出至少一部分的该接触窗；
在该钝化层上方形成一第一掩模图案层，该第一掩模图案层具有一第一开口而露出至少一部分的该接触窗；
在该第一开口内形成一底层凸块金属化部；
在该第一掩模图案层上方形成一第二掩模图案层，该第二掩模图案层具有一第二开口而仅露出一部分的该底层凸块金属化部；
在该第二开口内形成一柱体部，该底层凸块金属化部及该柱体部形成一T型接触窗；以及
去除该第一掩模图案层及该第二掩模图案层。
本发明的半导体装置由于采用T型立柱，因而能够维持半导体装置的结构完整性，防止在凸块电极/立柱与焊球/凸块之间的接垫区域内形成裂缝。
附图说明
1示出根据一实施例的具有T型立柱的半导体装置。
图2示出根据一实施例的使用T型立柱将二基底接合在一起。
图3A至图3C图示出提供T型立柱及焊料的不同实施例。
图4至图9示出根据一实施例的形成T型立柱的方法。
图10至图12示出根据另一实施例的形成T型立柱的方法。
图13至图15示出根据又另一实施例的形成T型立柱的方法。
上述附图中的附图标记说明如下：
102～基底/第一基底；
104～T型立柱；
106～电路；
108～内层介电层；
110、114～接触窗；
112～金属层间介电层；
116～保护层；
118～导电层；
120～钝化层；
202～第二基底；
204～导电接触窗；
206～阻焊层；
208～底层凸块金属化部；
210～柱体部；
212～上表面；
216、1110、1410～焊料；
218～介金属化合物层；
410～晶种层；
510～第一掩模图案层；
710～第二掩模图案层；
1010、1310～第三掩模图案层；
W1、W2、W3～宽度。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
以下所述的实施例涉及具有T型立柱的凸块结构的使用。如下所述，实施例中采用上述结构以将一基底贴附于另一基底，其中每一基底可为芯片、晶片、印刷电路板、封装基板等等，而能够进行芯片对芯片、晶片对芯片、晶片对晶片、或晶片对印刷电路板或封装基底等等的贴附。以下所述的各个不同实施例中，相同的标号用于表示相同的部件。
请参照图1，其示出根据一实施例的一基底102的一部分具有多个T型立柱104形成于内。举例而言，基底102可包括硅块材基底、掺杂或未掺杂基底、或是绝缘层上覆硅(silicon on insulator，SOI)基底的一有源(active)层。一般来说，SOI基底包括一层半导体材料，例如硅，其形成于一绝缘层上。举例而言，绝缘层可为埋入式氧化(buried oxide，BOX)层或氧化硅层。绝缘层位于一基底上，其通常为硅基底或玻璃基底。同时也可使用其他的基底，例如多层式基底或渐变式基底。
形成于基底102上的电路106可为用于特定应用的任何类型电路。在一实施例中，电路106包括形成于基底102上的电子装置，基底106具有一层或多层的介电层位于电子装置上方。介电层之间可形成金属层，以进行电子装置之间电子信号的布线。电子装置也可形成于一层或多层介电层内。
举例而言，电路106可包括各种内连接的N型金属氧化物半导体(NMOS)及/或P型金属氧化物半导体(PMOS)装置，例如晶体管、电容、电阻、二极管、光电二极管、熔丝等等，用以执行一或多重功能。这些功能包括存储器结构、处理结构、传感器、放大器、电源分布、输入/输出电路等等。本领域普通技术人员可以了解的是上述因阐述目的所提供范例仅用于进一步解释某些实施例的应用，而非用于限定本发明。对于已知的应用来说，也可使用其他适用的电路。
在图1中也示出一内层介电(inter-layer dielectric，ILD)层108。举例而言，内层介电(ILD)层108包括了低介电常数(low-k)材料，例如磷硅玻璃(phosphosilicate glass，PSG)、硼磷硅玻璃(borophosphosilicate glass，BPSG)、氟硅玻璃(fluorinated silicate glass，FSG)、SiOxCy、旋涂玻璃(spin-on-glass)、旋涂高分子材料(spin-on-polymers)、碳化硅材料、其化合物、其复合材料、其组合物等等，其通过公知适当的方法制造而成，例如旋涂法、化学气相沉积(chemical vapor deposition，CVD)法、及等离子体辅助化学气相沉积(plasma-enhanced CVD，PECVD)法。需注意的是内层介电(ILD)层108可包括多介电层。
接触窗(contact)，例如接触窗110，形成且穿过内层介电层108内，以作为电路106的电性接触。举例而言，接触窗110的制作可先通过光刻技术在内层介电层108上沉积及图案化一光致抗蚀剂材料以露出用于形成接触窗110的内层介电层108部分。使用一蚀刻工艺，例如各向异性干蚀刻工艺，以在内层介电层108内形成开口。开口内可形成一扩散阻障衬层及/或一粘着层(未示出)并填入一导电材料。在一实施例中，扩散阻障衬层包括一或多层的TaN、Ta、TiN、Ti、CoW等等，且导电材料包括铜、钨、铝、银及其组合，借以形成图1所示的接触窗110。
一层或多层金属层间介电(inter-metal dielectric，IMD)层112及相关的金属化层(未示出)形成于内层介电层108上。一般来说，一层或多层金属层间介电层112及相关的金属化层用于电路106彼此的内连接且提供外部电路的电性连接。金属层间介电层112可由低介电常数材料所构成，例如由PECVD技术或高密度等离子体化学气相沉积(high-density plasma CVD，HDPCVD)等技术所形成的氟硅玻璃(FSG)且可包括中间蚀刻终止层。接触窗114形成于顶层金属层间介电层内，以提供外部电性连接。
需注意的是一或多层蚀刻终止层(未示出)可位于相邻的介电层(例如ILD层108及IMD层112)之间。一般来说，蚀刻终止层于形成介层窗(via)及/或接触窗时，提供一停止蚀刻工艺的机制。蚀刻终止层由介电材料所构成且与相邻的膜层(例如下方的半导体基底102、上方的ILD层108、及上方的IMD层112)之间具有不同的蚀刻选择比。在一实施例中，蚀刻终止层可由SiN、SiCN、SiCO、CN、其组合等等所构成，且通过CVD或PECVD等技术而形成。
在顶层IMD层112的表面上形成且图案化一保护层116，例如聚酰亚胺(polyimide)材料，以提供接触窗114一接触位置并保护下方的膜层而避免各种环境污染源。之后，在保护层116上形成且图案化一导电层118。导电层118提供上方用于外部连接的接触凸块的电性连接。导电层118已可作为引脚或球布局所需的重布局线层(redistribution layer，RDL)。导电层118可由任何适当的导电材料所构成，例如铜、钨、铝、银及其组合等等。
在导电层118上形成且图案化一钝化(passivation)层120，例如聚酰亚胺材料，且于钝化层120的开口上方形成T型立柱104，如图1所示。T型立柱104可由适当的导电材料所构成，例如Cu、Ni、Pt、Al、AlCu、W、CuSn、AuSn、InAu、PbSn等等，且与导电层118作电性接触。以下有更详细的说明。T型立柱104可通过沉积一种子层(未示出于图1中)并使用电镀技术来制作。
本领域普通技术人员将可以了解的是以上提供一般实施例的特征部件说明，然而实施例中也可具有其他众多的特征部件。例如，其他电路、衬层(liner)、阻障层、底层凸块金属化层等等。以上所述仅提供于此处所述的实施例背景且并未限定本说明或是这些特定实施例任何所要保护的范围。
请参照图2，其示出根据一实施例的T型立柱104连接于一第二基底202(例如封装基底、印刷电路板(PCB)、芯片、晶片等等)之后，其中相同的部件使用相同的标号。如图2所示，第二基底202包括一导电接触窗204。在第二基底202上形成且图案化一阻焊层(solder mask)206，例如一聚酰亚胺层，使导电接触窗204能形成电性连接。
为了便于探讨，T型立柱104包括一底层凸块金属化(under-bumpmetallization，UBM)部208及一柱体部210。在一实施例中，柱体部210的宽度W1与底层凸块金属化(UBM)部208的宽度W2的比率(W1/W2)约在0.2至0.75的范围。已发现的是具有上述比率的T型立柱在接合至第二基底202后提供了延展性焊料对于T型立柱的高模数材料(例如，Cu)的一适当比率。
在一实施例中，阻焊层206内的开口具有一宽度W3，其容许T型立柱104的柱体部210的宽度W1能够置入阻焊层206内的开口，使T型立柱104延伸过阻焊层206的上表面(如图2的虚线212所示)。在本实施例中，阻焊层206的宽度W3大于T型立柱104的宽度W1(W3＞W1)。
图2也示出焊料216及介金属化合物(inter-metallic compound，IMC)层218。在焊接期间，IMC自然地形成一膜层，例如IMC层218，其位于焊料216与相邻表面(例如，T型立柱104及/或导电接触窗204)之间的接点。IMC层218的存在表示焊料与相邻材料之间具有良好的焊接。在一实施例中，T型立柱104的柱体部210置入于阻焊层206的开口内，使IMC层218完全地占据柱体部210与第二基底202的导电接触窗204之间的空间。在此方式中，导电接触窗204、IMC层218、柱体部210、及UBM部208形成一H型连接体而容许大部分的电流经由IMC层218及柱体部210而通过UBM部208与导电接触窗204之间。在一实施例中，焊料216包括SnPb、高铅材料、锡基焊料、无铅焊料或其他适当的导电材料。
图3A至图3C示出不同的T型立柱104类型，其可使用于各种晶片形式以及将第一基底102贴附于第二基底202的准备程序中，第二基底202基底可为芯片、晶片、电路板、封装基板等等。请先参照图3A，T型立柱104并无焊料直接与其贴附。确切来说，在本实施例中，第二基底202具有焊料216而位于欲贴附的T型立柱104上。
在图3B中，焊料直接放置于第一基底102上方的T型立柱104上。在本实施例中，由于焊料已形成于T型立柱104上，且其在本实施例中穿过焊料216而显露出来，因此焊料216不需位于第二基底202上。
在图3C中，其示出相似于图3B的实施例。然而，在本实施例中，T型立柱104被焊料216所覆盖。
图4至图9示出形成图3A所示的T型立柱的中间步骤。首先请参照图4，提供具有各种膜层、结构、装置等等的基底102，如图1所示，其中相同部件使用相同的标号。可使用任何适当的工艺来形成上述结构，此处将不再做详细的说明。因此，所提供的基底102具有一钝化层120，其图案化后露出下方部分的导电层118。
之后，如图4所示，一顺应性晶种层410沉积于钝化层120的表面上。晶种层410为导电材料所构成的一薄层，其有助于在后续工艺步骤中形成较厚的膜层。在一实施例中，晶种层410可通过CVD或物理气相沉积(physicalvapor deposition，PVD)技术来沉积一薄导电层而形成，例如由Cu、Ti、Ta、TiN、TaN、其组合等等所构成的薄层。举例而言，通过PVD工艺沉积一Ti层而形成一阻障层以及通过PVD工艺沉积一Cu层而形成一晶种层。
之后，请参照图5，其示出根据一实施例的于晶种层410上方形成一第一掩模图案层510。第一掩模图案层510定义出T型立柱104(请参阅图2)的UBM部208的外型，如下所述。第一掩模图案层510可为光致抗蚀剂掩模图案层、硬掩模(hard mask)、其组合等等。
图6示出根据一实施例的形成T型立柱104的UBM部208。UBM部208可由任何适当的导电材料所构成，包括Cu、Ni、Pt、Al、其组合等等，且通过任何适当的技术而形成，例如PVD、CVD、电化学沉积(electrochemicaldeposition，ECD)、分子束外延(molecular beam epitaxy，MBE)、原子层沉积(atomic layer deposition，ALD)、电镀(electroplating)等等。需注意的是在一些实施例中，例如在晶片的整个表面上沉积(例如，PVD及CVD)一顺应性层，且也可进行蚀刻或平坦化工艺(例如，化学机械研磨(chemicalmechanical polishing，CMP))，以去除第一掩模图案层510表面上多余的导电材料。在一实施例中，UBM部208的厚度约在2微米(μm)至20微米的范围。
图7示出根据一实施例的于第一掩模图案层510上形成一第二掩模图案层710。第二掩模图案层710定义出T型立柱104(请参阅图2)的柱体部210的外型，如下所述。第二掩模图案层710可为光致抗蚀剂掩模图案层、硬式掩模、其组合等等。
之后，图8示出根据一实施例的T型立柱104的柱体部210。柱体部210可由任何适当的导电材料所构成，包括Cu、Ni、Pt、Al、其组合等等，且通过任何适当的技术而形成，例如PVD、CVD、ECD、MBE、ALD、电镀等等。在一些实施例中，柱体部210及UBM部208由相同的材料所构成，而在其他实施例中，柱体部210及UBM部208可由不同的材料所构成。需注意的是在一些实施例中，例如在晶片的整个表面上沉积(例如，PVD及CVD)一顺应性层，且也可进行蚀刻或平坦化工艺，以去除第二掩模图案层710表面上多余的导电材料。在一实施例中，柱体部210的厚度约在20微米至100微米的范围。
在形成T型立柱104之后，去除第一掩模图案层510及第二掩模图案层710，如图9所示。在第一掩模图案层510及第二掩模图案层710由光致抗蚀剂材料所构成的实施例中，光致抗蚀剂可通过化学溶液加以剥除，例如乳酸乙酯(ethyllactate)、甲氧苯(anisole)、甲基丁酯(methyl butyl acetate)、醋酸戊酯(amyl acetate)、甲基酚醛树脂(cresol novolak resin)、及重氮光活性化合物(diazo photoactive compound)的混合物(称作SPR9)，或使用其他剥除工艺。进行一清洁工艺，例如湿式浸渍于磷酸(H3PO4)与双氧水(H2O2)所构成的化学溶液(称作DPP)，以及1％氢氟(HF)酸，或进行其他清洁工艺，以去除露出的晶种层410部分以及钝化层120表面的任何污染物。
之后，可进行适合于特定应用的其他后段(back-end-of-line，BEOL)工艺技术。举例而言，可形成封胶(encapsulant)、进行切割(singulation)工艺以分开个别的芯片、进行晶片级或芯片级堆迭工艺等等。然而，需注意的是上述实施例可使用于不同的状态。举例而言，上述实施例可使用于芯片对芯片接合、芯片对晶片接合、晶片对晶片接合、芯片级封装、晶片级封装等等。
图10至图12示出形成图3B所示的T型立柱的中间步骤。图10至图12所示的实施例相似于图4至图9所示的实施例。因此，图10示出完成图9的工艺之后的后续步骤。
请参照图10，其示出根据一实施例的形成一第三掩模图案层1010。第三掩模图案层1010定义出欲放置于T型立柱104的柱体部210周围的焊料外型，如下所述。第三掩模图案层1010可为光致抗蚀剂掩模图案层、硬掩模、其组合等等。
之后，请参照图11，形成焊料1110。在一实施例中，焊料1110由通过电镀技术所形成的SnPb、高铅材料、锡基焊料、无铅焊料或其他适当的导电材料。可使用平坦化工艺，例如CMP，以去除位于柱体部210的一端的焊料，以露出柱体部210的一端，如图11所示。
在形成焊料1110之后，去除第三掩模图案层1010，如图12所示。在第三掩模图案层1010由光致抗蚀剂材料所构成的实施例中，光致抗蚀剂可通过化学溶液加以剥除，例如SPR9，或使用其他剥除工艺。进行一清洁工艺，例如湿式浸渍于DPP化学溶液，以及1％氢氟(HF)酸，或进行其他清洁工艺，以去除露出的晶种层410部分以及钝化层120表面的任何污染物。
之后，可进行适合于特定应用的其他后段(BEOL)工艺技术。举例而言，可形成封胶、进行切割工艺以分开个别的芯片、进行晶片级或芯片级堆叠工艺等等。然而，需注意的是上述实施例可使用于不同的状态。举例而言，上述实施例可使用于芯片对芯片接合、芯片对晶片接合、晶片对晶片接合、芯片级封装、晶片级封装等等。
图13至图15示出形成图3C所示的T型立柱的中间步骤。图13至图15所示的实施例相似于图4至图9所示的实施例。因此，图13示出完成图9的工艺之后的后续步骤。
请参照图13，其示出根据一实施例的形成一第三掩模图案层1310。第三掩模图案层1310定义出欲放置于T型立柱104的柱体部210周围的焊料外型，如下所述。第三掩模图案层1310可为光致抗蚀剂掩模图案层、硬掩模、其组合等等。在一实施例中，光致抗蚀剂材料沉积厚度约在50微米至100微米之间的范围，且通过光刻技术进行图案化。
之后，请参照图14，形成焊料1410。在一实施例中，焊料1410由通过电镀技术所形成的SnPb、高铅材料、锡基焊料、无铅焊料或其他适当的导电材料。
在形成焊料1410之后，去除第三掩模图案层1010，如图15所示。在第三掩模图案层1310由光致抗蚀剂材料所构成的实施例中，光致抗蚀剂可通过化学溶液加以剥除，例如SPR9，或使用其他剥除工艺。进行一清洁工艺，例如湿式浸渍于DPP化学溶液，以及1％氢氟(HF)酸，以去除露出的晶种层410部分以及钝化层120表面的任何污染物。
之后，可进行适合于特定应用的其他后段(BEOL)工艺技术。举例而言，可形成封胶、进行切割工艺以分开个别的芯片、进行晶片级或芯片级堆叠工艺等等。然而，需注意的是上述实施例可使用于不同的状态。举例而言，上述实施例可使用于芯片对芯片接合、芯片对晶片接合、晶片对晶片接合、芯片级封装、晶片级封装等等。
本领域普通技术人员可以了解的是相似的工艺可用于形成图3A至图3C所示的实施例。举例而言，可注意到图10的第三掩模图案层1010的厚度近似于T型立柱104的柱体部210的高度，而图13的第三掩模图案层1310的厚度却大于T型立柱104的柱体部210的高度。除此之外，图10至图12所示的工艺相似于图13至图15所示的工艺。厚度的差异说明了柱体部210上方焊料可具有不同厚度。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动、替代与润饰。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何本领域普通技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果都可使用于本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。另外，每一权利要求构成个别的实施例，且本发明的保护范围也包括各个权利要求及实施例的组合。

Claims (15)

1.一种半导体结构，包括：
一第一基底，包括一第一导电层；
一T型立柱，电性耦接至该第一导电层，该T型立柱具有一底层凸块金属化部与该第一导电层接触，且具有一柱体部延伸自该底层凸块金属化部，该底层凸块金属化部具有一第一宽度且该柱体部具有一第二宽度，该第一宽度大于该第二宽度；
一第二基底，具有一第二导电层；
一焊料，围绕该柱体部且与该第一导电层及该第二导电层作电性接触；以及
一介金属化合物层，位于该柱体部与该第二导电层之间，该介金属化合物层连续性地延伸至该第二导电层与该柱体部之间。
2.如权利要求1所述的半导体结构，其中该柱体部与该底层凸块金属化部由不同的材料所构成，且该第二宽度为该第一宽度的0.2至0.75倍。
3.如权利要求1所述的半导体结构，其中该第一基底与该第二基底的至少其中一个为一芯片或一晶片。
4.如权利要求1所述的半导体结构，其中该第二基底包括一阻焊层，而该柱体部延伸越过该阻焊层的一上表面。
5.一种半导体结构，包括：
一第一基底，包括一第一导电层以及一钝化层位于该第一导电层的至少一部分；以及
一T型立柱，位于该第一导电层上方，该T型立柱具有一底层凸块金属化部及一柱体部，该底层凸块金属化部位于该钝化层上方。
6.如权利要求5所述的半导体结构，还包括一焊料，其与该T型立柱接触，其中该焊料未覆盖该T型立柱的该柱体部的一端。
7.如权利要求5所述的半导体结构，还包括一焊料，其与该T型立柱接触，其中该焊料覆盖该T型立柱的该柱体部的一端。
8.如权利要求5所述的半导体结构，其中该柱体部与该底层凸块金属化部由不同的材料所构成，且该柱体部的一宽度为底层凸块金属化部的一宽度的0.2至0.75倍。
9.一种半导体装置的制造方法，包括：
提供一第一基底，其具有一接触窗；
在该第一基底上方形成一钝化层，而露出至少一部分的该接触窗；
在该钝化层上方形成一第一掩模图案层，该第一掩模图案层具有一第一开口而露出至少一部分的该接触窗；
在该第一开口内形成一底层凸块金属化部；
在该第一掩模图案层上方形成一第二掩模图案层，该第二掩模图案层具有一第二开口而仅露出一部分的该底层凸块金属化部；
在该第二开口内形成一柱体部，该底层凸块金属化部及该柱体部形成一T型接触窗；以及
去除该第一掩模图案层及该第二掩模图案层。
10.如权利要求9所述的半导体装置的制造方法，其中该柱体部的一宽度为底层凸块金属化部的一宽度的0.2至0.75倍。
11.如权利要求9所述的半导体装置的制造方法，还包括：
在该钝化层上方形成一第三掩模图案层，该第三掩模图案层具有一上表面切齐于该柱体部的一顶部，该第三掩模图案层露出该柱体部；
形成一焊料，其围绕该柱体部，而使该柱体部的该顶部露出来；以及
去除该第三掩模图案层。
12.如权利要求9所述的半导体装置的制造方法，还包括：
在该钝化层上方形成一第三掩模图案层，该第三掩模图案层具有一上表面高于该柱体部的一顶部，该第三掩模图案层露出该柱体部；
形成一焊料，其围绕该柱体部，而使该焊料覆盖该柱体部的该顶部；以及
去除该第三掩模图案层。
13.如权利要求9所述的半导体装置的制造方法，还包括：
提供一第二基底，其具有一导电接触窗及一阻焊层；以及
将该第一基底接合至该该第二基底，使该柱体部置入于该阻焊层的一开口内。
14.如权利要求13所述的半导体装置的制造方法，其中一介金属化合物层置于该柱体部与该导电接触窗之间，该介金属化合物层连续性地延伸自该导电接触窗及该柱体部。
15.如权利要求9所述的半导体装置的制造方法，还包括：
提供一第二基底，其具有一导电接触窗、一阻焊层、以及一焊料位于该阻焊层的一开口内；以及
将该第一基底接合至该该第二基底，使该柱体部置入于该阻焊层的该开口的该焊料中。
CN201010169929.9A 2010-01-29 2010-04-29 半导体结构及半导体装置的制造方法 Active CN102142418B (zh)

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