CN103109362B - 具有穿透衬底的通孔的集成电路 - Google Patents

具有穿透衬底的通孔的集成电路 Download PDF

Info

Publication number
CN103109362B
CN103109362B CN201180043062.5A CN201180043062A CN103109362B CN 103109362 B CN103109362 B CN 103109362B CN 201180043062 A CN201180043062 A CN 201180043062A CN 103109362 B CN103109362 B CN 103109362B
Authority
CN
China
Prior art keywords
tsv
metal layer
metal
protrusion
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180043062.5A
Other languages
English (en)
Other versions
CN103109362A (zh
Inventor
J·A·韦斯特
Y-J·朴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103109362A publication Critical patent/CN103109362A/zh
Application granted granted Critical
Publication of CN103109362B publication Critical patent/CN103109362B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/085—Material
    • H01L2224/08501—Material at the bonding interface
    • H01L2224/08503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种穿透衬底的通孔（TSV）芯片（200），其包括多个TSV（216），TSV（216）包括外部介电套管（221）和内部金属芯（220）以及凸出的TSV末端（217），凸出的TSV末端端部（217）包括从TSV管芯出现的侧壁。横向于凸出的TSV末端的钝化层（231）在凸出的TSV末端的侧壁的一部分上。在凸出的TSV末端的远侧部分缺少钝化层，从而提供内部金属芯的暴露部分。TSV末端包括球状远侧末端端部（217（a）），其包括第一金属层（241）和第二金属层（242），第一金属层（241）包括除焊料之外的第一金属，并且第二金属层（242）包括覆盖暴露末端部分的除焊料之外的第二金属。球状远侧末端端部覆盖TSV侧壁的一部分并在外部介电套管的最顶表面上方，并具有比在球状远侧末端端部下面的凸出的TSV末端的横截面积大≥25%的最大横截面积。

Description

具有穿透衬底的通孔的集成电路
技术领域
公开的实施例涉及包括TSV IC的集成电路（IC），该TSV IC包括凸出的TSV的末端。
背景技术
穿透衬底的通孔（TSV）是从在IC管芯的顶侧半导体表面上形成的导电层级中的一个（例如，接触层级或后段制程金属互连层级中的一个）延伸到其底侧表面从而延伸晶圆的整个厚度的垂直电连接。垂直电路径相对于常规引线结合技术显著缩短，一般导致显著更快的器件操作。在一种布置方式中，TSV作为凸出的TSV末端在IC管芯（这里称为“TSV管芯”）的一侧上终止，例如从TSV管芯的底侧表面凸出。TSV管芯可以面向上或面向下结合，并可以从两个侧面结合，从而使得能够形成堆叠IC器件。尽管TSV可以穿过任何衬底材料形成，但其统称为穿透硅通孔。
因为由于在TSV管芯上的面积约束和/或TSV在TSV管芯上的一个或更多层上施加的应力，因此TSV面积一般不可以增加，所以TSV面积经常受限制。对于涉及TSV末端的常规焊料间接接合，由于焊料具有相对低的电迁移（EM）电流限制（例如，常规焊料的通常EM限制电流密度是大约104A/cm2，是Cu或Al的大约百分之一），通过含TSV的接头的EM电流密度一般受在TSV末端和TSV末端上的覆盖焊料之间的分界面面积限制。
此外，应用于堆叠管芯组件，相对于在结合到TSV管芯的顶部IC管芯上的邻接结合垫或结合特征显著较小的TSV面积通常限制堆叠管芯组件的总体EM性能。对该EM问题的常规解决方案涉及通过添加另外的背侧金属步骤，或通过形成另外TSV（以提供并行的TSV），从而能够在TSV末端上方添加图案化金属垫，以减小TSV管芯上的已选择TSV中的电流。
发明内容
公开的示例实施例描述具有包括远侧末端端部的凸出的TSV末端的TSV管芯，在没有在TSV末端上方添加图案化金属垫的增加成本和生产周期或与包括另外的并行TSV关联的管芯面积损失的情况下，该远侧末端端部可以解决在上面描述的EM问题。本发明人也已认识到公开的实施例在焊料间接接合的情况下避免或至少显著延迟TSV的内部金属芯由于与覆盖的Sn基焊料一起形成金属间化合物（IMC）导致的消耗，这帮助防止外部介电套管的IMC引起的破裂，该破裂可以在TSV管芯上（尤其是凸出的TSV末端离开芯片底侧的点附近）导致故障（例如漏泄或短路）。
远侧末端端部包含第一金属层和第二金属层，该第一金属层包括覆盖凸出的TSV末端的暴露部分的除焊料之外的第一金属，并且该第二金属层包括不同于在第一金属层上的第一金属的除焊料之外的第二金属。第一金属层和第二金属层一起提供覆盖TSV的侧壁的一部分和外部介电套管的最顶表面的球状远侧末端端部，并且球状远侧末端端部提供比在球状远侧末端端部下面的凸出的TSV末端的横截面积大≥25%的横截面积。
一个公开的示例实施例是形成TSV管芯的方法，包括将除焊料之外的第一金属层镀覆在包含外部介电套管和内部金属芯的TSV的凸出的TSV末端的远侧部分上，并在第一金属层上镀覆不同于第一金属层的除焊料之外的第二金属层。第一金属层和第二金属层一起为凸出的TSV末端提供覆盖TSV的侧壁的一部分和外部介电套管的最顶表面的球状远侧末端端部，并且球状远侧末端端部提供比在球状远侧末端端部下面的凸出的TSV末端的横截面积大≥25%的横截面积。
该方法可以进一步包含在包括多个TSV管芯的晶圆的底侧表面上，包括在凸出的TSV末端上方淀积介电钝化层。然后可以蚀刻钝化层（例如，干蚀刻）从而显露包括TSV的内部金属芯暴露部分的凸出的TSV末端的远侧部分。球状远侧末端端部可以然后在凸出的TSV末端的远侧部分上形成。球状远侧末端端部的形成可以包含选择性无电镀覆第一和第二金属层。
附图说明
图1A是根据本发明的实施例示出在形成TSV管芯的示范方法中的步骤的流程图。
图1B是根据本发明的另一实施例示出在形成TSV管芯的示范方法中的步骤的流程图。
图2A是根据本发明的实施例的TSV管芯的简化横截图示，该TSV管芯包含具有球状远侧末端端部的TSV。
图2B是根据本发明的另一实施例的TSV管芯的简化横截图示，该TSV管芯包含具有球状远侧末端端部的TSV。
图3是根据本发明的另一实施例的涉及在图2A中示出的实施例的TSV管芯的简化横截图示，该TSV管芯包含具有球状远侧末端端部的TSV，该TSV管芯经修改以便外部介电TSV套管沿凸出的TSV末端的侧壁延伸小于凸出的TSV末端的长度的距离。
图4是根据本发明的实施例的包含TSV管芯和第二IC管芯的堆叠IC器件的简化横截图示，该TSV管芯包含具有球状远侧TSV末端端部的TSV，并且该第二IC管芯具有多个凸出结合特征，其中示出凸出结合特征在回流焊料接头处接合到凸出的TSV末端。
具体实施方式
图1A是根据本发明的实施例示出在形成TSV管芯的示范方法100中的步骤的流程图。步骤101包含提供包含多个TSV管芯的晶圆。TSV管芯包括至少一个，并且一般包括多个TSV，该TSV包含内部金属芯和外部介电套管，该外部介电套管延伸芯片的全部厚度，从顶侧半导体表面（一般耦合到接触层级或BEOL金属层（例如M1、M2等）中的一个）延伸到从TSV管芯的底侧表面出现的凸出的TSV末端。在一个实施例中内部金属芯可以包含Cu。其他导电材料可以用于内部金属芯。在一个实施例中TSV直径≤12μm，例如在一个特别实施例中的8.5到10μm。
外部介电套管可以包含如下材料：例如氧化硅、氮化硅、掺磷硅酸盐玻璃（PSG）、氮氧化硅或某些CVD聚合物（例如聚对二甲苯）。外部介电套管通常是0.2到5μm厚。在内部金属芯为铜和某些其他材料的情况下，一般添加在此称为“TSV阻挡层”的金属扩散阻挡层，例如耐熔金属或耐熔金属氮化物。例如，TSV阻挡层材料可以包括如下材料：包括Ta、W、Mo、Ti、TiW、TiN、TaN、WN、TiSiN或TaSiN，该材料可以由物理汽相淀积（PVD）或化学汽相淀积（CVD）来淀积。TSV阻挡层通常是100–500A厚。TSV末端的远侧部分包括暴露（即无介电套管的）区，该暴露区至少部分暴露内部金属芯的最顶表面从而允许连接至其的电接触。
步骤102包含在凸出的TSV末端的远侧部分上镀覆除焊料之外的第一金属层。第一金属层形成与至少内部金属芯的最顶表面的电接触。第一金属层一般1到4μm厚。第一金属层提供IMC阻挡和电流扩散器功能。第一金属层可以包含如下材料：包括例如Ni、Pd、Co、Cr、Rh、NiP、NiB、CoWP或CoP。镀覆可以包含无电镀覆。如在镀覆的领域中已知，无电镀覆是仅在某些暴露金属或半导体表面上淀积，不在电介质例如聚合物、氧化物和氮化物上淀积的选择性淀积工艺，并因此不涉及生成图案的光刻或移除过多淀积材料的蚀刻步骤。在另一实施例中，可以通过以下方式来使用电镀：使用光刻建立图案化层，以便可以在TSV末端上方形成电镀垫，从而使用电镀工艺将淀积定位到末端区。
步骤103包含在第一金属层上镀覆不同于第一金属层的除焊料之外的第二金属层。镀覆可以包含无电镀覆。与在上面描述的步骤102相同，镀覆可以包含电镀。第一金属层与第二金属层一起为凸出的TSV末端提供球状远侧末端端部。球状远侧末端端部覆盖TSV侧壁的一部分和外部介电套管的最顶表面，并提供比在球状远侧末端端部下面的凸出的TSV末端的横截面积大≥25%的最大横截面积。在另一实施例中，球状远侧末端端部具有比在球状远侧末端端部下面的凸出的TSV末端的横截面积大≥40%的最大横截面积。例如，TSV末端直径可以是6到10μm，并且第一和第二金属层的组合厚度可以是1到5μm厚。
对于在本领域中已知由在某些金属（例如Cu）或半导体表面上开始的各向同性淀积图案来表征的无电工艺，在垂直于TSV末端的长度方向的尺寸中的淀积厚度通常是TSV末端的长度尺寸中淀积厚度的70%到85%。因此，4μm厚的淀积厚度提供约6μm的TSV宽度尺寸的增加。
在第一特别实施例中，第一金属层包含Ni并且第二金属层包含Cu、Pt、Pd或Au。例如，Ni可以是1到4μm厚，并且第二金属层可以包含2到5μm厚的Cu。Ni提供IMC阻挡，同时实施为Cu层的第二金属有助于焊料随后转换成CuxSnyIMC，并在第一金属层中延迟Ni完全转换成IMC，由此扩展EM能力。
通过形成球状末端端部，有效末端面积显著增加，这降低在TSV末端和焊料之间分界面的电流密度。此外，球状末端端部阻挡/延迟IMC形成反应进入TSV末端。球状远侧末端也延缓TSV内部金属芯（例如Cu）由于与覆盖的Sn基焊料一起形成IMC而消耗。
在第二特别实施例中，第一金属层包含Ni并且第二金属层包含Pd。在该第二特别实施例中，Pd可以是0.2到0.6μm厚。在第二特别实施例中，浸没Au层可以淀积在Pd或其他第二金属层上从而改善焊料浸湿。Au层可以是200到500A厚。Pd可以提供阻挡从而防止Au扩散通过直到PSV末端，并可以提供阻挡从而防止P（例如源自下面的NiP）腐蚀Au。
图1B是根据本发明的另一实施例示出在形成TSV芯片的示范方法150中的步骤的流程图。步骤151包含提供晶圆，该晶圆包含多个TSV管芯，其中每个TSV管芯都具有包括有源电路的顶侧半导体表面和底侧表面，以及多个TSV。TSV包含内部金属芯和外部介电套管，该外部介电套管延伸管芯的整个厚度，从顶侧半导体表面（一般耦合到接触层级或BEOL金属层（例如M1、M2等）中的一个）延伸到从TSV管芯的底侧表面出现的凸出的TSV末端。TSV末端包括侧壁。
步骤152包含在晶圆的底侧表面上，包括在凸出的TSV上方淀积介电钝化层。在一个实施例中，使用旋涂工艺淀积钝化层。然而，可以使用其他淀积工艺。
步骤153包含蚀刻钝化层从而显露凸出的TSV末端的远侧部分，该蚀刻包括暴露内部金属芯的一部分，其中在蚀刻之后钝化层继续覆盖晶圆的横向于凸出的TSV的底侧表面和一部分侧壁。干蚀刻可以用于该步骤。一些湿蚀刻工艺也可以是合适的。例如，一种示范湿蚀刻工艺用密封TSV末端的介电聚合物涂覆TSV末端，并然后使用溶剂将介电聚合物的一部分从TSV末端移除，从而暴露TSV末端的远侧部分以容许至其的电连接。
在一个实施例中步骤152可以包含介电钝化层的化学汽相淀积（CVD），该介电钝化层包含氮化硅或氮氧化硅，并且步骤153可以包含化学机械抛光（CMP）从而显露凸出的TSV末端的远侧部分，包括暴露内部金属芯的一部分。在该实施例中金属镀覆（在下面描述的步骤154、155）跨该钝化层横向生长。
步骤154类似于在方法100中的步骤102，并包含在TSV的凸出的TSV末端的远侧部分上镀覆除焊料之外的第一金属层。该镀覆可以包含无电镀覆。步骤155类似于在方法100中的步骤103，并包含在第一金属层上镀覆不同于第一金属层的除焊料之外的第二金属层。镀覆可以包含无电镀覆。第一金属层与第二金属层一起为凸出的TSV末端提供球状远侧末端端部。球状远侧末端端部覆盖TSV侧壁的一部分和外部介电套管的最顶表面，并具有比在球状远侧末端端部下面的凸出的TSV末端的横截面积大≥25%的最大横截面积。
图2A是根据本发明的实施例的TSV管芯200的简化横截图示，TSV管芯200包含具有凸出的TSV末端217的至少一个TSV216，凸出的TSV末端217具有球状远侧末端端部217（a）。TSV管芯200包含衬底205，衬底205包括顶侧半导体表面207和底侧表面210，顶侧半导体表面207包括有源电路209。示出的连接器208描绘在顶侧半导体表面207上的TSV216到有源电路209之间的耦合。TSV216包含外部介电套管221和内部金属芯220，以及在外部介电套管221和内部金属芯220之间的TSV阻挡层222。TSV216从顶侧半导体表面207延伸到从底侧表面210出现的凸出的TSV末端217。TSV末端包括在其上具有外部介电套管221和阻挡层222的侧壁。
介电钝化层231横向于凸出的TSV末端217，包括在凸出的TSV末端217的侧壁的一部分上。凸出的TSV末端217的远侧部分缺少介电钝化层231从而提供内部金属芯220的暴露部分。
包括除焊料之外的第一金属的第一金属层覆盖凸出的TSV末端217的暴露部分。第二金属层242包括除焊料之外的第二金属，其与第一金属层241上的第一金属不同。可见第一金属层241与第二金属层242一起为凸出的TSV末端217提供球状远侧末端端部217（a），其覆盖TSV侧壁的一部分和外部介电套管221的最顶表面221（a），并且其提供大于在球状远侧末端端部217（a）下面的凸出的TSV末端217的横截面积≥25%的横截面积。
在组装、可靠性测试期间以及在使用期间，当TSV缺少充当IMC阻挡层的金属盖时，在常规TSV接头中使用的焊料将从TSV末端消耗内部金属芯（例如Cu），这可以导致TSV内部芯金属例如Cu转换成IMC。本发明人已认识到IMC形成引起体积增加，这可以使周围外部介电套管221（尤其是凸出的TSV末端217离开衬底205的底侧表面210的点附近）破裂。在此披露的球状末端端部217（a）除了减小在TSV末端与焊料的分界面的电流密度之外，还如上所述阻止/延迟IMC形成反应进入TSV末端。球状末端也延缓TSV内部金属芯（例如Cu）由于与覆盖的Sn基焊料一起形成IMC而被消耗。在下面描述的图4示出示范焊点，该示范焊点将具有从TSV管芯的底侧表面凸出的球状末端端部的TSV末端与具有多个凸出结合特征的第二IC管芯耦合。
图2B是根据本发明的另一实施例的TSV管芯250的简化横截图示，TSV管芯250包含具有球状远侧末端端部的至少一个TSV。在图2B中示出的球状末端端部217（b）包含可选的第三金属层243、第二金属层242和第一金属层241。在该实施例中，第一金属层241可以包含Ni（例如1到4μm厚），第二金属层242可以包含Pd（例如0.2到0.6μm厚），并且第三金属层243可以包含Au（例如200到500A厚）。如上面提到，Pd可以阻挡可能的Au扩散，并也可以阻挡源自下面的NiP的P对Au的可能腐蚀。
图3是涉及在图2A中示出的实施例的TSV管芯300的简化横截图示，TSV管芯300包含具有球状远侧末端端部217（a）的TSV216，TSV管芯300经修改使得外部介电TSV套管221沿凸出的TSV末端217的侧壁延伸小于凸出的TSV末端217的长度的距离。在此称为中间距离（Di）的该距离可以是：
凸出的TSV末端的长度的1/3≤Di≤凸出的TSV末端的长度-1μm。
用于形成具有沿凸出的TSV末端217的侧壁延伸小于凸出的TSV末端217的长度的距离的外部介电TSV套管221的此类TSV末端的方法在授予Bonifield等人的共同受让的公开美国专利申请No.20090278238能够找到。
图4是包含第一TSV管芯200（如上面描述在图2A中示出）和第二IC管芯420的堆叠IC器件的简化横截图示，第一TSV管芯200包含具有球状远TSV末端端部217（a）的TSV216，并且第二IC管芯420具有多个凸出结合特征，其中示出在结合垫422上的单个结合特征（例如铜垫）425在回流焊料（例如，电解SnAg2.5wt.%焊料）接头435处接合到TSV管芯200的球状末端端部217（a）。IMC426（例如CuxSny）在结合特征425上示出，其获得自焊料回流工艺。
在图2B中示出的第三金属层243没有在图4中示出，因为其一般在焊料回流期间完全分解并因此完全扩散进入焊料从而被包括在回流焊料接头435中。另外，另一IMC层426’在焊料接头435中的焊料和第二金属层242（例如Ni第二金属层）之间形成。在第二金属层包含Ni的情况下，由于与Ni和Sn之间的IMC形成速率相比，当其是Cu和Sn时，IMC在结合垫425之间以更快的速率形成，因此IMC层426’将比IMC层426薄得多。
图4也示出公开的球状末端端部怎样通过显著增加TSV末端217的远侧部的有效面积，解决因为TSV末端与邻接垫425相比的（相对）较小横截面积（例如直径）上的EM限制，所以必须在晶圆背侧上的TSV末端上方建立图案化金属垫，或添加额外的TSV从而向下一层供应充足电流的问题。
在顶侧半导体表面上形成的有源电路包含电路元件，该电路元件一般包括晶体管、二极管、电容器和电阻器，以及将这些各种电路元件互连的信号线和其他电导体。公开的实施例可以集成各种工艺流程从而形成各种器件和相关产品。半导体衬底可以包括在其中的各种元件和/或其上的各种层。这些可以包括阻挡层、其他介电层、器件结构，包括源极区、漏极区、位线、基极、发射极、集电极、导线、导电通孔等的有源元件和无源元件。此外，公开的实施例可以在包括双极型、CMOS、BiCMOS和MEMS的各种工艺中使用。
本发明涉及领域的技术人员认识到可以对已描述示例实施例和在要求保护的发明的范围内实施的其他实施例做出修改。

Claims (6)

1.一种形成穿透硅通孔管芯即TSV管芯的方法，包含：
在TSV的凸出的TSV末端的远侧端部上镀覆除焊料之外的第一金属层，所述TSV穿透衬底，所述衬底上形成有钝化层，所述凸出的TSV末端从所述衬底凸出并且穿过所述钝化层，所述凸出的TSV末端包括内部金属芯、外部介电套管和阻挡层，所述阻挡层被设置在所述内部金属芯的侧壁上使得所述阻挡层被设置在所述内部金属芯和所述外部介电套管之间，其中所述阻挡层沿着所述内部金属芯的外表面延伸到所述凸出的TSV末端的所述远侧端部但没有覆盖所述远侧端部处的所述内部金属芯的最顶表面，其中所述外部介电套管沿着所述阻挡层的外表面延伸但留下与未被所述外部介电套管覆盖的所述远侧端部相邻的所述阻挡层的一部分，其中所述第一金属层覆盖所述阻挡层的所述未被覆盖的部分的第一部分但没有覆盖所述外部介电套管的任何部分；以及
在所述第一金属层上镀覆不同于所述第一金属层的除焊料之外的第二金属层，所述第二金属层覆盖所述阻挡层的所述未被覆盖的部分的第二部分但没有覆盖所述外部介电套管的任何部分；以及
在所述第二金属层上镀覆不同于所述第一金属层和所述第二金属层的除焊料之外的第三金属层以在所述凸出的TSV末端上形成球状远侧末端端部，其中所述第三金属层覆盖所述阻挡层的所述未被覆盖的部分的第三部分但没有覆盖所述外部介电套管的任何部分；
其中所述阻挡层的所述未被覆盖的部分的所述第一部分、所述第二部分和所述第三部分不同并且构成所述阻挡层的整个未被覆盖的部分，使得在镀覆所述第一金属层、所述第二金属层和所述第三金属层之后，所述未被覆盖的部分中没有部分被暴露；并且
其中所述阻挡层包括难熔金属或难熔金属氮化物；
其中从所述衬底凸出的所述外部介电套管由所述钝化层完全覆盖使得从所述衬底凸出的所述外部介电套管中没有部分被暴露。
2.根据权利要求1所述的方法，其中所述镀覆所述第一金属层和所述镀覆所述第二金属层都包含选择性无电镀覆，并且其中所述球状远侧末端端部在所述凸出的TSV末端的所述远侧部分上选择性形成。
3.根据权利要求1所述的方法，其中所述第一金属层包含从Ni、Pd、Co、Cr、Rh、NiP、NiB、CoWP和CoP组成的组中选择的第一金属。
4.根据权利要求1所述的方法，其中所述第一金属层包含Ni，并且第二金属层包含Cu。
5.根据权利要求1所述的方法，其中所述球状远侧末端端部具有比在所述球状远侧末端端部下面的所述凸出的TSV末端的第二横截面积大25％的第一横截面积。
6.根据权利要求1所述的方法，其中所述球状远侧末端端部具有比在所述球状远侧末端端部下面的所述凸出的TSV末端的第二横截面积大40％的第一横截面积。
CN201180043062.5A 2010-09-13 2011-09-13 具有穿透衬底的通孔的集成电路 Active CN103109362B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/880,629 US8039385B1 (en) 2010-09-13 2010-09-13 IC devices having TSVS including protruding tips having IMC blocking tip ends
US12/880,629 2010-09-13
PCT/US2011/051419 WO2012037140A2 (en) 2010-09-13 2011-09-13 Integrated circuits with through-substrate vias

Publications (2)

Publication Number Publication Date
CN103109362A CN103109362A (zh) 2013-05-15
CN103109362B true CN103109362B (zh) 2019-08-16

Family

ID=44773319

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180043062.5A Active CN103109362B (zh) 2010-09-13 2011-09-13 具有穿透衬底的通孔的集成电路

Country Status (4)

Country Link
US (2) US8039385B1 (zh)
JP (1) JP6073790B2 (zh)
CN (1) CN103109362B (zh)
WO (1) WO2012037140A2 (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
KR20130053338A (ko) * 2011-11-15 2013-05-23 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자
US9129943B1 (en) * 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US20130313710A1 (en) * 2012-05-22 2013-11-28 Micron Technology, Inc. Semiconductor Constructions and Methods of Forming Semiconductor Constructions
US8709936B2 (en) * 2012-07-31 2014-04-29 International Business Machines Corporation Method and structure of forming backside through silicon via connections
KR101972969B1 (ko) * 2012-08-20 2019-04-29 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
CN202816916U (zh) * 2012-10-10 2013-03-20 矽力杰半导体技术(杭州)有限公司 一种倒装封装装置
US9034752B2 (en) 2013-01-03 2015-05-19 Micron Technology, Inc. Methods of exposing conductive vias of semiconductor devices and associated structures
US9059111B2 (en) 2013-04-11 2015-06-16 International Business Machines Corporation Reliable back-side-metal structure
US9171782B2 (en) * 2013-08-06 2015-10-27 Qualcomm Incorporated Stacked redistribution layers on die
US9281274B1 (en) 2013-09-27 2016-03-08 Stats Chippac Ltd. Integrated circuit through-substrate via system with a buffer layer and method of manufacture thereof
US9318414B2 (en) 2013-10-29 2016-04-19 Globalfoundries Inc. Integrated circuit structure with through-semiconductor via
US9318413B2 (en) 2013-10-29 2016-04-19 Globalfoundries Inc. Integrated circuit structure with metal cap and methods of fabrication
KR20150109213A (ko) * 2014-03-19 2015-10-01 에스케이하이닉스 주식회사 관통 전극을 갖는 반도체 소자 및 그 제조방법
US10163705B2 (en) * 2014-04-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Profile of through via protrusion in 3DIC interconnect
KR102320821B1 (ko) 2014-09-11 2021-11-02 삼성전자주식회사 반도체 패키지
DE102014115105B4 (de) 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
CN104733398A (zh) * 2015-03-31 2015-06-24 武汉新芯集成电路制造有限公司 一种晶圆三维集成引线工艺
US9472490B1 (en) 2015-08-12 2016-10-18 GlobalFoundries, Inc. IC structure with recessed solder bump area and methods of forming same
US9780052B2 (en) * 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
US10418311B2 (en) * 2017-03-28 2019-09-17 Micron Technology, Inc. Method of forming vias using silicon on insulator substrate
CN107910327B (zh) * 2017-11-07 2024-05-14 长鑫存储技术有限公司 电容器阵列结构及其制造方法
US10957625B2 (en) 2017-12-29 2021-03-23 Micron Technology, Inc. Pillar-last methods for forming semiconductor devices
KR20220090793A (ko) 2020-12-23 2022-06-30 삼성전자주식회사 반도체 패키지
US20230005869A1 (en) * 2021-07-05 2023-01-05 Changxin Memory Technologies, Inc. Micro bump, method for forming micro bump, chip interconnection structure and chip interconnection method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4059063B2 (ja) * 2002-11-11 2008-03-12 株式会社村田製作所 セラミック多層基板およびその製造方法
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4800585B2 (ja) * 2004-03-30 2011-10-26 ルネサスエレクトロニクス株式会社 貫通電極の製造方法、シリコンスペーサーの製造方法
JP5222459B2 (ja) * 2005-10-18 2013-06-26 新光電気工業株式会社 半導体チップの製造方法、マルチチップパッケージ
US8154134B2 (en) 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
JP2009277719A (ja) * 2008-05-12 2009-11-26 Nec Electronics Corp 半導体装置及びその製造方法
US7833895B2 (en) 2008-05-12 2010-11-16 Texas Instruments Incorporated TSVS having chemically exposed TSV tips for integrated circuit devices
US8183673B2 (en) * 2008-10-21 2012-05-22 Samsung Electronics Co., Ltd. Through-silicon via structures providing reduced solder spreading and methods of fabricating the same
KR101553560B1 (ko) * 2008-11-26 2015-09-16 삼성전자주식회사 적층 패키지 및 이의 제조 방법
US8097953B2 (en) * 2008-10-28 2012-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit stacking-joint interface structure

Also Published As

Publication number Publication date
WO2012037140A3 (en) 2012-05-31
US8299612B2 (en) 2012-10-30
CN103109362A (zh) 2013-05-15
WO2012037140A2 (en) 2012-03-22
US8039385B1 (en) 2011-10-18
JP6073790B2 (ja) 2017-02-01
US20120235296A1 (en) 2012-09-20
JP2013538466A (ja) 2013-10-10

Similar Documents

Publication Publication Date Title
CN103109362B (zh) 具有穿透衬底的通孔的集成电路
CN105280611B (zh) 3dic互连器件及其形成方法
CN101719484B (zh) 具有再分布线的tsv的背连接
CN106469701B (zh) 半导体器件结构及其形成方法
JP5271985B2 (ja) 集積回路構造
JP3771905B2 (ja) 入出力サイトのための共通ボール制限金属
TWI544597B (zh) 積體電路元件以及半導體製程
US20140061920A1 (en) Semiconductor device
KR20000028654A (ko) 알루미늄 콘택트 형성 방법 및 집적 회로 구조체
TW201023330A (en) Integrated circuit
CN105655320B (zh) 低成本芯片背部硅通孔互连结构及其制备方法
JP5627835B2 (ja) 半導体装置および半導体装置の製造方法
US7279720B2 (en) Large bumps for optical flip chips
JP2013506999A (ja) 銅プラグを有する半導体デバイスおよびデバイスを形成するための方法
US9324611B2 (en) Corrosion resistant via connections in semiconductor substrates and methods of making same
JP5248627B2 (ja) 半導体のマイクロパッド形成方法
CN107039394B (zh) 半导体结构及其制造方法
CN104064550B (zh) 半导体器件及其制造方法
JP2007221080A (ja) 半導体装置およびその製造方法
US20040201101A1 (en) Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures
US20080067681A1 (en) Interconnection structure and manufacturing method thereof
JP5891211B2 (ja) 半導体装置
CN110010576A (zh) 具凸块结构的半导体装置及其制造方法
US11031361B2 (en) Semiconductor bonding structure and method of manufacturing the same
JPH08153690A (ja) 半導体装置、半導体装置の製造方法、及び配線形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant