JP6456232B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6456232B2 JP6456232B2 JP2015092604A JP2015092604A JP6456232B2 JP 6456232 B2 JP6456232 B2 JP 6456232B2 JP 2015092604 A JP2015092604 A JP 2015092604A JP 2015092604 A JP2015092604 A JP 2015092604A JP 6456232 B2 JP6456232 B2 JP 6456232B2
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- film
- electrode
- semiconductor device
- plating film
- solder ball
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Description
<半導体装置の構造>
図1は、本実施の形態における半導体装置SAの上面図である。図1に示すように、本実施の形態における半導体装置SAは、矩形形状の配線基板WBを有し、この配線基板WBの中央部に封止材(アンダーフィル)UFを介して、矩形形状の半導体チップCHPが搭載されている。図1に示すように、半導体チップCHPのサイズは、配線基板WBのサイズよりも小さくなっている。例えば、配線基板WBの1辺の長さは、8mm〜15mmm程度であり、その厚さは、0.2mm〜0.6mm程度である。一方、半導体チップCHPの1辺の長さは、3mm〜12mm程度であり、その厚さは、0.05mm〜0.7mm程度である。
本実施の形態における半導体装置は、上記のように構成されており、以下に、その製造方法について、図面を参照しながら説明する。
次に、上記実施の形態の変形例について説明する。図14は、図12のバンプ電極の変形例1を示す要部断面図である。図15は、変形例1の半導体装置の製造工程中の要部断面図である。
次に、上記実施の形態の変形例について説明する。図16および図17は、変形例2の半導体装置の製造工程中の要部断面図である。
〔付記1〕
(a)その主面上にパッド電極を有する半導体基板を準備する工程、
(b)前記半導体基板の主面上に、前記パッド電極の一部を露出する第1開口を有する第1絶縁膜を形成する工程、
(c)前記パッド電極上および前記第1絶縁膜上に第1金属膜を堆積する工程、
(d)前記第1金属膜上に、前記第1金属膜の一部を露出する第2開口を有する第2絶縁膜を形成する工程、
(e)前記第2開口内の前記第1金属膜上に第1メッキ膜を形成する工程、
(f)前記第1メッキ膜上に第2メッキ膜を形成する工程、
(g)前記第2絶縁膜を除去する工程、
(h)前記第1メッキ膜にエッチング処理を施し、前記第2メッキ膜に張出部を形成する工程、
(i)前記第2メッキ膜上に、半田ボールを配置する工程、
(j)前記半田ボールを溶融し、前記第2メッキ膜の上面全体に濡れ広がった半田ボール電極を形成する工程、
を有し、
前記第2メッキ膜の上面は、前記第2絶縁膜の上面に等しいか、または、前記第2絶縁膜の上面よりも低い、半導体装置の製造方法。
〔付記2〕
付記1に記載の半導体装置の製造方法において、
前記第1メッキ膜は、銅膜、前記第2メッキ膜は、ニッケル膜からなる、半導体装置の製造方法。
〔付記3〕
付記2に記載の半導体装置の製造方法において、
前記エッチング処理は、前記第1メッキ膜および前記第2メッキ膜の表面を、アンモニア過水で処理した後に、硫酸過水で第1メッキ膜を選択的にエッチングする、半導体装置の製造方法。
10 表面保護膜
11 保護膜
12 シード膜
13、13c レジスト膜
14、14a、14b 第1メッキ膜
15、15a、15b 第2メッキ膜
16、16b 半田ボール電極
16a 半田ボール
17 プレ半田
BE、BE2 バンプ電極
CHP 半導体チップ
CL コア層
CV 凹部
LND ランド
OH 張出部
PA パッド電極
PE、PE2 ポスト電極
SA 半導体装置
SB 基板用半田ボール
SR1、SR2 ソルダレジスト膜
ST 幹部
TA 端子
UF 封止材(アンダーフィル)
WL1、WL2、WL3 配線
Claims (8)
- (a)その主面上にパッド電極を有する半導体基板を準備する工程、
(b)前記半導体基板の主面上に、前記パッド電極の一部を露出する第1開口を有する第1絶縁膜を形成する工程、
(c)前記パッド電極上および前記第1絶縁膜上に第1金属膜を堆積する工程、
(d)前記第1金属膜上に、前記第1金属膜の一部を露出する第2開口を有する第2絶縁膜を形成する工程、
(e)前記第1金属膜上に第1メッキ膜を形成し、前記第2開口内に位置する幹部と、前記第2開口周囲の前記第2絶縁膜上に位置する張出部と、を有するポスト電極を形成する工程、
(f)前記第2絶縁膜を除去する工程、
(g)前記ポスト電極上に、半田ボールを配置する工程、
(h)前記半田ボールを溶融し、前記幹部および前記張出部の上面に濡れ広がった半田ボール電極を形成する工程、
を有し、
前記(h)工程において、前記幹部は、側壁を有し、前記半田ボール電極は、前記幹部と前記張出部の上面にのみ形成され、前記幹部の前記側壁は、前記半田ボール電極から露出している、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記張出部の、前記側壁からの突出幅は、2μm以上かつ10μm以下である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記半田ボールは、錫、金および銅を含む半田材からなる、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(e)工程は、さらに、
(i)前記第1メッキ膜の表面上に第2メッキ膜を形成する工程、
を有し、
前記第1メッキ膜は、銅膜からなり、前記第2メッキ膜は、ニッケル膜からなる、半導体装置の製造方法。 - (a)その主面上にパッド電極を有する半導体基板を準備する工程、
(b)前記半導体基板の主面上に、前記パッド電極の一部を露出する第1開口を有する第1絶縁膜を形成する工程、
(c)前記パッド電極上および前記第1絶縁膜上に第1金属膜を堆積する工程、
(d)前記第1金属膜上に、前記第1金属膜の一部を露出する第2開口を有する第2絶縁膜を形成する工程、
(e)前記第2開口内の前記第1金属膜上に第1メッキ膜を形成する工程、
(f)前記第1メッキ膜上に第2メッキ膜を形成してポスト電極を形成する工程、
(g)前記第2絶縁膜を除去する工程、
(h)前記第2メッキ膜上に、半田ボールを配置する工程、
(i)前記半田ボールを溶融し、前記第2メッキ膜の上面全体に濡れ広がった半田ボール電極を形成する工程、
を有し、
前記(e)工程において、前記第1メッキ膜の上面は、前記第2絶縁膜の上面よりも低く、
前記(f)工程において、
前記第2メッキ膜は、前記第1メッキ膜の上面上、および、前記第2開口周囲の前記第2絶縁膜上に形成され、
前記ポスト電極は、前記第1メッキ膜と前記第2メッキ膜との積層構造からなる幹部と、前記第2メッキ膜からなる張出部と、を含み、
前記(i)工程において、前記幹部は、側壁を有し、前記半田ボール電極は、前記幹部と前記張出部の上面にのみ形成され、前記幹部の前記側壁は、前記半田ボール電極から露出している、半導体装置の製造方法。 - 請求項5に記載の半導体装置の製造方法において、
前記張出部の、前記側壁からの突出量は、2μm以上かつ10μm以下である、半導体装置の製造方法。 - 請求項5に記載の半導体装置の製造方法において、
さらに、
(j)前記第2メッキ膜の表面上に第3メッキ膜を形成する工程、
を有する、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記第1メッキ膜は、銅膜からなり、前記第2メッキ膜は、ニッケル膜からなり、前記第3メッキ膜は、金膜からなる、半導体装置の製造方法。
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