CN109524408A - 半导体存储器 - Google Patents
半导体存储器 Download PDFInfo
- Publication number
- CN109524408A CN109524408A CN201811092138.3A CN201811092138A CN109524408A CN 109524408 A CN109524408 A CN 109524408A CN 201811092138 A CN201811092138 A CN 201811092138A CN 109524408 A CN109524408 A CN 109524408A
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- conductor
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- semiconductor memory
- memory
- semiconductor
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- Non-Volatile Memory (AREA)
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Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017179348A JP2019057532A (ja) | 2017-09-19 | 2017-09-19 | 半導体メモリ |
JP2017-179348 | 2017-09-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN109524408A true CN109524408A (zh) | 2019-03-26 |
Family
ID=65721601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811092138.3A Pending CN109524408A (zh) | 2017-09-19 | 2018-09-19 | 半导体存储器 |
Country Status (4)
Country | Link |
---|---|
US (6) | US10381374B2 (zh) |
JP (1) | JP2019057532A (zh) |
CN (1) | CN109524408A (zh) |
TW (4) | TWI731796B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112510050A (zh) * | 2019-09-13 | 2021-03-16 | 铠侠股份有限公司 | 半导体存储装置 |
CN112563287A (zh) * | 2019-09-10 | 2021-03-26 | 铠侠股份有限公司 | 半导体装置及半导体装置的制造方法 |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10892269B2 (en) * | 2014-09-12 | 2021-01-12 | Toshiba Memory Corporation | Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit |
JP6203152B2 (ja) * | 2014-09-12 | 2017-09-27 | 東芝メモリ株式会社 | 半導体記憶装置の製造方法 |
CN111052236B (zh) | 2017-09-06 | 2024-03-05 | 株式会社半导体能源研究所 | 半导体装置 |
JP2019057532A (ja) * | 2017-09-19 | 2019-04-11 | 東芝メモリ株式会社 | 半導体メモリ |
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TW202143224A (zh) | 2021-11-16 |
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US11729973B2 (en) | 2023-08-15 |
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