CN109120268A - A kind of dynamic comparer offset voltage calibration method - Google Patents
A kind of dynamic comparer offset voltage calibration method Download PDFInfo
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- CN109120268A CN109120268A CN201810987111.4A CN201810987111A CN109120268A CN 109120268 A CN109120268 A CN 109120268A CN 201810987111 A CN201810987111 A CN 201810987111A CN 109120268 A CN109120268 A CN 109120268A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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Abstract
A kind of dynamic comparer offset voltage calibration method, belongs to Analogous Integrated Electronic Circuits technical field.The present invention is suitable for the gradually-appoximant analog-digital converter of bottom crown sampled form, by the way that a calibration with the mutually isostructural calibration capacitance array realization of quantization capacitor array to comparator offset voltage is arranged in the digital analog converter of gradually-appoximant analog-digital converter；The quantizing process of the digital analog converter of gradually-appoximant analog-digital converter includes calibration mode and normal mode of operation, imbalance code word is obtained to 0 quantization using gradually-appoximant analog-digital converter when calibration mode, according to the switching of capacitor in imbalance code word control calibration capacitance array, the output quantization code word for the comparator imbalance voltage that has been eliminated when normal mode of operation.The present invention can eliminate the relative influence of the comparator imbalance voltage in the output quantization code word that gradually-appoximant analog-digital converter obtains, and logic is simply easily achieved, and calibration accuracy is high and does not need to refresh in real time.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to one kind samples gradual approaching for bottom crown
The dynamic comparer offset voltage calibration method of number converter (SAR ADC).
Background technique
With the fast development of mobile communication, portable testing set, consumer electronics wireless communication etc., it is desirable that modulus
The higher the better for the speed of converter (ADC), the lower power consumption the better.Relative to traditional high-speed high-precision flow line (pipeline)
ADC, successive approximation (SAR) ADC possess that structure is simple, area is small, the characteristics such as low in energy consumption, at low cost, technology feature size
It constantly reduces and the application (such as time-interleaved, more bit shifts) of some technologies is but also SAR ADC is provided with realization height
A possibility that speed conversion.Therefore SAR ADC has great potentiality in the application field of high-speed low-power-consumption.
Main modular includes: comparator, digital analog converter (DAC), register cell and logic control list in SAR ADC
Member etc..Wherein, comparator is the core circuit of SAR ADC, decides the indexs such as the speed, precision and power consumption of ADC, is had very
Important role.Ideal comparator has the low and high level of equal probabilities to export when inputting equal；And for actual comparators,
Due to process mismatch, there are comparator imbalance voltage Voffset, only when the difference of input is equal to offset voltage
When Voffset, the probability for exporting low and high level is just equal.A comparator is mostly used in single-channel SAR ADC, therefore comparator loses
It adjusts voltage mainly to cause DC offset error, leads to the reduction of the quantizing range of ADC.And for the SAR using multiple comparators
For ADC, comparator imbalance causes nonlinearity erron, and the performance of ADC is caused to decline.Comparator imbalance is mainly by inputting to pipe
The mismatch of threshold voltage and size causes, therefore can be reduced by increasing the size of input pipe, but big size certainly will be brought
Big power consumption.
Summary of the invention
It is asked for SAR ADC quantizing range caused by comparator imbalance voltage in above-mentioned SAR ADC is small with what performance declined
Topic, and tradition eliminate power problems existing for the method for comparator imbalance, are suitable for using lower pole the invention proposes one kind
The offset voltage calibration method of the gradually-appoximant analog-digital converter SAR ADC dynamic comparer of plate sampling technique, logic are simply easy
In realization, and calibration accuracy can achieve 1 LSB (ADC minimum resolution).
The technical solution of the present invention is as follows:
A kind of dynamic comparer offset voltage calibration method, the output quantity obtained for calibrating gradually-appoximant analog-digital converter
Change the comparator imbalance voltage in code word, the digital analog converter of the gradually-appoximant analog-digital converter include quantization capacitor array and
Calibration capacitance array, the calibration capacitance array are consistent with the quantization capacitor array；
The step of gradually-appoximant analog-digital converter calibrates comparator offset voltage in quantization is as follows:
Step 1: the calibration capacitance array is connected common mode electricity with the top crown of all capacitors in quantization capacitor array
Pressure is sampled using all capacitor bottom crowns in the calibration capacitance array and quantization capacitor array to 0；
Step 2: capacitor bottom crowns all in the quantization capacitor array are connected common-mode voltage, by the calibration capacitance
All capacitor bottom crowns are connect with its higher level version in array, by all capacitors in the quantization capacitor array and calibration capacitance array
Top crown disconnected with common-mode voltage, comparator starts to compare and be switched in the quantization capacitor array according to comparison result
The connect current potential of the bottom crown of each capacitor, obtained after having switched the lowest order capacitor of the quantization capacitor array it is described gradually
Approach the imbalance code word of analog-digital converter；
Step 3: all capacitor bottom crowns of the quantization capacitor array are connected input voltage, by the calibration capacitance
The inversion signal for the imbalance code word that all capacitor bottom crowns are obtained according to step 2 in array carries out corresponding switching, will be described
Quantify capacitor array and connects common-mode voltage with the top crown of all capacitors in calibration capacitance array；
Step 4: the bottom crown of all capacitors in the quantization capacitor array is connected common-mode voltage, by calibration capacitance battle array
The bottom crown of all capacitors is even connect with top crown in column, by all capacitors in the quantization capacitor array and calibration capacitance array
Top crown disconnected with common-mode voltage, comparator starts to compare and be switched in the quantization capacitor array according to comparison result
The connect current potential of the bottom crown of each capacitor, obtained after having switched the lowest order capacitor of the quantization capacitor array it is described gradually
The output quantization code word of analog-digital converter is approached, the output quantization code word is to eliminate the result of comparator imbalance voltage.
Specifically, the gradually-appoximant analog-digital converter is the single-ended sampling of digital analog converter, an input terminal of comparator
The quantization capacitor array and calibration capacitance array are connected, another input terminal of comparator connects forward reference voltage, in step
When rapid a pair 0 samples, the calibration capacitance array connects ground voltage with all capacitor bottom crowns in quantization capacitor array.
Specifically, the gradually-appoximant analog-digital converter is the sampling of digital analog converter both-end, each input terminal of comparator
It is all connected with the quantization capacitor array and calibration capacitance array, when step 1 is to 0 sampling, the calibration capacitance array and quantization
All capacitor bottom crowns connect common-mode voltage in capacitor array.
The invention has the following beneficial effects: the present invention can eliminate in the output quantization code word that gradually-appoximant analog-digital converter obtains
Comparator imbalance voltage relative influence, logic is simply easily achieved, and calibration accuracy is high and does not need to refresh in real time.
Detailed description of the invention
Fig. 1 is to be suitable for a kind of gradually forcing for dynamic comparer offset voltage calibration method proposed by the present invention in embodiment
The structural schematic diagram of DAC and comparator in near-lying mode number converter.
Fig. 2 is a kind of dynamic comparer offset voltage calibration method proposed by the present invention in embodiment under calibration mode
DAC capacitor plate potential change schematic diagram, wherein Fig. 2 (a) is to 0 sample phase, and Fig. 2 (b) is that sampling terminates comparator progress
Before comparing, Fig. 2 (c) is after comparator compares.
Fig. 3 is a kind of dynamic comparer offset voltage calibration method proposed by the present invention normal mode of operation in embodiment
Lower DAC capacitor plate potential change schematic diagram, wherein Fig. 3 (a) is to input voltage sample phase, and Fig. 3 (b) is that sampling terminates ratio
Before being compared compared with device, Fig. 3 (c) is after comparator compares.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is described in detail:
The present invention is suitable for the gradually-appoximant analog-digital converter of bottom crown sampled form, by Approach by inchmeal analog-to-digital conversion
One is arranged in the digital analog converter of device and realizes comparison with the isostructural calibration capacitance array cCDAC of quantization capacitor array CDAC phase
It is a kind of circuit structure of the digital analog converter of gradually-appoximant analog-digital converter as shown in Figure 1 compared with the calibration of device offset voltage, amount
Change one of input terminal of the top crown connection comparator of capacitor in capacitor array CDAC, bottom crown passes through switch connection benchmark
Voltage, common-mode voltage, input voltage or ground voltage；Of capacitor in calibration capacitance array cCDAC and quantization capacitor array CDAC
Number corresponded to capacitance it is identical, likewise, in calibration capacitance array cCDAC capacitor top crown connect comparator one of them
Input terminal, bottom crown pass through switch connection reference voltage, common-mode voltage, input voltage or ground voltage；Calibration capacitance array cCDAC
It is connected by a switch with common-mode voltage Vcm with the top crown of quantization capacitor array CDAC, and calibration capacitance array cCDAC institute
Having the bottom crown of capacitor can be connect by a switch with top crown.
The present invention suitable for gradually-appoximant analog-digital converter with digital analog converter it is single-ended sampling and both-end sampling, below with
The course of work that the present invention will be described in detail for the sampling of digital analog converter both-end.
Being suitable for the invention SAR ADC, there are two types of operating modes: calibration mode and normal mode of operation in quantization, often
Kind mode has sample phase and comparison phase respectively, below by taking four potential differences divide SAR ADC as an example, successively carries out according to the stage
Detailed description.
Fig. 2 (a) is the sample phase of calibration mode: the bottom crown of quantization all capacitors of capacitor array CDAC connects common-mode voltage
The bottom crown of all capacitors of Vcm, calibration capacitance array cCDAC meets common-mode voltage Vcm, quantifies capacitor array CDAC and calibration capacitance
The top crown of all capacitors of array cCDAC meets common-mode voltage Vcm.
Fig. 2 (b)-(c) is the comparison phase of calibration mode: before comparing beginning, quantization all capacitors of capacitor array CDAC
Bottom crown meets common-mode voltage Vcm, and the bottom crown and calibration capacitance array cCDAC of all capacitors of calibration capacitance array cCDAC are all
The top crown of capacitor connects, and quantifies the top crown and common mode electricity of capacitor array CDAC and all capacitors of calibration capacitance array cCDAC
Pressure Vcm is disconnected；Subsequent comparator starts to compare and be determined under quantization every capacitor of capacitor array CDAC according to comparison result
The connect current potential of pole plate is forward direction reference voltage VREFP or negative sense reference voltage VREFN, until the amount of switching is completed in minimum bit comparison
Change the lowest order capacitor in capacitor array CDAC, the output codons for obtaining SAR ADC are the code word Doffset that lacks of proper care.It is calibrating
During the comparison phase of mode, calibration capacitance array cCDAC bottom crown connects with top crown always.
The sample phase of Fig. 3 (a) normal mode of operation: the bottom crown of quantization all capacitors of capacitor array CDAC connects input letter
Number Vinn or Vinp, the bottom crown of each capacitor of calibration capacitance array cCDAC according to the inversion signal of imbalance code word Doffset into
The corresponding switching of row, the top crown for quantifying capacitor array CDAC and all capacitors of calibration capacitance array cCDAC meet common-mode voltage Vcm.
The comparison phase of Fig. 3 (b)-(c) normal mode of operation: the bottom crown of quantization all capacitors of capacitor array CDAC connects altogether
The bottom crown of all capacitors of mode voltage Vcm, calibration capacitance array cCDAC connects with the top crown of capacitor, the upper pole of all capacitors
Plate is disconnected with common-mode voltage Vcm.Start to compare, pole under quantization every capacitor of capacitor array CDAC is determined according to comparison result
The connect current potential of plate is VREFP or VREFN, until minimum bit comparison completes to have switched the lowest order electricity in quantization capacitor array CDAC
Hold, obtain the output quantization code word Dout of ADC, this output quantization code word Dout is defeated after eliminating comparator imbalance voltage
Result out.During the comparison phase of normal mode of operation, calibration capacitance array cCDAC bottom crown always with top crown phase
It connects.
The operation principle of the present invention is that: SAR ADC passes through quantization capacitor array CDAC bottom crown sampled input signal, in conjunction with
Comparator completes quantizing process, and before normal work quantifies input voltage, the present invention first quantifies zero input, obtains
The corresponding imbalance code word Doffset of offset voltage Voffset, wherein when the single-ended sampling of digital analog converter, one of comparator is defeated
Entering end connection quantization capacitor array and calibration capacitance array, another input terminal of comparator connects forward reference voltage, so that
The quantizing range of the SAR ADC of single-ended structure is-VCM~+VCM, needs 0 sampling by calibration capacitance array cCDAC and quantization
All capacitor bottom crowns of capacitor array CDAC connect ground level；When digital analog converter both-end samples, due to the SAR of differential configuration
ADC, if input is vi, both sides sampled voltage is respectively VCM+vi/2 and VCM-vi/2, therefore needs to compare connection to 0 sampling
The calibration capacitance array cCDAC of two input terminals of device connects common mode electricity with the bottom crown of all capacitors in quantization capacitor array CDAC
It is flat.In the sample phase of SAR ADC normal mode of operation, the school of calibration digital analog converter is passed through according to imbalance code word Doffset
Pseudo-capacitance array cCDAC, compensated input signal, to achieve the purpose that mistuning calibration function.
By taking both-end samples as an example, according to SAR ADC working principle, at the end of calibration mode, quantify capacitor array CDAC
Output voltage are as follows:
Wherein, VdpFor the end the P output voltage of digital analog converter DAC, VxnFor the N-terminal output voltage of digital analog converter DAC,
It also is comparator N-terminal input voltage, VriI-th bit capacitor in the quantization capacitor array CDAC connected for the end P of digital analog converter DAC
Bottom crown connects current potential,I-th bit capacitor bottom crown in the quantization capacitor array CDAC connected for the N-terminal of digital analog converter DAC
Current potential is connected, andFor VriInversion signal, VcmFor common-mode voltage, CiTo quantify i-th bit capacitance in capacitor array CDAC,
CtFor single-ended total capacitance value.
Comparator input voltage VxMeet following formula:
The sample phase of normal mode of operation quantifies the capacitor charging of capacitor array CDAC:
The comparison phase of normal mode of operation before starting comparison, quantifies the electricity of bottom crown on the capacitor of capacitor array CDAC
Lotus amount meets:
The then input voltage of comparator are as follows:
Hereafter, start to compare, SAR ADC is to comparator terminal input voltage VxQuantified.And existed according to formula (1) latter
Within the half of the quantified precision 1LSB of ADC, therefore ADC has reacted input voltage V to the quantized result of formula (5)in=Vinp-Vinn
Size, and error is within 1LSB, has achieved the purpose that eliminate imbalance.
In conclusion the invention proposes a kind of comparator imbalance voltage calibration methods applied to SAR ADC, it is only necessary to
On the basis of traditional digital analog converter DAC addition one and quantization the mutually isostructural calibration capacitance array of capacitor array with simply
Logical design can be realized, calibration accuracy is high and does not need to refresh in real time.
Those skilled in the art should understand that modification and variation combination can be made to the present invention, but do not taking off
In range from the spirit of this programme, it should all cover within the scope of the present invention.
Claims (3)
1. a kind of dynamic comparer offset voltage calibration method, which is characterized in that obtained for calibrating gradually-appoximant analog-digital converter
To output quantization code word in comparator imbalance voltage, the digital analog converter of the gradually-appoximant analog-digital converter includes quantization
Capacitor array and calibration capacitance array, the calibration capacitance array are consistent with the quantization capacitor array；
The step of gradually-appoximant analog-digital converter calibrates comparator offset voltage in quantization is as follows:
Step 1: the calibration capacitance array is connected into common-mode voltage with the top crown of all capacitors in quantization capacitor array, benefit
It is sampled with all capacitor bottom crowns in the calibration capacitance array and quantization capacitor array to 0；
Step 2: capacitor bottom crowns all in the quantization capacitor array are connected common-mode voltage, by the calibration capacitance array
In all capacitor bottom crowns connect with its top crown, by it is described quantization capacitor array and calibration capacitance array in all capacitors it is upper
Pole plate is disconnected with common-mode voltage, and comparator starts to compare and be switched according to comparison result each in the quantization capacitor array
The connect current potential of the bottom crown of capacitor obtains the Approach by inchmeal after having switched the lowest order capacitor of the quantization capacitor array
The imbalance code word of analog-digital converter；
Step 3: all capacitor bottom crowns of the quantization capacitor array are connected input voltage, by the calibration capacitance array
In the inversion signal of the imbalance code word that is obtained according to step 2 of all capacitor bottom crowns carry out corresponding switching, by the quantization
Capacitor array connects common-mode voltage with the top crown of all capacitors in calibration capacitance array；
Step 4: the bottom crown of all capacitors in the quantization capacitor array is connected into common-mode voltage, it will be in calibration capacitance array
The bottom crowns of all capacitors even connect with top crown, quantifies the upper of all capacitors in capacitor array and calibration capacitance array for described
Pole plate is disconnected with common-mode voltage, and comparator starts to compare and be switched according to comparison result each in the quantization capacitor array
The connect current potential of the bottom crown of capacitor obtains the Approach by inchmeal after having switched the lowest order capacitor of the quantization capacitor array
The output quantization code word of analog-digital converter, the output quantization code word are to eliminate the result of comparator imbalance voltage.
2. dynamic comparer offset voltage calibration method according to claim 1, which is characterized in that the Approach by inchmeal mould
Number converter is the single-ended sampling of digital analog converter, and an input terminal of comparator connects the quantization capacitor array and calibration capacitance
Another input terminal of array, comparator connects forward reference voltage, when step 1 is to 0 sampling, the calibration capacitance array
Ground voltage is connected with all capacitor bottom crowns in quantization capacitor array.
3. dynamic comparer offset voltage calibration method according to claim 1, which is characterized in that the Approach by inchmeal mould
Number converter is the sampling of digital analog converter both-end, and each input terminal of comparator is all connected with the quantization capacitor array and calibration electricity
Hold array, when step 1 is to 0 sampling, the calibration capacitance array connects altogether with all capacitor bottom crowns in quantization capacitor array
Mode voltage.
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| CN111490791A (en) * | 2020-05-13 | 2020-08-04 | 深圳芥子科技有限公司 | Incremental successive approximation analog-to-digital converter |
| US10862494B2 (en) | 2019-04-30 | 2020-12-08 | Xiamen University | Background offset drift calibration circuit and method for comparator |
| CN112636757A (en) * | 2020-12-25 | 2021-04-09 | 上海东软载波微电子有限公司 | Successive approximation type analog-to-digital converter and offset compensation method thereof |
| CN112994699A (en) * | 2021-03-04 | 2021-06-18 | 北京大学（天津滨海）新一代信息技术研究院 | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method |
| CN113131934A (en) * | 2021-04-29 | 2021-07-16 | 东南大学 | Comparator offset voltage calibration method applied to 16-bit low-power-consumption successive approximation type analog-to-digital converter |
| CN113922819A (en) * | 2021-12-14 | 2022-01-11 | 之江实验室 | One-step two-bit successive approximation type analog-to-digital converter based on background calibration |
| CN114614821A (en) * | 2022-03-30 | 2022-06-10 | 深圳齐芯半导体有限公司 | SAR ADC offset error correction method and circuit based on differential structure |
| CN114640350A (en) * | 2022-03-30 | 2022-06-17 | 中国科学技术大学 | Successive approximation analog-to-digital converter, calibration method and working method |
| CN115118281A (en) * | 2022-06-29 | 2022-09-27 | 北京知存科技有限公司 | Offset calibration control method for successive approximation analog-to-digital converter |
| CN116073829A (en) * | 2023-03-07 | 2023-05-05 | 南京航空航天大学 | LMS foreground calibration method and system of successive approximation type ADC |
| CN117176168A (en) * | 2023-08-25 | 2023-12-05 | 重庆览山汽车电子有限公司 | Calibration method and successive approximation type analog-to-digital converter |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10862494B2 (en) | 2019-04-30 | 2020-12-08 | Xiamen University | Background offset drift calibration circuit and method for comparator |
| CN111490791A (en) * | 2020-05-13 | 2020-08-04 | 深圳芥子科技有限公司 | Incremental successive approximation analog-to-digital converter |
| CN111490791B (en) * | 2020-05-13 | 2023-04-07 | 深圳芥子科技有限公司 | Incremental successive approximation analog-to-digital converter |
| CN112636757A (en) * | 2020-12-25 | 2021-04-09 | 上海东软载波微电子有限公司 | Successive approximation type analog-to-digital converter and offset compensation method thereof |
| CN112636757B (en) * | 2020-12-25 | 2024-05-31 | 上海东软载波微电子有限公司 | Successive approximation type analog-to-digital converter and offset compensation method thereof |
| CN112994699B (en) * | 2021-03-04 | 2022-10-04 | 北京大学（天津滨海）新一代信息技术研究院 | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method |
| CN112994699A (en) * | 2021-03-04 | 2021-06-18 | 北京大学（天津滨海）新一代信息技术研究院 | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method |
| CN113131934A (en) * | 2021-04-29 | 2021-07-16 | 东南大学 | Comparator offset voltage calibration method applied to 16-bit low-power-consumption successive approximation type analog-to-digital converter |
| CN113922819A (en) * | 2021-12-14 | 2022-01-11 | 之江实验室 | One-step two-bit successive approximation type analog-to-digital converter based on background calibration |
| CN114614821B (en) * | 2022-03-30 | 2023-10-20 | 广东齐芯半导体有限公司 | SAR ADC offset error correction method and circuit based on differential structure |
| CN114640350A (en) * | 2022-03-30 | 2022-06-17 | 中国科学技术大学 | Successive approximation analog-to-digital converter, calibration method and working method |
| CN114640350B (en) * | 2022-03-30 | 2024-05-24 | 中国科学技术大学 | Successive approximation analog-to-digital converter, calibration method and working method |
| CN114614821A (en) * | 2022-03-30 | 2022-06-10 | 深圳齐芯半导体有限公司 | SAR ADC offset error correction method and circuit based on differential structure |
| CN115118281A (en) * | 2022-06-29 | 2022-09-27 | 北京知存科技有限公司 | Offset calibration control method for successive approximation analog-to-digital converter |
| CN116073829A (en) * | 2023-03-07 | 2023-05-05 | 南京航空航天大学 | LMS foreground calibration method and system of successive approximation type ADC |
| CN117176168A (en) * | 2023-08-25 | 2023-12-05 | 重庆览山汽车电子有限公司 | Calibration method and successive approximation type analog-to-digital converter |
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