CN109462402B

CN109462402B - Mixed type assembly line ADC structure

Info

Publication number: CN109462402B
Application number: CN201811241098.4A
Authority: CN
Inventors: 贾华宇; 马珺; 杜知微
Original assignee: Taiyuan University of Technology
Current assignee: Taiyuan University of Technology
Priority date: 2018-10-24
Filing date: 2018-10-24
Publication date: 2022-08-16
Anticipated expiration: 2038-10-24
Also published as: CN109462402A

Abstract

The invention discloses a mixed type assembly line ADC structure, which comprises 1 traditional 4-bit MDAC, 1 zero-crossing comparator, 5 mixed time domain quantizers and 1 digital calibration module; the MDAC output end is connected with the zero crossing comparator, the output end of the zero crossing comparator is sequentially connected with 5 mixed time domain quantizers, the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of the digital calibration module, and the output end of the digital calibration module is in two-way connection with the MDAC input end. The 1 st-stage MDAC (multiplying digital-to-analog converter) inputs a voltage signal, performs voltage-time conversion through a zero-crossing comparator, outputs a time pulse signal, and adopts a time domain quantizer at the later stage. Designing a mixed time domain quantizer that uses 1 capacitor DAC instead of the DAC in the time domain can reduce clock jitter errors.

Description

Mixed type assembly line ADC structure

Technical Field

The invention belongs to the technical field of pipeline analog-to-digital converters, and particularly relates to a novel mixed pipeline ADC structure.

Background

The high speed development of modern communication systems puts higher demands on the performance of ADCs. In wireless communications, high linearity and high dynamic range ADCs are typically required to provide a sufficiently high clutter free dynamic range to signal-to-noise harmonic distortion ratio. The increasing speed of communication systems has led to an increasing amount of data that needs to be processed per unit of time, which has placed higher demands on the speed of the ADC. The rapid development of personal communication systems and various types of portable consumer electronics products requires further reduction in power consumption of ADCs.

The pipelined ADC adopts a working mode of connecting a high-gain margin amplifier and a plurality of sub-stages in series, so that the pipelined ADC has the characteristics of high precision and high speed, and becomes a hotspot of research in the field of converters. The residue amplifier in the traditional pipeline sub-stage has the characteristics of high gain, high linearity and the like, so that the ADC can obtain higher precision and smaller nonlinear error. However, the conventional residue amplifier composed of the operational amplifier and the switched capacitor has a complex circuit design and high difficulty, and generates large power consumption. Especially at low supply voltages, the headroom amplifier makes it more difficult to achieve a compromise between low power consumption and high accuracy.

The time domain based analog-to-digital conversion technology was proposed in 2008, and the technology is used for pipeline ADC in 2014, which combines the time domain based converter and the traditional pipeline structure, absorbs the advantages of the two structures, and realizes high-precision and high-speed analog-to-digital conversion with lower power consumption. However, as a new ADC structure, the pipeline ADC based on time domain needs to solve two key problems: 1. when the high-precision analog-to-digital conversion is realized, the number of the sub-stages of the assembly line is large, and the power consumption is not easy to further reduce. 2. The 1 st stage MDAC (multiplying digital-to-analog converter) of the pipeline ADC based on the time domain usually adopts a closed loop high-performance amplifier to realize an inter-stage margin amplifier, which can obtain more accurate gain and less nonlinear error, but this will generate larger power consumption. However, if a margin amplifier with a simpler structure and a lower open-loop gain is adopted, the margin curve deviates from the ideal characteristics due to the limited open-loop gain and the nonlinear error, thereby affecting the conversion accuracy.

Disclosure of Invention

The invention aims to provide a novel mixed type pipeline ADC structure which has the characteristics and advantages of a time domain converter and a voltage domain converter and meets the parameter requirements of high precision and low power consumption.

In order to achieve the purpose, the invention adopts the following specific technical scheme:

a mixed type pipeline ADC structure comprises 1 traditional 4-bit MDAC (multiplying digital-to-analog converter), 1 zero-crossing comparator, 5 mixed time domain quantizers and 1 digital calibration module. Other auxiliary modules include voltage current reference, clock module, digital output module, etc.

The MDAC output end is connected with the zero crossing comparator, the output end of the zero crossing comparator is sequentially connected with 5 mixed time domain quantizers, the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of the digital calibration module, and the output end of the digital calibration module is in two-way connection with the MDAC input end.

The structure of the invention adopts MDAC multiplying digital-to-analog converter in voltage domain in the 1 st stage of the assembly line), and adopts a time domain quantizer in the later stage. The input of the 1 st stage MDAC (multiplying digital-to-analog converter) is a voltage signal, the output of the 1 st stage MDAC is subjected to voltage-time conversion by a zero-crossing comparator, so that the output of the 1 st stage MDAC is a time pulse signal, and the time domain of the later stage is a time domainThe quantizer operates in the time domain. Wherein, the voltage-time conversion process needs 3 clock phases, and the sampling and feedback capacitors discharge simultaneously. During the voltage-time conversion, outputT _O Is linear and is not affected by amplifier parameters. The latter stage employs 5 mixed time domain quantizers, which can reduce clock jitter error, and after the zero-crossing time, the amplified time margin output is transmitted to the next stage. And the time domain quantizer of the later stage adopts 1 capacitor DAC to replace the DAC of the time domain, so that the clock jitter error can be reduced.

The invention has reasonable design, and particularly has good practical application and popularization values.

Drawings

Fig. 1 shows the novel hybrid pipeline ADC architecture.

Fig. 2 shows the voltage-time conversion process in the novel hybrid pipelined ADC architecture.

Fig. 3 shows a hybrid time domain quantizer in the novel hybrid pipelined ADC architecture.

Fig. 4 shows the operation of the hybrid time domain quantizer in the hybrid pipelined ADC architecture of the present invention.

Detailed Description

The following detailed description of specific embodiments of the invention refers to the accompanying drawings.

A hybrid pipelined ADC architecture, as shown in FIG. 1, includes 1 conventional 4-bit MDAC, 1 zero-crossing comparator, 5 hybrid time-domain quantizers, and 1 digital calibration block. Other auxiliary modules include voltage current reference, clock module, digital output module, etc. The output end of the MDAC is connected with the zero-crossing comparator, the output end of the zero-crossing comparator is sequentially connected with the 5 mixed time domain quantizers, the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of the digital calibration module, and the output end of the digital calibration module is in two-way connection with the input end of the MDAC.

The traditional assembly line has more substages and is not easy to further reduce power consumption. The structure replaces the traditional assembly line sub-stage with the assembly line except the 1 st stage by the converter sub-stage based on the time domain, and can reduce the power consumption of the ADC on the premise of not reducing the precision. The structure of the time quantizer is designed, and the mixed time domain quantizer is adopted, so that the clock jitter error can be reduced.

The signal input to the hybrid pipeline ADC first passes through a sample-and-hold circuit, and then is input to a 1 st stage MDAC (multiplying digital-to-analog converter), which is a voltage signal. The MDAC can amplify the input voltage signal and then perform voltage-time conversion through the zero comparator, so that the input signal at the later stage is a time domain signal. The signal inputted to the time quantizer 1 is an amplified time domain signal and is an analog signal, the time quantizer 1 can perform AD conversion on the inputted analog signal and can generate a 2.5-bit digital output, and the analog signal which is not converted and the analog signal inputted to the time quantizer 1 are subjected to margin amplification by a comparator and are used as the input of the subsequent stage. The signal input to the time quantizer 2 is a time domain analog signal after the margin amplification, and the same operation as that of the time quantizer 1 is performed again. And the digital output of each time quantizer is used for obtaining a complete digital signal after the conversion of the total input analog signal through the digital signal output by the digital calibration module.

Fig. 2 shows the voltage-time conversion process in the present structure. This conversion process requires 3 clock phases, with the sample and feedback capacitors discharging simultaneously. Since there is no charge on both capacitors, the output of the time domain is always linear at zero crossings, given that the linear characteristics of the current sources meet the requirements, without taking into account the non-ideal characteristics of the amplifier. The output of the time domain is independent of the amplifier parameters at the zero crossing of the discharge time phase, so that during this voltage-time conversion the output isT _O Is linear and is not affected by amplifier parameters. In the zero-crossing detection, the time-domain output signal is independent of the error of the amplifier, so 1 low-gain nonlinear amplifier can be used in the voltage-time conversion process.

Fig. 3 is a hybrid time domain quantizer. The charge subtraction of the quantizer is done with 1 capacitive DAC. The linearity of the DAC in the structure is determined only by matching of the capacitors, and the implementation is easy. The time domain errors such as time jitter and mismatch of delay units only affect the linearity of the sub-TDC and have no effect on the inter-stage margin.

Fig. 4 shows the operation of the hybrid time domain quantizer. First, all the capacitors are reset to the positive reference voltage. In the charging phase, the capacitor is charged with a current input based on time. At this point, the sub-TDC quantizes the time input and generates a corresponding hot code output. In the next clock phase, the charge stored on the capacitor (representing the remaining amount) is discharged by the current source I and the remaining amount is amplified. After the zero-crossing time, the amplified time margin input is transmitted to the next stage.

It should be noted that modifications and applications may occur to those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A mixed pipeline ADC structure is characterized in that: the system comprises 1 traditional 4-bit MDAC, 1 zero-crossing comparator, 5 mixed time domain quantizers and 1 digital calibration module;

the output end of the MDAC is connected with a zero-crossing comparator, the output end of the zero-crossing comparator is sequentially connected with 5 mixed time domain quantizers, the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of a digital calibration module, and the output end of the digital calibration module is bidirectionally connected with the input end of the MDAC;

3 clock phases are adopted in the zero-crossing comparator in the voltage-time conversion process, and the sampling capacitor and the feedback capacitor discharge at the same time;

firstly, inputting a signal input into an ADC (analog to digital converter) of the hybrid pipeline into a 1 st-stage MDAC (multilevel digital AC) after the signal passes through a sample-hold circuit, wherein the input MDAC is a voltage signal; the MDAC amplifies the input voltage signal, and then performs voltage-time conversion through a zero comparator, so that the input post-stage signal is a time domain signal; the signal input into the time quantizer 1 is an amplified time domain signal and is an analog quantity signal, the time quantizer 1 performs AD conversion on the input analog quantity signal to generate a 2.5-bit digital output, and the analog signal which is not converted and the analog signal input into the time quantizer 1 are subjected to margin amplification through a comparator and serve as input of a later stage; the signal input to the time quantizer 2 is a time domain analog signal after margin amplification, and the same working process as that of the time quantizer 1 is performed again; the digital output of each time quantizer is used for obtaining a complete digital signal after the conversion of the total input analog signal through the digital signal output by the digital calibration module.

2. The hybrid pipelined ADC structure of claim 1, wherein: the time domain quantizer adopts 1 capacitor DAC to replace the DAC of the time domain.