CN106533443A - Offset voltage calibration circuit for high-speed dynamic comparator - Google Patents
Offset voltage calibration circuit for high-speed dynamic comparator Download PDFInfo
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- CN106533443A CN106533443A CN201611024728.3A CN201611024728A CN106533443A CN 106533443 A CN106533443 A CN 106533443A CN 201611024728 A CN201611024728 A CN 201611024728A CN 106533443 A CN106533443 A CN 106533443A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1023—Offset correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/125—Asynchronous, i.e. free-running operation within each conversion cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention belongs to the technical field of analogue integrated circuits, and particularly relates to an offset voltage calibration circuit for a high-speed dynamic comparator. The circuit comprises a pulse modulator, a digital-to-analog converter, the comparator, a register logical unit, and an offset voltage calibration circuit, wherein the circuit adopts upper plate sampling, an input end of the comparator is connected with an output end or a common-mode level of the digital-to-analog converter, and an output end of the offset voltage calibration circuit is connected with an input end of the digital-to-analog converter. The offset voltage calibration circuit for the high-speed dynamic comparator provided by the invention has the advantages that an offset voltage of the comparator is compensated through the calibration circuit and the digital-to-analog converter; and the calibration is digital, so that hardware requirements are low, the reliability is high, the power consumption is low, and the calibration is accurate.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical field, and in particular to a kind of to change for high speed successive approximation modulus
The dynamic comparer offset voltage calibration circuit of device (hereinafter referred to as SAR ADC).
Background technology
ADC is a kind of circuit that analog circuit signal is converted into Digital Circuit Signal, and which is widely used in communication, signal
In all kinds of electronic systems such as process, storage, and play irreplaceable effect.Currently, electronic information technology development is swift and violent, market
Especially Communications Market is very big to the ADC demands of high speed, middle precision, low-voltage, low-power consumption.Compared to the ADC of other structures,
SAR ADC simple structures, area are little.SAR ADC analogue units are less simultaneously, with the continuous contracting of semiconductor fabrication process size
Little, SAR ADC become the emphasis and focus of domestic and international research.
SAR ADC core textures mainly include comparator, digital to analog converter (hereinafter referred to as DAC) and logical block.Wherein
Comparator is the most key part in SAR ADC, and it directly determines the conversion accuracy and conversion speed of SAR ADC.Relatively
Main problem in device design includes comparing speed, resolution ratio, offset voltage；Relatively speed and resolution ratio are largely determined by ratio
Compared with the structure and size of device, what offset voltage was mainly caused to the threshold voltage mismatch and W/L mismatches of pipe by input crystal, and it is normal
Greatly, it directly affects the linearity of SAR ADC and dynamic model to the offset voltage of the dynamic comparer in high speed SAR ADC
Enclose.Therefore, it is to ensure dynamic range and precision, needs to calibrate the offset voltage of comparator.
In industrial quarters, current SAR ADC products are mainly middle low speed ADC, this SAR of the sample rate less than 10Msps
Static comparison device being adopted ADC, comparator imbalance calibration voltage technology is based on multistage AC coupled technology more；Should in high-speed ADC
With in, dynamic comparer by deduct output mean value carry out offset voltage calibration, the shortcoming of this collimation technique is to subtract
The little dynamic range of SAR ADC；In academic research, by the differential pair to comparator input difference to pipe a pair of biasings in parallel
Pipe, calibrates offset voltage, the input of differential pair generally using electric capacity storage electric charge-, but the shortcoming of this collimation technique exists
It is analog quantity in the calibration information of storage, therefore antijamming capability is weak, and stability is poor, is difficult to apply to practical application.
The content of the invention
The present invention proposes a kind of imbalance electricity for being applied to high speed, medium accuracy (8-10 positions) SAR ADC dynamic comparers
Pressure calibration circuit, not only can accurately compensate the offset voltage of dynamic comparer, and calibration range is also greatly increased.
The technical scheme is that, a kind of high speed dynamic comparer offset voltage calibration circuit, it is characterised in that include
Comparator, pulse-modulator, digital to analog converter, register logic unit, sampling hold circuit, asynchronous clock and register and mistake
Adjust voltage calibration circuit；Wherein：
The input of the comparator is connected with the output end of digital to analog converter, the input clock and asynchronous clock of comparator
And the output clock connection of register；
The input termination outside input clock of the pulse-modulator, for adjusting calibration mode and data transfer module
Clock；
The input end of clock of the digital to analog converter connects the output end of pulse-modulator, the data input pin of digital to analog converter
The output end of the output end and sampling hold circuit of offset voltage calibration circuit is connect, digital to analog converter is used for storing up in the calibration mode
Deposit the offset voltage of comparator；It is used for data conversion under data transfer module；
The input end of clock of the register logic unit connects the output end and asynchronous clock and register of pulse-modulator
Output end, register logic unit in the calibration mode be used for store comparator offset voltage imbalance code；Turn in data
Sort for data output under mold changing formula；
The input end of clock of the offset voltage calibration circuit connects the output end of pulse-modulator, offset voltage calibration circuit
Data input terminate register logic unit output end, offset voltage calibration circuit be used for calculate offset voltage and control number
The switch of weighted-voltage D/A converter.
Further, the offset voltage calibration circuit includes subtracter, register and switching logic；Wherein：
The input signal of subtracter includes subtrahend and minuend, the input of subtrahend and the output end of register logic unit
Connection；Output data level when the voltage of minuend is zero for input voltage；
The input of register is connected with the output end of subtracter, by external control signal control register；
Switching logic input is connected with register output end, and switching logic output end is connected with digital to analog converter
Connect
The present invention has the beneficial effect that：Simple structure, by increasing part logic circuit and being switched using existing DAC-circuit
Calibration is capable of achieving, therefore hardware requirement is low, reliability is high, power consumption is extremely low, calibration is accurate, and need not be refreshed in real time.
Description of the drawings
Fig. 1 is the SAR ADC structural representations using offset voltage calibration circuit of the present invention；
Fig. 2 is control signal and pulse-modulated signal sequential chart in the present invention；
Schematic diagrams of the Fig. 3 for SAR ADC offset voltage calibration circuits；
Fig. 4 is that conventional dynamic comparator imbalance voltage calibration circuit is illustrated with offset voltage calibration circuit of the present invention contrast
Figure；
Fig. 5 is offset voltage calibration circuit of the present invention switching sequence explanatory diagram in the calibration mode；Wherein, (a) be sampling
In the stage, be (b) reseting stage, is (c) process ending phase；
Fig. 6 is offset voltage calibration circuit of the present invention switching sequence explanatory diagram under normal work (data conversion) pattern；
Wherein, (a) it is sample phase, is (b) reseting stage, (c) is to process ending phase.
Specific embodiment
Below in conjunction with the accompanying drawings, the present invention is described in detail：
Fig. 1 is the SAR ADC structural representations using offset voltage calibration circuit of the present invention, comprising with lower module：One
Pulse-modulator, a sampling hold circuit, a digital to analog converter, a comparator, a register logic unit, one
Asynchronous clock produces circuit and register, an offset voltage calibration circuit；Wherein pulse-modulator as calibration control circuit,
Function includes：Clock division, clock duty cycle adjustment and the switching of ADC mode of operations.
The SAR ADC of the present invention have both of which：Calibration mode and normal mode of operation, are controlled by calibration signal,
As shown in Figure 2.When calibration signal is in low level, pulse-modulator produces periodic logical block and Cai Bao switching signals
As register logic unit and the clock of sampling hold circuit；When calibration signal is in high level, pulse-modulator produces week
Clock of the phase property calibration switch signal as mistuning calibration function potential circuit.
Fig. 3 is the offset voltage calibration circuit theory diagrams in the present invention, comprising with lower module：One subtracter, one is posted
Storage and a switching logic.
Fig. 4 is that conventional dynamic comparator imbalance voltage calibration circuit is illustrated with offset voltage calibration circuit of the present invention contrast
Figure.Fig. 4 (a) and (b) are conventional dynamic comparator imbalance voltage calibration circuit fundamental diagram；Fig. 4 (c), (d), (e), (f),
G () and (h) is offset voltage calibration circuit fundamental diagram of the present invention.Traditional comparator imbalance voltage be by comparator come
Calibration, and the comparator imbalance voltage of the present invention is compensating by digital to analog converter.
The operation principle of the present invention：Offset voltage is converted into digital code by analog-to-digital conversion by SAR ADC, then using existing
Some digital to analog converters and offset voltage calibration circuit compensation offset voltage.The offset voltage of comparator can be reduced by the present invention
To a least significant bit (LSB) voltage (LSB).
For easy analysis, it is assumed that comparator imbalance magnitude of voltage is a LSB (for comparator imbalance voltage is more than one
The situation of LSB, analysis method are similar).Fig. 5 and Fig. 6 is respectively offset voltage calibration circuit in calibration mode and normal work mould
Switching sequence explanatory diagram under formula, in figure, all electric capacity are all specific capacitances, and are labelled with highest order, interposition, lowest order；
The lowest order of C and D capacitor arrays is (DAC of this structure is referred to as pseudo-differential DAC) that can not be changed.
When offset voltage calibration circuit in the calibration mode when (Fig. 5), the subtracter in offset voltage calibration circuit and post
Storage is respectively at work and reset state.The change-over period of SAR ADC includes sampling and two stages of coded treatment, and this
The bright change-over period includes sampling, resets and coded treatment three phases.In sample phase, sampling switch (401) and output switch
(403) disconnect, comparator Differential Input short switch (402) closure, the lower step connection common-mode voltage of CDAC；In reset rank
Section, sampling switch (401), comparator Differential Input short switch (402) and output switch (403) all disconnect, the subordinate of CDAC
Plate connects common-mode voltage；In the coded treatment stage：Sampling switch (401), comparator Differential Input short switch (402) and output
Switch (403) disconnects, and comparator carried out repeating comparison in the stage, until exporting last a data, then register logical
All data are put into offset voltage calibration circuit and are calibrated by unit.
In calibration mode sample phase, CDAC charging charges are：
Q=C (Vin-Vcm)=C (Vdac+Voffset-Vcm) (1)
Wherein VinFor comparator input voltage (Vin=Vdac+Voffset), VdacFor DAC output voltage, VcmFor common-mode voltage,
VoffsetFor offset voltage, C is total capacitance value.As the voltage of sample phase input voltage and lower step is all identical value, because
This：
Q=CVoffset (2)
Such as Fig. 5 (c)：Under the condition analysis, the digital output code of SAR ADC is 1001, and reference value is 1000, by losing
Voltage calibration circuit is adjusted to obtain mistuning digital code for 0001.
When offset voltage calibration circuit in the normal mode of operation when (Fig. 6), the subtracter in offset voltage calibration circuit
Quit work, and register is in preservation state.In sample phase, sampling switch (401) and output switch (403) closure, than
Disconnect compared with device Differential Input short switch (402), subordinate's switching plate connection offset voltage calibration contactor signal of CDAC；
Reseting stage, sampling switch (401) and comparator Differential Input short switch (402) disconnect, output switch (403) closure CDAC
Lower step connection common-mode voltage；In coded treatment stage, sampling switch (401) and comparator Differential Input short switch
(402) disconnect, output switch (403) closure, comparator carried out repeating comparison in the stage, until exporting last a data.
In normal mode of operation sample phase, CDAC charging charges are：
Q=C (Vin-Vcm-Vcalibration)=C (Vdac+Voffset-Vcm-Vcalibration) (3)
Wherein VcalibrationFor calibration voltage value, C is total capacitance value.Under normal mode of operation, difference common mode VcmVoltage is
0, therefore
Q=C (Vin+Voffset-Vcalibration) (4)
For without offset voltage comparator, should meeting：
Qideal=CVin (5)
By above formula, the offset voltage after being calibrated is：
Offset voltage V in above formulaoffsetIt is a fixed value under identical condition of work, VcalibrationResolution ratio about 1
LSB, for any one offset voltage value, | Voffset-Vcalibration| minimum value be less than 0.5 LSB.Therefore this
Bright comparator imbalance error can reach 0.5 LSB.As a result such as Fig. 6 (c)：For the input that Differential Input is 0 after calibration
Voltage, the transformation result of the ADC is 1000.
In sum, the present invention proposes a kind of comparator imbalance voltage calibration circuit for being applied to high speed SAR ADC.
Claims (2)
1. a kind of high speed dynamic comparer offset voltage calibration circuit, it is characterised in that including comparator, pulse-modulator, number
Weighted-voltage D/A converter, register logic unit, sampling hold circuit, asynchronous clock and register and offset voltage calibration circuit；Wherein：
The input of the comparator is connected with the output end of digital to analog converter, the input clock of comparator and asynchronous clock and is posted
The output clock connection of storage；
The input termination outside input clock of the pulse-modulator, for adjust calibration mode and data transfer module when
Clock；
The input end of clock of the digital to analog converter connects the output end of pulse-modulator, and the data input termination of digital to analog converter is lost
The output end of the output end and sampling hold circuit of voltage calibration circuit, digital to analog converter is adjusted to be used in the calibration mode storing ratio
Compared with the offset voltage of device；It is used for data conversion under data transfer module；
The input end of clock of the register logic unit connects the defeated of the output end and asynchronous clock and register of pulse-modulator
Go out end, register logic unit is used for the imbalance code of the offset voltage for storing comparator in the calibration mode；In data conversion mould
Sort for data output under formula；
The input end of clock of the offset voltage calibration circuit connects the output end of pulse-modulator, the number of offset voltage calibration circuit
According to the output end of input termination register logic unit, offset voltage calibration circuit is used to calculate offset voltage and control digital-to-analogue to turn
The switch of parallel operation.
2. a kind of high speed dynamic comparer offset voltage calibration circuit according to claim 1, it is characterised in that the mistake
Voltage calibration circuit is adjusted to include subtracter, register and switching logic；Wherein：
The input signal of subtracter includes subtrahend and minuend, and the input of subtrahend is connected with the output end of register logic unit
Connect；Output data level when the voltage of minuend is zero for input voltage；
The input of register is connected with the output end of subtracter, by external control signal control register；
Switching logic input is connected with register output end, and switching logic output end is connected with digital to analog converter.
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| CN201611024728.3A CN106533443B (en) | 2016-11-16 | 2016-11-16 | A kind of high speed dynamic comparer offset voltage calibration circuit |
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| CN201611024728.3A CN106533443B (en) | 2016-11-16 | 2016-11-16 | A kind of high speed dynamic comparer offset voltage calibration circuit |
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| CN106533443B CN106533443B (en) | 2019-01-22 |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108141219A (en) * | 2017-12-12 | 2018-06-08 | 深圳市汇顶科技股份有限公司 | For the method and analog-digital converter of analog-to-digital conversion |
| CN108519115A (en) * | 2018-03-14 | 2018-09-11 | 无锡思泰迪半导体有限公司 | A kind of offset voltage bearing calibration applied to hall device |
| CN109120268A (en) * | 2018-08-28 | 2019-01-01 | 电子科技大学 | A kind of dynamic comparer offset voltage calibration method |
| CN109586696A (en) * | 2018-11-30 | 2019-04-05 | 西安电子科技大学 | Offset voltage correcting circuit for dynamic comparer |
| CN110149117A (en) * | 2019-07-05 | 2019-08-20 | 成都博思微科技有限公司 | A kind of self calibration comparator imbalance voltage cancellation circuit |
| CN110286405A (en) * | 2019-07-10 | 2019-09-27 | 中国科学院近代物理研究所 | A kind of caliberating device of deep space probe system and application |
| CN110914653A (en) * | 2017-07-26 | 2020-03-24 | ams国际有限公司 | Optical sensor device and method for optical sensing |
| CN111262561A (en) * | 2020-02-05 | 2020-06-09 | 电子科技大学 | Metastable state detection circuit of comparator |
| CN113607329A (en) * | 2021-07-13 | 2021-11-05 | 复旦大学 | Pressure sensor signal temperature compensation method and pressure sensor |
| CN115913229A (en) * | 2022-12-15 | 2023-04-04 | 江苏润石科技有限公司 | Dynamic configuration method and circuit of comparator of SAR ADC, SAR ADC and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030063020A1 (en) * | 2001-10-01 | 2003-04-03 | Masenas Charles J. | Method and circuit for dynamic calibration of flash analog to digital converters |
| CN102118168A (en) * | 2011-04-08 | 2011-07-06 | 中国科学院半导体研究所 | Sequential-approximation analog-digital converter based on multi-bit serial conversion |
| CN104242942A (en) * | 2014-09-29 | 2014-12-24 | 清华大学 | Six-bit asynchronous successive approximation analog-digital converter with comparator offset calibration function |
| US9048860B1 (en) * | 2014-06-05 | 2015-06-02 | Xilinx, Inc. | Successive approximation analog-to-digital conversion |
| US20160099722A1 (en) * | 2014-10-07 | 2016-04-07 | Realtek Semiconductor Corp. | Method and apparatus for calibrating comparator offset of successive-approximation-register analog-to-digital converter |
| CN105959006A (en) * | 2016-04-27 | 2016-09-21 | 上海华虹宏力半导体制造有限公司 | Successive approximation type analog-to-digital converter calibration circuit |
-
2016
- 2016-11-16 CN CN201611024728.3A patent/CN106533443B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030063020A1 (en) * | 2001-10-01 | 2003-04-03 | Masenas Charles J. | Method and circuit for dynamic calibration of flash analog to digital converters |
| CN102118168A (en) * | 2011-04-08 | 2011-07-06 | 中国科学院半导体研究所 | Sequential-approximation analog-digital converter based on multi-bit serial conversion |
| US9048860B1 (en) * | 2014-06-05 | 2015-06-02 | Xilinx, Inc. | Successive approximation analog-to-digital conversion |
| CN104242942A (en) * | 2014-09-29 | 2014-12-24 | 清华大学 | Six-bit asynchronous successive approximation analog-digital converter with comparator offset calibration function |
| US20160099722A1 (en) * | 2014-10-07 | 2016-04-07 | Realtek Semiconductor Corp. | Method and apparatus for calibrating comparator offset of successive-approximation-register analog-to-digital converter |
| CN105959006A (en) * | 2016-04-27 | 2016-09-21 | 上海华虹宏力半导体制造有限公司 | Successive approximation type analog-to-digital converter calibration circuit |
Non-Patent Citations (2)
| Title |
|---|
| BOB VERBRUGGEN等: ""A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS"", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| 李鹏等: ""一种高速高精度比较器的设计"", 《集成电路设计与开发》 * |
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| CN110914653B (en) * | 2017-07-26 | 2022-04-01 | ams国际有限公司 | Optical sensor device and method for optical sensing |
| CN110914653A (en) * | 2017-07-26 | 2020-03-24 | ams国际有限公司 | Optical sensor device and method for optical sensing |
| US11326942B2 (en) | 2017-07-26 | 2022-05-10 | Ams International Ag | Optical sensor arrangement and method for light sensing |
| CN108141219B (en) * | 2017-12-12 | 2021-07-09 | 深圳市汇顶科技股份有限公司 | Method for analog-to-digital conversion and analog-to-digital converter |
| WO2019113772A1 (en) * | 2017-12-12 | 2019-06-20 | 深圳市汇顶科技股份有限公司 | Method for analog-digital conversion and analog-digital converter |
| CN108141219A (en) * | 2017-12-12 | 2018-06-08 | 深圳市汇顶科技股份有限公司 | For the method and analog-digital converter of analog-to-digital conversion |
| CN108519115A (en) * | 2018-03-14 | 2018-09-11 | 无锡思泰迪半导体有限公司 | A kind of offset voltage bearing calibration applied to hall device |
| CN108519115B (en) * | 2018-03-14 | 2020-09-15 | 无锡思泰迪半导体有限公司 | Offset voltage correction method applied to Hall device |
| CN109120268A (en) * | 2018-08-28 | 2019-01-01 | 电子科技大学 | A kind of dynamic comparer offset voltage calibration method |
| CN109586696A (en) * | 2018-11-30 | 2019-04-05 | 西安电子科技大学 | Offset voltage correcting circuit for dynamic comparer |
| CN110149117A (en) * | 2019-07-05 | 2019-08-20 | 成都博思微科技有限公司 | A kind of self calibration comparator imbalance voltage cancellation circuit |
| CN110286405A (en) * | 2019-07-10 | 2019-09-27 | 中国科学院近代物理研究所 | A kind of caliberating device of deep space probe system and application |
| CN110286405B (en) * | 2019-07-10 | 2020-09-15 | 中国科学院近代物理研究所 | Application of calibration device of deep space detector system |
| CN111262561A (en) * | 2020-02-05 | 2020-06-09 | 电子科技大学 | Metastable state detection circuit of comparator |
| CN111262561B (en) * | 2020-02-05 | 2023-03-31 | 电子科技大学 | Metastable state detection circuit of comparator |
| CN113607329A (en) * | 2021-07-13 | 2021-11-05 | 复旦大学 | Pressure sensor signal temperature compensation method and pressure sensor |
| CN115913229A (en) * | 2022-12-15 | 2023-04-04 | 江苏润石科技有限公司 | Dynamic configuration method and circuit of comparator of SAR ADC, SAR ADC and chip |
| CN115913229B (en) * | 2022-12-15 | 2023-10-03 | 江苏润石科技有限公司 | Dynamic configuration method and circuit of comparator of SAR ADC, SAR ADC and chip |
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